CN106158610B - Floating gate structure, method for fabricating the same, and flash memory including the same - Google Patents

Abstract

This application provides a kind of FGS floating gate structure, its production method and including its flash memory.The production method includes: offer substrate, and substrate has p-well region；The successively tunnel oxide far from substrate, the first polysilicon layer and mask layer are set on the surface for being provided with p-well region of substrate；It is sequentially etched mask layer, the first polysilicon layer, tunnel oxide and substrate and forms shallow trench；On the side wall and bottom surface of shallow trench, laying is set, doped with P-type ion in laying on mask layer；Spacer material layer is set on laying；It anneals to laying and spacer material layer, the first polysilicon layer end adjacent with laying forms the doped polysilicon area doped with P-type ion, and the first polysilicon layer and doped polysilicon area constitute floating gate；And more than removal mask layer laying and spacer material layer.The production method can be realized higher program speed, lower cut-in voltage and reliable data storage effect.

Description

Floating gate structure, method for fabricating the same, and flash memory including the same

technical field

The present application relates to the technical field of semiconductor manufacturing, and in particular, to a floating gate structure, a method for fabricating the same, and a flash memory including the same.

Background technique

A method for fabricating a floating gate and a shallow trench isolation structure in a flash memory generally includes a process of firstly fabricating a shallow trench isolation structure and then depositing polysilicon, and a process of first depositing polysilicon and then fabricating the shallow trench isolation structure. Among them, FIG. 1 shows a schematic flowchart of a method for manufacturing a flash memory in the prior art. First, ion implantation is performed on the silicon substrate 100', and the P-well region 101' shown in FIG. 2 is formed on the silicon substrate 100'; then, the surface of the formed P-well region 101' is grown as shown in FIG. 3 . The tunnel oxide layer 102' is formed, and the first polysilicon layer 103' and the silicon nitride layer 104' shown in FIG. 3 are sequentially formed on the tunnel oxide layer 102'; 104', the first polysilicon layer 103' and the silicon substrate 100' are etched to obtain the trench 200' shown in FIG. 4; Carbon-doped silicon nitride is deposited on the silicon layer 104' to form a liner layer 105' shown in FIG. 5; an isolation material is deposited on the liner layer 105' shown in FIG. 5 to fill the trench 200', and the isolation The material is annealed and planarized to form the isolation material layer 106 ′ shown in FIG. 6 ; then the liner layer 105 ′ and the isolation material layer 106 ′ above the silicon nitride layer 104 ′ are removed to obtain the shallow trench shown in FIG. 7 trench isolation structure 300 ′; after forming the shallow trench isolation structure 300 ′, the shallow trench isolation structure 300 ′ shown in FIG. 7 is thinned, and the silicon nitride layer 104 ′ is removed to obtain the device with the cross-sectional structure shown in FIG. 8 ; Then the ONO layer 107' and the second polysilicon layer 108' shown in Figure 9 are formed on the first polysilicon layer 103' and the exposed shallow trench isolation structure 300' shown in Figure 8; The second polysilicon layer 108', the ONO layer 107', the first polysilicon layer 103' and the tunnel oxide layer 102' are etched to form the gate structure 400' shown in FIG. 10, wherein, The first polysilicon layer 103' serves as a floating gate, and the second polysilicon layer 108' serves as a control gate.

In the process of diffusion annealing the isolation material, the atomic radius of the ions implanted in the P well region 101 ′, such as boron ions, is very small, and it is easy to form a gap to diffuse into the shallow trench isolation structure 300 ′, and the diffusion reduces in the P well region. The concentration of dopant ions, which in turn affects the turn-on voltage of semiconductor devices. Although the liner layer 105' is provided in the prior art to prevent boron from diffusing into the shallow trench isolation structure 300', the ability to control the diffusion is limited, and the diffusion phenomenon is still difficult to control under the condition that the size of semiconductor devices continues to decrease. However, since the diffusion is difficult to control, the turn-on voltages of multiple semiconductor devices in the integrated circuit are different, resulting in different start times and unstable operation, thereby affecting the yield and stability of the integrated circuit.

SUMMARY OF THE INVENTION

The present application aims to provide a floating gate structure, a method for fabricating the same, and a flash memory including the same, so as to solve the problem of unstable turn-on voltage of integrated circuits caused by the diffusion of impurity ions in the P-well to the shallow trench isolation structure in the prior art.

In order to achieve the above object, according to an aspect of the present application, a method for fabricating a floating gate structure is provided, the fabrication method comprising: providing a substrate, the substrate having a P-well region; and on a surface of the substrate provided with the P-well region A tunnel oxide layer, a first polysilicon layer and a mask layer are arranged on the substrate in sequence; the mask layer, the first polysilicon layer, the tunnel oxide layer and the substrate are sequentially etched to form shallow trenches; A liner layer is arranged on the sidewall and bottom surface of the shallow trench and on the mask layer, and the liner layer is doped with P-type ions; an isolation material layer is arranged on the liner layer; the liner layer and the isolation material layer are annealed , a doped polysilicon region doped with P-type ions is formed at the adjacent end of the first polysilicon layer and the liner layer, and the first polysilicon layer and the doped polysilicon region constitute a floating gate; and the mask layer is removed The above liner layer and isolation material layer form a shallow trench isolation structure.

Further, the impurity ions in the P-well region are boron, and the P-type ions in the liner layer are boron ions.

Further, the molar concentration of P-type ions in the liner layer is 1E12˜1E14 atoms/cm ³ .

Further, the thickness of the backing layer is 20-200 nm.

Further, the liner layer is formed by an in-situ steam generation process. In the in-situ steam generation process, tetramethylsilane, oxygen and boron fluoride are used as reaction gases, wherein the flow rate of tetramethylsilane is 2000-4000 sccm, and the oxygen The flow rate is 4000-6000 sccm, the flow rate of boron fluoride is 3000-4000 sccm, and the deposition temperature is 600-800 ℃.

Furthermore, the annealing temperature of annealing is 700-900 degreeC.

Further, disposing the isolation material layer on the liner layer is performed using a high aspect ratio filling process.

Further, the isolation material layer is a silicon dioxide layer, and during the implementation of the high aspect ratio filling process, the deposition temperature is 300-500° C., the deposition gas includes TEOS, O ₂ and O ₃ , and the volume ratio of TEOS and O ₂ is 1:3～1:25, the volume ratio of TEOS and O ₃ is 1:1～1:30.

Further, the process of removing the liner layer and the isolation material layer above the mask layer includes: chemical mechanical planarization of the isolation material layer above the liner layer; etching to remove the liner layer above the mask layer; etching to remove A layer of isolation material above the mask layer.

Further, the liner layer above the mask layer is removed by etching using an etching substance including phosphoric acid.

Further, the isolation material layer above the mask layer is removed by etching using an etching substance including hydrofluoric acid.

Further, after removing the liner layer and the isolation material layer above the mask layer, the manufacturing method further includes: thinning the isolation material layer and the liner layer; removing the mask layer to form a shallow trench isolation structure.

Further, the etching substance for thinning the isolation material layer and the liner layer includes a mixed solution of hydrofluoric acid and phosphoric acid, wherein the volume fraction of hydrofluoric acid is 20% to 45%, and the etching temperature is 25 to 60° C. The etching time is 1 to 3 minutes.

The present application also provides a floating gate structure, the floating gate structure includes a substrate and a P well region disposed in the substrate, and a shallow trench isolation structure is provided in the P well region, and between adjacent shallow trench isolation structures A tunnel oxide layer and a floating gate are sequentially arranged on the surface of the substrate, and the shallow trench isolation structure includes a liner layer and an isolation material layer, and the liner layer is doped with P-type ions; the floating gate includes a first polycrystalline The silicon layer and the doped polysilicon region doped with P-type ions are disposed between the first polysilicon layer and the pad layer.

Further, the P-type ions are boron ions.

The present application also provides a flash memory, characterized in that the flash memory includes the above floating gate structure, an isolation oxide layer and a control gate disposed on the floating gate in the floating gate structure.

By applying the technical solution of the present application, P-type ions are doped in the liner layer of the shallow trench isolation structure, and then when the liner layer and the isolation material layer are annealed, the P-type ions will be directed to the substrate and the first multi-layered ions. Diffusion in the crystalline silicon layer, on the one hand, makes up for the loss caused by the diffusion of impurity ions in the P-well region of the substrate, and avoids the loss of turn-on voltage caused by diffusion; on the other hand, the P-type ions diffused into the first polysilicon layer P-type regions will be formed at both ends of the width direction of the first polysilicon layer, so that the first polysilicon layer will form a P-N-P structure in the width direction. The presence of ions reduces the barrier for electron movement, which in turn enables higher programming speeds, lower turn-on voltages, and reliable data storage.

Description of drawings

The accompanying drawings that form a part of the present application are used to provide further understanding of the present application, and the schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute improper limitations on the present application. In the attached image:

Fig. 1 shows the manufacturing process flow chart of flash memory in the prior art;

FIG. 2 to FIG. 10 are schematic diagrams showing the cross-sectional structure of the device after each process in FIG. 1 is executed, wherein,

FIG. 2 shows a schematic cross-sectional structure diagram after ion implantation is performed on a silicon substrate to form a P well region;

3 shows a schematic cross-sectional structure diagram of growing a tunnel oxide layer on the surface of the P-well region shown in FIG. 2 and sequentially forming a first polysilicon layer and a silicon nitride layer on the tunnel oxide layer;

FIG. 4 shows a schematic cross-sectional structure diagram after etching the silicon nitride layer, the first polysilicon layer and the silicon substrate shown in FIG. 3 to obtain a trench;

FIG. 5 shows a schematic cross-sectional structure of the sidewall and bottom surface of the trench shown in FIG. 4 and the silicon nitride layer after depositing carbon-doped silicon nitride to form a liner layer;

6 shows a schematic cross-sectional structure diagram of depositing an isolation material on the liner layer shown in FIG. 5 to fill the trenches, and performing annealing and planarization processing on the isolation material to form an isolation material layer;

FIG. 7 shows a schematic cross-sectional structure diagram after removing the liner layer and the isolation material layer above the silicon nitride layer shown in FIG. 6 to obtain a shallow trench isolation structure;

FIG. 8 shows a schematic cross-sectional structure diagram of the shallow trench isolation structure shown in FIG. 7 after thinning and removing the silicon nitride layer;

9 shows a schematic cross-sectional structure diagram of forming an ONO layer and a second polysilicon layer on the first polysilicon layer and the exposed shallow trench isolation structure shown in FIG. 8;

FIG. 10 shows a schematic cross-sectional structure diagram after etching the second polysilicon layer, the ONO layer, the first polysilicon layer and the tunnel oxide layer shown in FIG. 9 to form a gate structure;

FIG. 11 shows a schematic flowchart of a method for fabricating a floating gate structure provided by a preferred embodiment of the present application;

FIG. 12 to FIG. 20 show schematic cross-sectional structures of the device after each process of the manufacturing method shown in FIG. 11 is implemented, wherein,

Figure 12 shows a schematic cross-sectional structure of the provided substrate, the substrate having a P-well region;

FIG. 13 shows a schematic cross-sectional structure diagram of a tunnel oxide layer, a first polysilicon layer, and a mask layer that are arranged in sequence away from the substrate on the surface of the substrate shown in FIG. 12 on which the P-well region is provided;

FIG. 14 is a schematic cross-sectional structure diagram of forming a shallow trench by sequentially etching the mask layer, the first polysilicon layer, the tunnel oxide layer and the substrate shown in FIG. 13;

FIG. 15 shows a schematic cross-sectional structure diagram of the sidewall and bottom surface of the shallow trench shown in FIG. 14 and the mask layer after a liner layer is arranged, wherein the liner layer is doped with P-type ions;

Fig. 16 shows a schematic cross-sectional structure diagram after disposing an isolation material layer on the liner layer shown in Fig. 15;

FIG. 17 shows a schematic cross-sectional structure diagram of annealing the liner layer and the isolation material layer shown in FIG. 16 to form a doped polysilicon region;

FIG. 18 shows a schematic cross-sectional structure diagram of the isolation material layer above the liner layer shown in FIG. 17 after chemical mechanical planarization is performed;

FIG. 19 shows a schematic cross-sectional structure diagram after etching and removing the liner layer and the isolation material layer above the mask layer shown in FIG. 18; and

FIG. 20 shows a schematic cross-sectional structure diagram of the isolation material layer and the liner layer shown in FIG. 19 after thinning.

Detailed ways

It should be noted that the following detailed description is exemplary and intended to provide further explanation of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It should be noted that the terminology used herein is for the purpose of describing specific embodiments only, and is not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly dictates otherwise, the singular is intended to include the plural as well, furthermore, it is to be understood that when the terms "comprising" and/or "including" are used in this specification, it indicates that There are features, steps, operations, devices, components and/or combinations thereof.

For ease of description, spatially relative terms, such as "on", "over", "on the surface", "above", etc., may be used herein to describe what is shown in the figures. The spatial positional relationship of one device or feature shown to other devices or features. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or features would then be oriented "below" or "over" the other devices or features under other devices or constructions". Thus, the exemplary term "above" can encompass both an orientation of "above" and "below." The device may also be positioned in other different ways, and the spatially relative descriptions used herein interpreted accordingly.

As described in the background art, the atomic radius of boron ions in the P-well region of the prior art is very small, and it is easy to form gaps and diffuse into the shallow trench isolation structure. The diffusion reduces the concentration of dopant ions in the P-well, thereby affecting the The turn-on voltage of semiconductor devices, and the currently set liner layer has limited ability to control diffusion, and the diffusion phenomenon is still difficult to control, resulting in different turn-on voltages of multiple semiconductor devices in the integrated circuit, which further leads to different start times, unstable operation, affecting Yield and stability of integrated circuits. In order to solve the above problems caused by diffusion, the present application proposes a shallow trench isolation structure, a method for fabricating the same, and a flash memory including the same.

In a preferred embodiment of the present application, a method for fabricating a flash memory structure is provided, wherein FIG. 11 shows the flow of the aforementioned fabrication method. The fabrication method includes: providing a substrate 100, the substrate 100 having a P-well region 101; disposing a tunnel oxide layer 102, a first polycrystalline layer 102 far away from the substrate 100 on the surface of the substrate 100 provided with the P-well region 101 in sequence Silicon layer 103 and mask layer 104; etching mask layer 104, first polysilicon layer 103, tunnel oxide layer 102 and substrate 100 in sequence to form shallow trench 200; on the sidewall and bottom surface of shallow trench 200 A liner layer 105 is arranged on the top and the mask layer 104, and the liner layer 105 is doped with P-type ions; an isolation material layer 106 is arranged on the liner layer 105; the liner layer 105 and the isolation material layer 106 are annealed, An end portion of the first polysilicon layer 103 adjacent to the liner layer 105 forms a doped polysilicon region 131 doped with P-type ions, and the first polysilicon layer 103 and the doped polysilicon region 131 form a floating gate; and removing the liner layer 105 and the isolation material layer 106 above the mask layer 104 to form a shallow trench isolation structure 300 .

The above manufacturing method doped the liner layer 105 of the shallow trench isolation structure with P-type ions, and then when the liner layer 105 and the isolation material layer 106 are annealed, the P-type ions will be directed to the substrate 100 and the first multi-layered ions. Diffusion in the crystalline silicon layer 103, on the one hand, makes up for the loss caused by the diffusion of impurity ions in the P-well region 101 of the substrate 100, and avoids the loss of the turn-on voltage caused by the diffusion; on the other hand, the diffusion into the first polysilicon layer 103 The P-type ions will form a P-type region at the end of the first polysilicon layer 103 in the width direction, so that the first polysilicon layer 103 forms a P-N-P structure in the width direction. There are electrons in the P region, and the existence of the P region will reduce the potential barrier for electron movement, thereby enabling higher programming speed, lower turn-on voltage and reliable data storage effect. It should be noted here that the width direction referred to in this application is the same as the width direction generally understood by those skilled in the art, and both refer to the direction along which the shallow trench isolation structures are arranged on the surface of the substrate.

It should be clear to those skilled in the art that P-type ions refer to ions that can provide holes, such as boron, aluminum, gallium, and indium. In this application, boron ions are preferred. Therefore, in this application, the impurity ions in the P-well region 101 are preferably boron ions. The P-type ions in the pad layer 105 are boron ions.

Now, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of these exemplary embodiments to those of ordinary skill in the art. In the accompanying drawings, layers are exaggerated for clarity and the thicknesses of the regions, and the same reference numerals are used to denote the same devices, and thus their descriptions will be omitted.

First, a substrate 100 as shown in FIG. 12 is provided. The substrate 100 has a P-well region 101, wherein the P-well region 101 can be formed by implanting boron into the substrate 100 by using an ion implantation method commonly used in the art. 100 can be silicon of single crystal, polycrystalline or amorphous structure, or silicon germanium (SiGe), can also be silicon on insulator (SOI), or can also include other materials, such as indium antimonide, lead telluride, arsenic Indium, Indium Phosphide, Gallium Arsenide or Gallium Antimonide. Although a few examples of materials from which substrate 100 can be formed are described herein, any material that can be a semiconductor substrate falls within the spirit and scope of the present invention.

Then, on the substrate 100 shown in FIG. 12 , the tunnel oxide layer 102 , the first polysilicon layer 103 and the mask layer 104 shown in FIG. 13 , which are separated from the substrate 100 in sequence, are provided.

The tunnel oxide layer 102 is formed by thermal oxidation, and the process gas for forming the tunnel oxide layer 102 includes silicon-containing gas and oxygen. The above-mentioned silicon-containing gas is SiH ₂ Cl ₂ or SiH ₂ , which is limited by vacuum conditions. Also includes N ₂ . The thickness of the formed tunnel oxide layer 102 can be If the thickness of the tunnel oxide layer 110 is too large, the distance between the first polysilicon layer 103 (which is subsequently etched to form the floating gate) and the substrate 100 will increase, thereby reducing the distance between the first polysilicon layer 103 and the substrate 100 . The capacitance between the substrates 100 reduces the efficiency of reading, writing and erasing the flash memory. In a preferred embodiment, the formed tunnel oxide layer 102 can also be annealed. The above-mentioned formation process of the first polysilicon layer 103 and the mask layer 104 can be a chemical vapor deposition process, a physical vapor deposition process, or a plasma deposition process, preferably a chemical vapor deposition process, and the thickness of the first polysilicon layer 120 can be for preferred The above-mentioned mask layer 104 is preferably a silicon nitride layer. On the one hand, the mask layer 104 is used to protect the first polysilicon layer 103 from damage during the process of etching to form the shallow trench 200, and on the other hand, it can be used as a follow-up removal. Stop layer for substrate layer 105 and isolation material layer 106 .

After the mask layer 104 is formed, the mask layer 104 shown in FIG. 13 , the first polysilicon layer 103 , the tunnel oxide layer 102 and the substrate 100 are sequentially etched to form the shallow trench 200 shown in FIG. 14 . The above-mentioned etching process can adopt the etching process commonly used in the art, for example, firstly, a photoresist is arranged on the surface of the mask layer 104, and then the photoresist is patterned to form a photoresist mask containing openings, wherein the openings are formed. The position and width of the trench correspond to the position and width of the subsequently formed shallow trench; then the mask layer 104, the first polysilicon layer 103, the tunnel oxide layer 102, and the substrate 100 are etched along the opening in sequence until the lining A shallow trench 200 with a predetermined depth is formed in the bottom 100 .

The above-mentioned etching can be etched by methods well known to those skilled in the art, such as chemical wet etching and dry etching, preferably plasma dry etching, wherein the use of argon gas Ar and tetrafluoromethane CF ₄ , hexafluoromethane is used. A mixed gas of fluorine-containing gas such as fluoroethane C ₂ F ₆ and trifluoromethane CHF ₃ is used as the etching gas, in which argon Ar plays the role of diluting the etching gas, and its flow rate is 100-300sccm; The flow rate of tetrafluoromethane CF ₄ is 50-100 sccm, the flow rate of hexafluoroethane C ₂ F ₆ is 100-400 sccm, and the flow rate of trifluoromethane CHF ₃ is 10-100 sccm, and the gas ionization is set as the radio frequency power source of the plasma The output power is 50-1000W; the output power of the radio frequency bias power source is 50-250W; the pressure in the reaction chamber is set at 50-200mTorr, and the substrate temperature is controlled between 20-90°C. The above-mentioned plasma etching process is anisotropic etching, and the etching process can be implemented by inductively coupled plasma type etching equipment, capacitively coupled plasma type etching equipment, and inductively coupled plasma etching equipment.

After the shallow trench 200 is formed, the liner layer 105 shown in FIG. 15 is provided on the sidewall and bottom surface of the shallow trench 200 shown in FIG. 14 and on the mask layer 104, wherein the liner layer 105 is doped There are P-type ions. The pad layer 105 of the present application meets the requirements of the pad layer of the current conventional technology, and the doping of P-type ions will not affect its performance, so the thickness of the pad layer 105 is preferably 20-200 nm; The concentration of ions is 1E12 to 1E14 atoms/cm ³ .

The above-mentioned processes for disposing the liner layer 105 include, but are not limited to, chemical vapor deposition, thermal oxidation, and wet oxygen oxidation. In the present application, low-pressure chemical vapor deposition or in-situ steam generation is preferred. When the in-situ steam generation process is adopted, preferably, tetramethylsilane, oxygen and boron fluoride are used as reaction gases, wherein the flow rate of tetramethylsilane is 2000-4000 sccm, the flow rate of oxygen is 4000-6000 sccm, and the flow rate of boron fluoride is 2000-4000 sccm. The flow rate is 3000～4000sccm, and the deposition temperature is 600～800℃. The in-situ steam generation process is a wet oxygen oxidation process, the oxidation speed is fast, the reaction time is very short, and can be completed within 10s, so the oxygen in the reaction gas is between the first polysilicon layer 103 and the tunnel oxide layer 102 And the amount of diffusion between the tunnel oxide layer 102 and the substrate 100 is very small, so as to avoid the formation of oxidation due to the reaction between the oxygen in the reactive gas and the substrate 100 and the first polysilicon layer 103 on both sides of the shallow trench 200 thing.

After the spacer layer 105 is formed, the insulating material layer 106 shown in FIG. 16 is provided on the spacer layer 105 shown in FIG. 15 . The isolation material used to form the isolation material layer 106 in the present application may be one or more of silicon dioxide, fluorosilicate glass, undoped silicate glass (USG) or tetraethyl orthosilicate. In order to improve isolation The filling effect of the material layer 106 is preferably implemented by setting the isolation material layer 106 on the liner layer 105 by a high aspect ratio filling process. Preferably, the isolation material layer 106 is a silicon dioxide layer, and the deposition temperature is 300-500° C. It includes TEOS, O ₂ and O ₃ , and the volume ratio of TEOS and O ₂ is 1:3-1:25, and the volume ratio of TEOS and O ₃ is 1:1-1:30.

After the above-mentioned setting of the isolation material layer 106 is completed, the liner layer 105 and the isolation material layer 106 shown in FIG. 16 are annealed to form the doped polysilicon region 131 shown in FIG. 17 . The annealing temperature of the above-mentioned annealing is preferably 800 to 900°C. During the annealing process, the P-type ions doped in the liner layer 105 will diffuse into the first polysilicon layer 103 and the substrate 100 , and the impurity ions in the P-well region 101 will also diffuse into the liner layer 105 , so the diffusion between the ions in the liner layer 105 and the P-well region 101 balances each other, so that the ions in the P-well region 101 are not reduced due to diffusion; instead, they diffuse into the first polysilicon layer 103 from the liner layer 105 The P-type ions formed in the first polysilicon layer 103 form a doped polysilicon region 131 doped with P-type ions. As described above, the formed doped polysilicon region 131 and the first polysilicon layer 103 The main part of the formed P-N-P structure.

After the above annealing process is completed, the liner layer 105 and the isolation material layer 106 above the mask layer 104 shown in FIG. 17 are removed to form the shallow trench isolation structure 300 shown in FIG. 19 . In a preferred implementation process of the present application, preferably the above-mentioned process of removing the liner layer 105 and the isolation material layer 106 includes: chemical mechanical planarization of the isolation material layer 106 above the liner layer 105 shown in FIG. 17 to obtain The device with the cross-sectional structure shown in FIG. 18; the liner layer 105 above the mask layer 104 shown in FIG. 18 is removed by etching; the isolation material layer 106 above the mask layer 104 shown in FIG. 18 is removed by etching to form a diagram of Shallow trench isolation structure 300 shown at 19.

The above chemical mechanical planarization process uses the mask layer 102 as its stop layer; when removing the liner layer 105 above the mask layer 104, it is preferable to use an etching substance including phosphoric acid to etch the liner layer 104; remove the mask The isolation material layer 106 above the layer 104 is preferably etched with an etching substance including hydrofluoric acid; The selectivity to various etching objects is optimized, and the etching effect is optimized.

In the fabrication of semiconductor devices, some liner layers 105 and isolation material layers 106 need to be thinned after the above process is completed. Therefore, in order to meet the requirements of specific semiconductor devices for the shallow trench isolation structure 300, the preferred After removing the liner layer 105 and the isolation material layer 106 above the mask layer 104, the above manufacturing method further includes thinning the isolation material layer 106 and the liner layer 105 shown in FIG. 19 to form a device with the cross-sectional structure shown in FIG. 20 . ; Remove the mask layer 104 shown in FIG. 20 to form a shallow trench isolation structure 300 .

The above process of thinning the isolation material layer 106 and the liner layer 105 is removed by using an etching solution including phosphoric acid and hydrofluoric acid, wherein, preferably, the volume fraction of hydrofluoric acid is 20% to 45%, and the etching temperature is 25～60℃, the etching time is 1～3min. When removing the mask layer 104, the mask layer 104 is preferably etched using an etching substance including phosphoric acid.

The present application also provides a floating gate structure, as shown in FIG. 20 , the floating gate structure includes a substrate 100 and a P-well region 101 disposed in the substrate 100 , and a shallow trench isolation structure is disposed in the P-well region 101 , a tunnel oxide layer 102 and a floating gate are sequentially disposed on the surface of the substrate 100 between adjacent shallow trench isolation structures, and the shallow trench isolation structure includes a liner layer 105 and an isolation material layer 106, and the liner layer 105 P-type ions are doped inside; the floating gate includes a first polysilicon layer 103 disposed on the tunnel oxide layer 102 and a doped polysilicon region 131 doped with P-type ions, and the doped polysilicon region 131 is disposed on the first polysilicon layer 103 . Between a polysilicon layer 103 and the pad layer 105 .

Further, the P-type ions are boron ions.

The present application also provides a flash memory, characterized in that the flash memory includes the above floating gate structure, an isolation oxide layer and a control gate disposed on the floating gate in the floating gate structure.

From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

1), the above-mentioned manufacturing method doped P-type ions in the liner layer of the shallow trench isolation structure, and then when the liner layer and the isolation material layer are annealed, the P-type ions will be directed to the substrate and the first polycrystalline Diffusion in the silicon layer, on the one hand, makes up for the loss caused by the diffusion of impurity ions in the P-well region of the substrate, and avoids the loss of turn-on voltage caused by diffusion;

2) On the other hand, P-type ions in the liner layer diffuse into the first polysilicon layer to form P-type regions at both ends of the first polysilicon layer, so that the first polysilicon layer is formed in the width direction In the P-N-P structure, due to the existence of electrons in the N region in the first polysilicon layer, the existence of the P region will reduce the potential barrier for electron movement, thereby enabling higher programming speed, lower turn-on voltage and reliable data storage effect. .

The above are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (15)

1. a manufacturing method of a floating gate structure, wherein the manufacturing method comprises: providing a substrate having a P-well region; A tunnel oxide layer, a first polysilicon layer and a mask layer are arranged on the surface of the substrate on which the P well region is disposed in sequence, and the first polysilicon layer is N type polysilicon layer; etching the mask layer, the first polysilicon layer, the tunnel oxide layer and the substrate in sequence to form shallow trenches; A liner layer is provided on the sidewall and bottom surface of the shallow trench and on the mask layer, the liner layer is doped with P-type ions, and the molar concentration of the P-type ions in the liner layer is 1E12～1E14atoms/cm ³ ; disposing a layer of insulating material on the backing layer; The liner layer and the isolation material layer are annealed, an end of the first polysilicon layer adjacent to the liner layer forms a doped polysilicon region doped with P-type ions, and the the first polysilicon layer and the doped polysilicon region form a floating gate; and The liner layer and the isolation material layer above the mask layer are removed to form a shallow trench isolation structure. 2 . The method for fabricating a floating gate structure according to claim 1 , wherein the impurity ions in the P-well region are boron, and the P-type ions in the liner layer are boron ions. 3 . 3 . The manufacturing method of the floating gate structure according to claim 1 , wherein the thickness of the pad layer is 20-200 nm. 4 . 4 . The manufacturing method of the floating gate structure according to claim 1 , wherein the liner layer is formed by an in-situ steam generation process, and in the in-situ steam generation process, tetramethylsilane, oxygen and Boron fluoride is a reactive gas, wherein the flow rate of tetramethylsilane is 2000-4000 sccm, the flow rate of oxygen is 4000-6000 sccm, the flow rate of boron fluoride is 3000-4000 sccm, and the deposition temperature is 600-800 ℃. 5 . The manufacturing method of the floating gate structure according to claim 1 , wherein the annealing temperature of the annealing is 700˜900° C. 6 . 6 . The method for fabricating a floating gate structure according to claim 1 , wherein disposing the isolation material layer on the liner layer is implemented by a high aspect ratio filling process. 7 . 7 . The method for manufacturing a floating gate structure according to claim 6 , wherein the isolation material layer is a silicon dioxide layer, and during the implementation of the high aspect ratio filling process, the deposition temperature is 300-500° C. 8 . , the deposition gas includes TEOS, O ₂ and O ₃ , and the volume ratio of TEOS and O ₂ is 1:3-1:25, and the volume ratio of TEOS and O ₃ is 1:1-1:30. 8. The method for fabricating a floating gate structure according to claim 1, wherein the process of removing the liner layer and the isolation material layer above the mask layer comprises: chemical mechanical planarization of the isolation material layer above the liner layer; Etching and removing the liner layer above the mask layer; The isolation material layer above the mask layer is removed by etching. 9 . The manufacturing method of the floating gate structure according to claim 8 , wherein the liner layer above the mask layer is removed by etching using an etching substance comprising phosphoric acid. 10 . 10 . The manufacturing method of the floating gate structure according to claim 8 , wherein the isolation material layer above the mask layer is removed by etching using an etching substance comprising hydrofluoric acid. 11 . 11 . The manufacturing method of the floating gate structure according to claim 1 , wherein after removing the liner layer and the isolation material layer above the mask layer, the manufacturing method further comprises: 11 . thinning the insulating material layer and the backing layer; The mask layer is removed to form a shallow trench isolation structure. 12 . The method for fabricating a floating gate structure according to claim 11 , wherein the etching substance for thinning the isolation material layer and the liner layer comprises a mixture of hydrofluoric acid and phosphoric acid, wherein hydrofluoric acid The volume fraction of acid is 20% to 45%, the etching temperature is 25 to 60° C., and the etching time is 1 to 3 minutes. 13. A floating gate structure, the floating gate structure comprising a substrate and a P-well region disposed in the substrate, and a shallow trench isolation structure is disposed in the P-well region, adjacent to the shallow trenches A tunnel oxide layer and a floating gate are sequentially arranged on the surface of the substrate between the isolation structures, wherein the shallow trench isolation structure includes a liner layer and an isolation material layer, and the liner layer is doped with doped with P-type ions; the floating gate includes a first polysilicon layer disposed on the tunnel oxide layer and a doped polysilicon region doped with P-type ions, and the doped polysilicon region is disposed on the Between the first polysilicon layer and the liner layer, the first polysilicon layer is an N-type polysilicon layer, and the molar concentration of P-type ions in the liner layer is 1E12-1E14 atoms/cm ³ . 14. The floating gate structure of claim 13, wherein the P-type ions are boron ions. 15. A flash memory, characterized in that the flash memory comprises the floating gate structure of claim 13 or 14, and an isolation oxide layer and a control gate disposed on the floating gate in the floating gate structure.