CN106201802A - The CPU internal interrupt response time of logic-based analyser and the measuring method of recovery time - Google Patents

Abstract

The present invention relates to a kind of measurement method of interrupt response time and recovery time inside CPU based on logic analyzer, it comprises the following steps: S1, CPU is respectively matched and connected with logic analyzer through GPIO1 port, GPIO2 port; Step S2, in software can Before triggering the interrupt trigger, flip the level of the GPIO1 port; step S3, trigger the selected software to trigger the interrupt, and flip the level signal of the GPIO1 port N times continuously; step S4, after the above software can trigger the interrupt recovery and GPIO1 After the level changes, the logic analyzer stops collecting the level signals corresponding to GPIO1 and GPIO2, and analyzes and records the level signals corresponding to GPIO1 and GPIO2 to determine the interrupt response time T1 and recovery time T2. The invention is easy to operate, can realize the accurate measurement of the interrupt response time and recovery time inside the CPU, and avoids the deviation of the system running time and timing analysis.

Description

Measurement of Interrupt Response Time and Recovery Time of CPU Based on Logic Analyzer method

technical field

The invention relates to a measurement method, in particular to a method for measuring interrupt response time and recovery time inside a CPU based on a logic analyzer.

Background technique

At present, domestic engine control software, whether it is software using multiple interrupt frameworks or software using real-time operating systems, cannot avoid the use of CPU internal interrupts, such as timer interrupts that come with the CPU or other soft interrupts triggered by instructions, and These internal interrupts usually play important roles, such as tick interrupts for real-time scheduling.

Interrupt response time and recovery time are one of the most important performance indicators of real-time operating systems or multiple interrupt systems. Interrupt response time refers to the time between when an interrupt request is generated and the processor (CPU) starts processing the user program. Interrupt recovery time refers to The time it takes the processor to return to the interrupted code. Interrupt response time and recovery time reflect the system's response speed to external events, which is of great significance for analyzing the real-time performance of real-time systems, especially for systems with interrupt switching frequency, the greater the system running time occupied by these two times. The accurate measurement of interrupt response time and recovery time not only provides an important reference for the early stage architecture design of the control software, but also is directly related to the performance of the later controller products.

Although the limited technical information of foreign engine control software also mentions that the operating system uses CPU internal interrupts, no specific guidance and implementation methods for interrupt measurement have been found. Domestic engine control software has not paid enough attention to the performance of interrupt response time and recovery time before, and there is no clear guidance method for their measurement, and the difficulty of measuring these two indicators of CPU internal interrupt It lies in the capture of interrupt request events and interrupt return time points, unlike external interrupts that have interrupt request hardware signals that can be observed. The measurement method of program running time in other industries is to use the built-in timer of the CPU to measure. It can achieve accurate results for the time measurement of ordinary sequence execution, but for the measurement of the two time indicators of internal interrupts, due to the lack of The capture of measurement points will cause a great loss of accuracy.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, to provide a kind of measurement method based on the interrupt response time and recovery time of the CPU inside the logic analyzer, which is easy to operate, and can realize the measurement of the interrupt response time and the recovery time inside the CPU. Accurate measurement, reducing the deviation of system running time and timing analysis, safe and reliable.

According to the technical scheme provided by the present invention, a kind of measuring method based on logic analyzer interrupt response time and recovery time inside CPU, described measuring method comprises the steps:

S1. Select two GPIO ports of the CPU, and configure the selected two GPIO ports as general-purpose output interfaces and initialize them as low-level outputs. The two GPIO ports are respectively marked as GPIO1 ports and GPIO2 ports; the CPU passes GPIO1 port and GPIO2 port are respectively matched and connected with the logic analyzer. When the level of the GPIO1 port is on the rising edge, the logic analyzer collects and saves the level signals corresponding to the GPIO1 port and GPIO2 port;

Step S2, the software of the selected CPU can trigger an interrupt, and before the software can trigger the interrupt, flip the level of the GPIO1 port, so that the logic analyzer can collect and save the level signals corresponding to the GPIO1 port and the GPIO2 port;

Step S3, triggering the selected software to trigger an interrupt, and flipping the level signal of the GPIO1 port N times continuously, and inserting piles during the interrupt processing, so that the GPIO1 port is flipped at the beginning position of the corresponding soft interrupt processing function. Level, and set the level of GPIO2 port high at the end of the interrupt processing function;

Step S4, after the above-mentioned software can trigger the interrupt recovery and after the GPIO1 level changes, the logic analyzer stops collecting the level signals corresponding to the GPIO1 port and the GPIO2 port, and analyzes the level signals corresponding to the recorded GPIO1 port and the GPIO2 port , to determine the interrupt response time T1 and recovery time T2.

In step S3, after the software triggerable interrupt is triggered, when the level signal of the GPIO1 port is continuously flipped N times, (N-2) * the interval time between flipping the level of the GPIO1 port on both adjacent sides is greater than the triggering time of the software triggerable interrupt The time when the CPU suspends executing the current program instruction, N is greater than or equal to 3.

In step S2, after the software of the selected CPU can trigger an interrupt, other interrupts of the CPU are shielded.

The advantages of the present invention: connect the GPIO1 port and GPIO2 port of the CPU with the logic analyzer, collect and record the level signals corresponding to the GPIO1 port and the GPIO2 port through the logic analyzer, and pass the flip change of the level signals corresponding to the GPIO1 port and the GPIO2 port , can measure the interrupt response time and interrupt recovery time of the CPU internal interrupt, easy to operate, reduce the deviation of system running time and timing analysis, safe and reliable.

Description of drawings

Fig. 1 is a flowchart of the present invention.

Fig. 2 is a schematic diagram of the level signals corresponding to the GPIO1 port and the GPIO2 port collected by the logic analyzer of the present invention.

detailed description

The present invention will be further described below in conjunction with specific drawings and embodiments.

As shown in Figure 1: can realize the accurate measurement to CPU internal interrupt response time and recovery time, avoid the deviation of system running time and sequence analysis, measuring method of the present invention comprises the following steps:

S1. Select two GPIO ports of the CPU, and configure the selected two GPIO ports as general-purpose output interfaces and initialize them as low-level outputs. The two GPIO ports are respectively marked as GPIO1 ports and GPIO2 ports; the CPU passes GPIO1 port and GPIO2 port are respectively matched and connected with the logic analyzer. When the level of the GPIO1 port is on the rising edge, the logic analyzer collects and saves the level signals corresponding to the GPIO1 port and GPIO2 port;

Specifically, for the selected CPU, select two GPIO ports, and configure the selected GPIO port as a general-purpose output interface, and initialize the GPIO port as a specific process for low-level output is well known to those skilled in the art. I won't repeat them here. When the logic analyzer is connected to the CPU, connect the GPIO1 port and GPIO2 port of the CPU to the two connection input channels of the logic analyzer respectively, connect the ground wire of the logic analyzer to the ground wire of the CPU, and connect the specific connection between the logic analyzer and the CPU Coordination is well known to those skilled in the art and will not be repeated here. Generally, the logic analyzer has a high sampling precision, and the working parameters of the logic analyzer can be 100M main frequency and 2ns sampling precision. Since GPIO1 and GPIO2 are initialized as low-level output, after the logic analyzer is connected to the CPU, if and only when the level of GPIO1 is on the rising edge, the logic analyzer will collect and save the output of GPIO1 and GPIO2. The level signal corresponding to the port.

Step S2, the software of the selected CPU can trigger an interrupt, and before the software can trigger the interrupt, flip the level of the GPIO1 port, so that the logic analyzer can collect and save the level signals corresponding to the GPIO1 port and the GPIO2 port;

In the embodiment of the present invention, the software inside the CPU is selected to trigger the interrupt, that is, the corresponding software is run on the CPU, and the corresponding internal interrupt is triggered by the software, so that the measurement of the interrupt response time and recovery time can be realized. After the software of the selected CPU can trigger an interrupt, the remaining interrupts of the CPU can be shielded to avoid the situation of preempting or nesting multiple interrupts. It can be seen from step 1 that since the GPIO1 port is initialized as a low-level output, after flipping the level of the GPIO1 port, the GPIO1 port has a rising edge. At this time, the logic analyzer can realize the corresponding level of the GPIO1 port and GPIO2 port Signal collection and storage.

Step S3, triggering the selected software to trigger an interrupt, and flipping the level signal of the GPIO1 port N times continuously, and inserting piles during the interrupt processing, so that the GPIO1 port is flipped at the beginning position of the corresponding soft interrupt processing function. Level, and set the level of GPIO2 port high at the end of the interrupt processing function;

In the embodiment of the present invention, when the level signal of the GPIO1 port is continuously flipped N times after the software can trigger the interrupt trigger, (N-2) * the interval time between flipping the level of the GPIO1 port on both adjacent sides is longer than the software can trigger the interrupt The time from the trigger until the CPU suspends the execution of the current program instruction, N is greater than or equal to 3. The time from the triggering of the interrupt triggered by the software to the termination of the execution of the current program instruction by the CPU can be obtained from the CPU manual; during specific implementation, the level signal of the GPIO1 port can be reversed through software instructions.

Software triggerable interrupts are triggered by software instructions, and the specific triggering process is well known to those skilled in the art. In the process of interrupt processing, by flipping the level of GPIO1 port at the start position of the corresponding soft interrupt processing function, it is possible to capture the moment when the CPU starts to process the interrupt user program, and by setting the level of GPIO2 port at the end position of the interrupt processing function to High, it is possible to capture the moment when the interrupt user program is executed, and the technical means commonly used in this technical field can be used to implement stubbing during the interrupt processing process. The specific implementation process is well known to those skilled in the art and will not be repeated here.

After triggering the software triggerable interrupt, when flipping the level signal of the GPIO1 port N times in a row, use the Mth flip in the level signal of the N times flipping the GPIO1 port (M=rounding (soft interrupt triggers to CPU suspension) The time to execute the current program instruction/interval time between two flips of CPIO1 + 1), M is greater than or equal to 1) can simulate and capture the generation of interrupt requests inside the CPU, after flipping the level signal of the GPIO1 port for the M time, the CPU enters In the interrupt processing process, through the above time setting, the subsequent flipping of the level signal of the GPIO1 port can capture the time point when the CPU returns to the original program and be used to observe the software execution status after the interrupt resumes.

Step S4, after the above-mentioned software can trigger the interrupt recovery and after the GPIO1 level changes, the logic analyzer stops collecting the level signals corresponding to the GPIO1 port and the GPIO2 port, and analyzes the level signals corresponding to the recorded GPIO1 port and the GPIO2 port , to determine the interrupt response time T1 and recovery time T2.

In the embodiment of the present invention, the sampling of the level signals corresponding to the GPIO1 port and the GPIO2 port by the logic analyzer is limited by the storage capacity of the logic analyzer, but at least it is necessary to ensure the sampling of the level signals corresponding to the GPIO1 port and the GPIO2 port After the software can trigger the interrupt recovery, during specific implementation, the sampling stop condition of the logic analyzer can be set, and the sampling stop condition can be determined according to needs, and will not be repeated here. After the sampling is stopped, analyze the recorded level signals corresponding to the GPIO1 port and GPIO2 port.

As shown in Figure 2, according to the definition of interrupt response time and interrupt recovery time, T1 is the interrupt response time, starting from T1 in the figure: the falling edge of the GPIO1 port level represents the generation of an interrupt request, and ending at T1: GPIO1 port power The flat rising edge represents that the CPU starts to process the interrupt user program, and read the time difference between the end position and the start position of T1 from the logic analyzer, so as to obtain the interrupt response time T1.

For the interrupt recovery time T2, in the figure, the start position of T2: the rising edge corresponding to the GPIO2 port represents the completion of the execution of the interrupt user program, and the end position of T2: the falling edge of the GPIO1 port level represents the CPU returning to the original program time point, from the logic analyzer Read out the time difference between the end position and the start position of T2, that is, the interrupt recovery time T2 can be obtained.

Taking CPU adopting processor TMS320F2812, CPU running engine control software, the measured internal interrupt is interrupt response time T1 and interrupt recovery time T2 corresponding to RTOSINT interrupt as an example, the specific implementation process of the present invention is described. specifically,

After the start-up section of the control software, configure the two pins GPIOA10 and GPIOD6 as general-purpose output functions, and initialize them to output low levels to ensure that these two pins are not used in other unrelated instrumentation codes for this measurement, and other interrupts are shielded. Connect the two GPIOA10 and GPIOD6 signals and the ground wire to the two channels ch1, ch2 and ground wire ch_Gnd of the logic analyzer, set the acquisition accuracy of the logic analyzer to 2ns, and the trigger condition is the rising edge of GPIOA10 to trigger and save the data.

Before setting the RTOSINT interrupt flag bit, set the 10th bit of the GPIOA data register value to 1, GPIOA10 is high level, after setting the RTOSINT interrupt flag bit, repeatedly reset the 10th bit of the GPIOA data register value to 1 or 0 , and then achieve the effect of flipping the GPIOA10 level five times.

Flip the value of the data register bit corresponding to GPIOA10 at the beginning position of the corresponding soft interrupt processing function, and set the data register position of GPIOD6 to 1 at the end position of the interrupt processing function, and GPIOD6 outputs a high level.

The logic analyzer collects and analyzes the data recorded above, so as to obtain the interrupt response time T1 and the interrupt recovery time T2. Specifically, using the fast output hardware characteristics of GPIO (the time required for the GPIO flipping level of TMS320F2812 is 40ns, the instructions for flipping GPIO are only 1-3 CPU instructions, and the time is up to 25ns), the GPIO level change moment Approximately expressing the four time points when an interrupt request is generated, the CPU starts to process the interrupt user program, the execution of the interrupt user program is completed, and the CPU returns to the interrupted code, the error of the measurement of the interrupt response and recovery time is at most 25ns, which is more than the time when the timer obtains the count value. The error caused by the function (including the time when the function is put in and out of the stack and the function processing time) is small. The level change of the GPIO signal is captured by the high precision of the logic analyzer, and then the interrupt response time T1 and the interrupt recovery time T2 are obtained by analyzing the data. , the accuracy of the measurement results can reach about tens of ns on a processor of about 100M.

According to the above process, the RTOSINT interrupt response time T1 and interrupt recovery time T2 of the engine control software can be measured more accurately, which is consistent with the theoretical analysis, which provides the basis for the timing and time analysis and verification of the system, and the evaluation and verification of product performance Basic guarantees are provided.

The invention connects the GPIO1 port and the GPIO2 port of the CPU with the logic analyzer, collects and records the level signals corresponding to the GPIO1 port and the GPIO2 port through the logic analyzer, and can measure the The interrupt response time and interrupt recovery time of CPU internal interrupts are obtained, which is convenient to operate, reduces the deviation of system running time and timing analysis, and is safe and reliable.

Claims (3)

1. a kind of measuring method based on the CPU internal interrupt response time of logic analyzer and recovery time, it is characterized in that, described measuring method comprises the steps: S1. Select two GPIO ports of the CPU, and configure the selected two GPIO ports as general-purpose output interfaces and initialize them as low-level outputs. The two GPIO ports are respectively marked as GPIO1 ports and GPIO2 ports; the CPU passes GPIO1 port and GPIO2 port are respectively matched and connected with the logic analyzer. When the level of the GPIO1 port is on the rising edge, the logic analyzer collects and saves the level signals corresponding to the GPIO1 port and GPIO2 port; Step S2, the software of the selected CPU can trigger an interrupt, and before the software can trigger the interrupt, flip the level of the GPIO1 port, so that the logic analyzer can collect and save the level signals corresponding to the GPIO1 port and the GPIO2 port; Step S3, triggering the selected software to trigger an interrupt, and flipping the level signal of the GPIO1 port N times continuously, and inserting piles during the interrupt processing, so that the GPIO1 port is flipped at the beginning position of the corresponding soft interrupt processing function. Level, and set the level of GPIO2 port high at the end of the interrupt processing function; Step S4, after the above-mentioned software can trigger the interrupt recovery and after the GPIO1 level changes, the logic analyzer stops collecting the level signals corresponding to the GPIO1 port and the GPIO2 port, and analyzes the level signals corresponding to the recorded GPIO1 port and the GPIO2 port , to determine the interrupt response time T1 and recovery time T2. 2. the measuring method of interrupt response time and recovery time based on the CPU internal interrupt response time of logic analyzer according to claim 1, it is characterized in that, in step S3, after software can trigger interrupt triggering, flipping the electric current of GPIO1 mouth continuously N times When the signal is flat, (N-2)*The interval between flipping the GPIO1 port level on both adjacent sides is greater than the time from when the software can trigger an interrupt to when the CPU stops executing the current program instruction, and N is greater than or equal to 3. 3. the measuring method of the interrupt response time and recovery time based on the CPU interior of logic analyzer according to claim 1, it is characterized in that, in step S2, after the software of selected CPU can trigger interrupt, shield the remaining interrupts of CPU.