CN106252388B - Semiconductor crystal wafer and its manufacturing method - Google Patents

Abstract

The embodiment of the present invention provides a kind of semiconductor crystal wafer and its manufacturing method.The semiconductor crystal wafer includes multiple spaced chips, and the dicing lane being arranged at intervals between two neighboring chip.Wherein, each chip include the semiconductor devices being formed on one surface of wafer, positioned at the back metal on another surface of wafer and at least one through the wafer and connecting the metal part of semiconductor devices and the through-hole of the back metal.The through-hole is formed in same etching technics with the dicing lane.The embodiment of the present invention can reduce the fragment rate of semiconductor crystal wafer, improve product yield.

Description

Semiconductor wafer and method of manufacturing the same

technical field

The present invention relates to the fields of microelectronics and semiconductor manufacturing methods, and in particular, to a semiconductor wafer and a manufacturing method thereof.

Background technique

After the device is fabricated on the semiconductor wafer through the process steps of illumination, etching, deposition, cleaning, injection, etc., physical and mechanical cutting is generally used to cut the circuit device fabricated from the semiconductor wafer into multiple independent chips. Physical mechanical cutting generally uses a slicing machine. Its working principle is to use the cutting surface of a high-speed rotating diamond blade to physically cut the semiconductor wafer at a feed speed of several to tens of millimeters per second, and reserve along the wafer. In the scribing area, the semiconductor wafer material is cut into tiny granular substances to achieve the purpose of cutting and separation. The circuit devices on the semiconductor wafer can be cut into a plurality of independent chips by means of physical mechanical cutting. However, the above method has some disadvantages, because the cutting edge itself has a certain thickness, and the edges of the front and back sides of the chip may be chipped to a certain degree during the cutting process. If the width of the dicing lane between chips is not designed enough, the width of the blade cut and chipping will affect the device structure, resulting in device damage and yield reduction. If the width of the dicing lane is designed to be wide enough, the number of chips fabricated on a wafer will be reduced, resulting in an increase in the cost of the device.

In addition, when fabricating discrete semiconductor devices, in order to increase the gain of the device and reduce the grounding inductance, a through-hole structure is usually used. This structure is generally etched from the backside of the wafer to introduce vias that run through the entire semiconductor wafer to the semiconductor, and then fill the vias with metal to connect the source to the grounded backside of the wafer to reduce Source-to-ground inductance. So another way to separate semiconductor wafer devices into individual chips is to use an etch process. Etching along the scribing area on the backside of the semiconductor wafer while etching the through hole separates the chips from one chip. However, this method also has drawbacks. One is improper control. When the chips have been etched and separated, the through holes that need to be etched are not etched to the required depth. The second is that after etching, the wafer is fragile in subsequent processes due to the problem of etching depth control.

SUMMARY OF THE INVENTION

In view of the above content, the purpose of the embodiments of the present invention is to provide a semiconductor wafer and a method for manufacturing the same, so as to improve the above problems.

A semiconductor wafer provided by an embodiment of the present invention includes: a plurality of chips arranged at intervals, and dicing lanes arranged at intervals between two adjacent chips. Wherein, each of the chips includes a semiconductor device formed on one surface of the wafer, a backside metal located on the other surface of the wafer, and at least one metal portion penetrating the wafer and connecting the semiconductor device and the wafer. A through hole of the back metal; wherein, the through hole and the dicing lane are formed in the same etching process.

Preferably, the etched surface of the scribing channel and the etched surface of the through hole are the same etched surface. By adjusting the size ratio of the diameter of the through hole and the width of the scribing channel, the through hole is etched to the metal part of the semiconductor device. , the depth of the groove formed by the etching of the scribing track is between one fifth to four fifths of the thickness of the wafer.

Preferably, the diameter of the through hole is 5 to 50 times the maximum width of the dicing lane, and when the through hole is elliptical, the diameter refers to the diameter of the long side.

Preferably, a dicing lane is set between any two adjacent chips, each dicing lane includes a first part and a second part connected at opposite ends of the first part, and the width of the first part is greater than that of the second part.

Preferably, the width of the first portion of the scribe lane is 1 to 10 times the width of the second portion.

Preferably, the wafer is formed from one of silicon, sapphire, silicon carbide, gallium arsenide, and gallium nitride, or is grown on silicon, sapphire, silicon carbide, and gallium arsenide wafers. One of the epitaxial layers of epitaxial wafers is formed.

A method for manufacturing a semiconductor wafer provided by an embodiment of the present invention includes: attaching a wafer on which a semiconductor device is formed to a substrate support; and placing a surface of the wafer away from the substrate support forming a patterned mask layer to expose a part of the wafer; and etching the exposed part of the wafer to form through holes penetrating the wafer substrate and including different widths Scribing lanes of a first part and a second part, wherein the width of the first part is larger than that of the second part, and the second part is connected at opposite ends of the first part.

Preferably, after the wafer is attached to the substrate support, the method further includes: thinning the first wafer substrate, wherein the wafer is thinned to Between 50 and 200 microns.

Preferably, the step of forming a patterned mask layer on a surface of the wafer away from the substrate support sheet includes: depositing a mask layer on a surface of the wafer away from the substrate support sheet forming a layer of protective material above the mask layer, and using a lithography plate to perform photolithography on the protective material to form a patterned protective layer; and removing the part of the mask layer that is not covered by the protective layer The patterned mask layer is formed.

Preferably, the lithography plate includes a first light passing portion corresponding to the through hole and a second light passing portion corresponding to the scribe lane, and the second light pass portion includes a first pass portion corresponding to the scribe lane. A part of the corresponding first light-passing area and the second light-passing area corresponding to the second part of the scribe lane, the width of the first light-passing area is greater than the width of the second light-passing area.

Preferably, the method further includes: forming a patterned backside metal on a surface of the wafer away from the substrate support sheet, so that the backside metal is electrically connected to the metal part of the semiconductor device through the through hole ; and removing the substrate support from the wafer to separate the semiconductor wafer.

Preferably, the method uses reactive ion etching, inductively coupled plasma etching, or ion beam etching to etch a portion of the wafer.

Preferably, the patterned mask layer is formed of one or more combinations of nickel, aluminum, silicon dioxide, silicon nitride, and photoresist.

Compared with the prior art, in the semiconductor wafer and the manufacturing method thereof provided by the embodiments of the present invention, by adjusting the size ratio of the diameter of the through hole and the width of the dicing channel, when the through hole is etched to the metal part of the semiconductor device, the dicing channel is The etch depth is between one-fifth and four-fifths of the wafer thickness. It has been verified by experiments that the etching depth of the dicing track is controlled within a certain range. When the wafer is separated from the substrate support sheet, the remaining part of the etching can be connected, which can reduce the fragmentation of the wafer. Rate. In addition, the design of the scribing track of the semiconductor wafer includes two parts with different widths. By designing different widths, the etching depths of the regions with different widths are different, so that the connection strengths of different regions of the chip are different. It has been verified by experiments that the fragmentation rate of semiconductor wafers can be reduced and the product yield can be improved.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 shows a schematic diagram of a planar structure of a through hole and a dicing track of a semiconductor wafer provided by a preferred embodiment of the present invention.

FIG. 2 is an enlarged schematic plan view of a part of the semiconductor wafer through hole and the dicing lane shown in FIG. 1 .

FIG. 3 is a schematic cross-sectional view of the semiconductor wafer along the line A-A shown in FIG. 1 .

FIG. 4 is a schematic diagram of a lithography plate used for manufacturing the through holes and scribe lanes shown in FIG. 2 according to an embodiment of the present invention.

5 is a process flow diagram of a method for manufacturing a semiconductor wafer according to a preferred embodiment of the present invention.

6 to 15 are schematic structural diagrams of the respective components of the semiconductor wafer manufactured in each process flow step of the semiconductor wafer manufacturing method.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. The components of the embodiments of the invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Thus, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present invention.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

Referring to FIGS. 1 to 3 , a semiconductor wafer 100 provided by a preferred embodiment of the present invention includes a plurality of chips 110 disposed at intervals and dicing lanes 120 disposed between adjacent chips 110 . Preferably, in this embodiment, the plurality of chips 110 included in the semiconductor wafer 100 may be arranged in a matrix on the plane where the semiconductor wafer 100 is located.

In this embodiment, a dicing lane 120 is set between any two adjacent chips 110 . In the same extending direction, two adjacent dicing lanes 120 are connected to each other. Adjacent scribing lanes 120 in different extending directions are arranged to cross each other. As shown in FIG. 2 , the dicing lane 120 includes a first portion 121 and a second portion 122 connected to opposite ends of the first portion 121 . The width of the first portion 121 is greater than the width of the second portion 122 . Preferably, the width of the first portion 121 is between 1 and 10 times the width of the second portion 122 .

Further, as shown in FIG. 3 , the chip 110 includes a semiconductor device 130 fabricated on one surface of the wafer 101 , a back metal 140 disposed on the other surface of the wafer 101 , and a metal 140 that penetrates the wafer 101 . At least one through hole 150 for connecting the metal part of the semiconductor device 130 and the backside metal 140 (only one through hole 150 is shown in this embodiment). In this embodiment, when the semiconductor device 130 is a three-terminal device, the metal portion of the semiconductor device 130 may be a source metal. The semiconductor device 130 is connected to the backside metal 140 through the through hole 150 . The backside metal 140 can be used as a ground metal. Preferably, the wafer 101 used to fabricate the chip 110 in this embodiment can be formed of one of silicon, sapphire, silicon carbide, gallium arsenide, and gallium nitride wafers, or silicon, sapphire, and silicon carbide. , One of the epitaxial wafers in which the epitaxial layer is grown on the gallium arsenide wafer bare chip is formed. The shape of the through hole 150 may be circular or oval.

Secondly, the dicing lane 120 is a trench etched from the back side of the wafer 101 where the semiconductor device 130 is formed. When etching the metal portion of the semiconductor device, the etching depth of the trench is between one fifth and four fifths of the thickness of the wafer 101 . In this embodiment, the through holes 150 and the dicing lanes 120 are formed in the same etching process.

Preferably, in one embodiment, the through holes 150 and the scribing lanes 120 can be formed by using the photolithography plate 170 shown in FIG. 4 to perform processes such as illumination and etching. Specifically, the mask 170 includes a plurality of first light passing parts 171 corresponding to the through holes 150 and a plurality of second light passing parts 172 corresponding to the dicing lanes 120 . The shape of the first light passing portion 171 is the same as that of the through hole 150 , and the shape of the second light passing portion 172 is the same as that of the dicing lane 120 . Specifically, the second light passing portion 172 includes a first light passing area 1721 corresponding to the first portion 121 of the scribe lane 120 and a second light passing area 1722 corresponding to the second portion 122 of the scribe lane 120 . The width of the first light passing region 1721 is greater than the width of the second light passing region 1722 .

To sum up, in the semiconductor wafer 100 provided by the embodiment of the present invention, the dicing track 120 is designed into two parts with different widths, which can reduce the fragmentation rate of the semiconductor wafer 100 and improve the product yield through experimental verification.

FIG. 5 shows a process flow diagram of the method for manufacturing the semiconductor wafer 100 in the preferred embodiment of the present invention. The flowchart will be described in detail below with reference to FIGS. 6 to 15 . It should be noted that the method described in the present invention is not limited to the specific sequence shown in FIG. 5 and the following. It should be understood that, in other embodiments, the order of some steps in the method of the present invention may be exchanged with each other according to actual needs, or some steps may be omitted or deleted.

Step S501 , as shown in FIG. 6 , a plurality of semiconductor devices 130 are formed on a wafer 200 . In this embodiment, the semiconductor device 130 may be represented by a metal part of the semiconductor device. Specifically, the patterned semiconductor device 130 may be formed on one surface of the wafer 200 through photolithography, deposition, etching, and other processes. The wafer 200 may be formed of a semiconductor wafer die 201 or formed after the epitaxial layer 202 is grown on the semiconductor wafer die 201 .

Step S502 , as shown in FIG. 7 , the wafer 200 formed with the semiconductor device 130 is attached to the substrate support sheet 300 , and the wafer 200 is thinned. Specifically, the substrate support sheet 300 is attached to the side of the wafer 200 where the semiconductor device 130 is formed. The substrate support sheet 300 may be made of materials such as sapphire, glass, silicon carbide, and silicon wafers. In other embodiments, a thin substrate can also be used as the wafer 200, so that the step of thinning the wafer 200 is omitted.

In this embodiment, the substrate support sheet 300 is preferably attached to the side of the wafer 200 close to the semiconductor device 130 using an adhesive 203 (such as optical adhesive OCA, OCR, Wax, etc.). The methods of thinning the wafer 200 include rough grinding, fine grinding and polishing. Coarse grinding has a fast removal rate, but the roughness is large, reaching several hundreds of nanometers. The removal of fine grinding is slow, and the roughness is about tens of nanometers. The polishing removal amount is the slowest, but the roughness of the wafer 200 can be satisfied by the polishing process. In addition, the wafer 200 is thinned to between 50 μm and 200 μm. Under this thickness, if the wafer 200 is subjected to subsequent processes such as photolithography, etching, and metallization, it is easily broken. Therefore, in this embodiment, the wafer 200 is first attached to the substrate support sheet 300 , and then processes such as thinning are performed to prevent the wafer 200 from being broken during the process.

Step S503 , forming a patterned mask layer 220 on a surface of the wafer 200 away from the substrate support sheet 300 to expose a part of the wafer 200 .

Specifically, as shown in FIG. 8 , first, a mask layer 210 is deposited on a surface of the wafer 200 away from the substrate support sheet 300 . Specifically, the mask layer 210 may be formed by sputtering, electroplating, deposition and other methods. The mask layer 210 may be formed of one or more combinations of nickel, aluminum, silicon dioxide, silicon nitride, and photoresist.

Then, as shown in FIG. 9 , a patterned protective layer 220 is formed on the mask layer 210 . Specifically, a layer of protective material can be formed on the mask layer 210 first, and the protective material can be photoresist, such as positive photoresist or negative photoresist. Then, the protective material is illuminated and developed to form the patterned protective layer 220 . The photomask 170 shown in FIG. 4 can be used to perform light irradiation and development, so as to form exposed areas in the protective material layer with shapes corresponding to the through holes 150 and the scribe lanes 120 .

Finally, as shown in FIG. 10 , the part of the mask layer 210 not covered by the protective layer 220 is removed to form a patterned mask layer 210 to expose a part of the wafer 200 . Wherein, in this embodiment, the mask layer 210 may be etched by wet etching or dry etching, so as to remove the part not covered by the protective layer 220 .

Step S504 , as shown in FIG. 11 , etching a part of the exposed wafer 200 to form through holes 150 and scribe lines 120 , and then removing the mask layer 210 on the surface of the wafer 200 . Wherein, the formed dicing lane 120 includes a first portion 121 and a second portion 122 connected to opposite ends of the first portion 121 . The width of the first portion 121 is greater than the width of the second portion 122 . Preferably, the width of the first portion 121 is between 1 and 10 times the width of the second portion 122 .

Specifically, etching equipment such as RIE (Reactive Ion etching, reactive ion etching), ICP (Inductively Coupled Plasma, inductively coupled plasma etching), IBE (Ion Beam Etching, ion beam etching), ERC, etc. The exposed portion of the wafer 200 is etched. In addition, it has been verified that for the same through hole shape, the larger the etching aperture, the faster the etching rate. Therefore, in this embodiment, the designed aperture of the through hole 150 is larger than the width of the dicing lane 120 . Preferably, the diameter of the through hole 150 is 5 to 50 times the maximum width of the dicing lane 120 (eg, the width of the first portion 121 ). When the through hole 150 is etched to the position of the semiconductor device 130 , it stops, and the etching depth of the scribing channel 120 is adjusted by the design size ratio of the aperture of the dicing channel 120 and the through hole 150 . In this way, when the etching depth of the through hole 150 reaches the semiconductor device 130 , the etching depth of the scribe line 120 can be controlled to be between 1/5 and 4/5 of the thickness of the wafer 200 .

Step S505 , a patterned backside metal 140 is formed on the side of the wafer 200 away from the substrate support sheet 300 , and the backside metal 140 is connected to the metal portion of the semiconductor device 130 through the through hole 150 .

Specifically, as shown in FIG. 12 , first, a metal layer 230 is formed on the side of the wafer 200 away from the substrate support sheet 300 .

Then, as shown in FIG. 13 , a patterned etch stop layer 240 is formed over the metal layer 230 . Specifically, a layer of protective material may be first formed on the metal layer 230 by coating. The protective material can be a photoresist, such as positive photoresist or negative photoresist. Then, photolithography is performed on the protective material to form the patterned etch stop layer 240 . The patterned etching barrier layer 240 may be formed by illuminating and developing the protective material.

Finally, as shown in FIG. 14 , the part of the metal layer 230 that is not blocked by the patterned etch barrier layer 240 is etched, and then the etch barrier layer 240 is removed to form the patterned etch barrier layer 240 . Backside metal 140.

Step S506 , the substrate support sheet 300 is removed from the side of the wafer 200 close to the semiconductor device 130 to form the semiconductor wafer 100 as shown in FIG. 3 .

Finally, the semiconductor wafer 100 is split along the dicing lanes 120 of the semiconductor wafer 100 to form a plurality of independent chips 110 as shown in FIG. 15 .

To sum up, according to the method for manufacturing the semiconductor wafer 100 provided by the embodiment of the present invention, the dicing track 120 of the semiconductor wafer 100 obtained by manufacturing includes two parts with different widths, and the dimensions of the diameter of the through hole and the width of the dicing track are adjusted by adjusting the diameter of the through hole. When the through hole is etched to the metal part of the semiconductor device, the etching depth of the scribe line is between 1/5 and 4/5 of the thickness of the wafer 200 . It has been verified by experiments that the chipping rate of the semiconductor wafer 200 can be reduced and the product yield can be improved.

It should also be noted that, in the description of the present invention, unless otherwise expressly specified and limited, the terms "arrangement", "installation", "connection" and "connection" should be understood in a broad sense, for example, it may be a fixed connection, It can also be a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or the internal communication between the two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of the invention is usually placed in use, only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying The device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first", "second", "third", etc. are only used to differentiate the description and should not be construed as indicating or implying relative importance.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (11)

1. a semiconductor wafer, is characterized in that, described semiconductor wafer comprises: multiple spaced chips; and A dicing lane spaced between two adjacent chips, where: Each of the chips includes a semiconductor device formed on one surface of the wafer, a backside metal on the other surface of the wafer, and at least one metal portion extending through the wafer and connecting the semiconductor device and the backside metal The through hole; wherein, the through hole and the dicing lane are formed in the same etching process; Wherein, a scribing lane is set between any two adjacent chips, each scribing lane includes a first part and a second part connected at opposite ends of the first part, and the width of the first part is greater than that of the second part. 2. semiconductor wafer according to claim 1, is characterized in that, the etched surface of described scribe lane and the etched surface of through hole are the same etched surface, by adjusting the size ratio of through hole diameter and scribe lane width , so that when the through hole is etched into the metal part of the semiconductor device, the depth of the trench formed by the scribing channel etching is between one fifth to four fifths of the thickness of the wafer. 3. The semiconductor wafer according to claim 2, wherein the diameter of the through hole is 5 to 50 times the maximum width of the scribing track, and when the through hole is elliptical, the diameter refers to is the long side diameter. 4. The semiconductor wafer of claim 3, wherein the width of the first portion of the scribe lane is 1 to 10 times the width of the second portion. 5 . The semiconductor wafer according to claim 1 , wherein the wafer is formed of one of silicon, sapphire, silicon carbide, gallium arsenide, and gallium nitride, or is silicon, sapphire , silicon carbide, and one of epitaxial wafers with epitaxial layers grown on gallium arsenide wafer die. 6. A method for manufacturing a semiconductor wafer, wherein the method comprises: attaching the wafer formed with the semiconductor device to the substrate support; A patterned mask layer is formed on a surface of the wafer away from the substrate support, exposing a portion of the wafer to be etched; and etching a part of the exposed wafer to form a through hole penetrating the wafer and a dicing lane including a first part and a second part with different widths, wherein the width of the first part is larger than that of the A second portion connected at opposite ends of the first portion. 7. The method for manufacturing a semiconductor wafer according to claim 6, wherein after the wafer is attached to the substrate support sheet, the method further comprises: The wafer is thinned, wherein the wafer is thinned to between 50 and 200 microns. 8. The method for manufacturing a semiconductor wafer according to claim 7, wherein the step of forming a patterned mask layer on a surface of the wafer away from the substrate support sheet comprises: depositing a mask layer on a surface of the wafer away from the substrate support; A layer of photoresist is formed on the mask layer, and a photoresist is subjected to a photoresist development process to form a patterned protective layer; and removing the part of the mask layer not covered by the protective layer to form the patterned mask layer; Wherein, the lithography plate includes a first light-passing portion corresponding to the through hole and a second light-passing portion corresponding to the scribing lane, and the second light-passing portion includes a first portion corresponding to the scribing lane The corresponding first light-passing area and the second light-passing area corresponding to the second part of the scribe lane, the width of the first light-passing area is greater than the width of the second light-passing area. 9. The method for manufacturing a semiconductor wafer according to claim 6, wherein the method further comprises: A patterned backside metal is formed on the side of the wafer away from the substrate, so that the backside metal is electrically connected to the semiconductor device through the through hole; and The substrate support sheet is removed from the wafer to separate the semiconductor wafer. 10. The method for manufacturing a semiconductor wafer as claimed in claim 6, wherein the method adopts reactive ion etching, inductively coupled plasma etching, or ion beam etching to etch a portion of the wafer. Etching is performed. 11. The method for manufacturing a semiconductor wafer according to claim 6, wherein the patterned mask layer is made of one of nickel, aluminum, silicon dioxide, silicon nitride, and photoresist or More than one composition is formed.