CN106298963A - SONOS device architecture and the method forming this device - Google Patents

Abstract

The invention provides a SONOS device structure and a method for forming the device. The SONOS device structure according to the present invention comprises: a silicon substrate, a source electrode and a drain electrode formed in the silicon substrate, a gate of a multilayer structure formed on the silicon substrate; wherein the gate comprises from bottom to top: a tunneling silicon oxide layer, a silicon nitride layer, a blocking silicon oxide layer and a polysilicon control gate, the tunneling silicon oxide layer is in contact with the silicon substrate; wherein, a first gate side is formed on the sidewall of the polysilicon control gate A wall, a second gate sidewall is formed on the first gate sidewall and the sidewalls of the tunneling silicon oxide layer, the silicon nitride layer and the blocking silicon oxide layer.

Description

SONOS device structure and method for forming the device

technical field

The invention relates to the field of semiconductor manufacturing, more specifically, the invention relates to a SONOS device structure with improved erasing and writing windows and a method for forming the device.

Background technique

Flash memory (Flash Memory) is widely used in consumer electronic products such as mobile phones and digital cameras and portable systems due to its non-volatile characteristics. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon/silicon dioxide/silicon nitride/silicon dioxide/silicon) flash memory is characterized by its simple process, low operating voltage, high data reliability and easy integration into standard Due to the medium advantages of the CMOS process, it is regarded as a substitute product of the common floating gate (Floating Gate) type flash memory.

A typical SONOS structure is composed of silicon substrate (S)-tunneling oxide layer (O)-charge storage layer silicon nitride (N)-blocking oxide layer (O)-polysilicon gate (S). This structure uses electron tunneling to compile and hole injection to erase data.

In SONOS, charges are stored in a trapping center in an ONO (Oxide-Nitride-Oxide, silicon dioxide/silicon nitride/silicon dioxide) dielectric layer, so it is called a charge trapping device.

With the advancement of process technology nodes, SONOS devices are shrinking in equal proportions with the process nodes. The smaller SONOS device channels under advanced process nodes lead to a reduction in the area of the ONO dielectric film in the storage area, thereby reducing the erase and write of SONOS devices. window, or limit the ability to further improve the scaling of SONOS device units.

In the existing technology, for SONOS devices with smaller sizes under advanced technology nodes, a series of process optimizations are used to improve the trapping ability of the ONO dielectric layer, thereby increasing the erasing and writing window of SONOS devices, or further improving the shrinking ability of SONOS devices. It is the focus and direction of the research.

Contents of the invention

The technical problem to be solved by the present invention is to provide a SONOS device structure capable of improving the erasing and writing window and a method for forming the device in view of the above-mentioned defects in the prior art.

In order to achieve the above technical purpose, according to the present invention, a SONOS device structure is provided, including: a silicon substrate, a source electrode and a drain electrode formed in the silicon substrate, and a gate of a multilayer structure formed on the silicon substrate ; Wherein the gate includes from bottom to top: a tunneling silicon oxide layer, a silicon nitride layer, a blocking silicon oxide layer and a polysilicon control gate, and the tunneling silicon oxide layer is in contact with the silicon substrate; wherein, in the polysilicon control A first gate sidewall is formed on the sidewall of the gate, and a second gate sidewall is formed on the sidewall of the first gate sidewall and the sidewalls of the tunneling silicon oxide layer, the silicon nitride layer and the blocking silicon oxide layer.

Preferably, the material of the first gate spacer is silicon oxide.

Preferably, the thickness of the first gate spacer is between 50A˜200A.

Preferably, the second gate spacer is in contact with the silicon substrate.

Preferably, the material of the second gate spacer is silicon nitride, and the thickness of the second gate spacer is between 50A˜200A.

In order to achieve the above-mentioned technical purpose, according to the present invention, a method for forming a SONOS device structure is also provided, which is characterized in that it comprises:

The first step: sequentially preparing an ONO stack comprising a tunneling silicon oxide layer, a silicon nitride layer and a blocking silicon oxide layer on a silicon substrate;

The second step: preparing a polysilicon control gate on the surface of the blocking silicon oxide layer, wherein the size of the polysilicon control gate on a plane parallel to the substrate surface is smaller than that of the ONO stack;

The third step: preparing a first gate spacer material layer on the surface of the device;

The fourth step: performing self-aligned etching, etching the first gate spacer material layer, leaving only the first gate spacer material layer on the sidewall of the polysilicon control gate, and etching away the material layer beyond the polysilicon control gate. An ONO stack of the first gate spacer material layer on the gate sidewall to form a first gate spacer on the ONO stack;

The fifth step: preparing a second gate spacer material layer on the surface of the above-mentioned device, and self-aligning etching the second gate spacer material layer so that the first gate spacer and the tunnel silicon oxide layer, nitrogen forming a second gate spacer on the sidewalls of the silicon oxide layer and the blocking silicon oxide layer;

The sixth step: forming source and drain in the silicon substrate.

Preferably, the first gate spacer material layer is a silicon oxide layer.

Preferably, the thickness of the first gate spacer material layer is between 50A˜200A.

Preferably, the second gate spacer material layer is a silicon nitride layer.

Preferably, the thickness of the second gate spacer material layer is between 50A˜300A.

The SONSO device provided by the invention has a larger equivalent channel length under limited area and size, thereby increasing the erasing and writing window or further improving the shrinking ability of the SONOS device unit. The process of the invention is relatively simple, easy to integrate, and can be used for mass production.

Description of drawings

A more complete understanding of the invention, and its accompanying advantages and features, will be more readily understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, in which:

Fig. 1 schematically shows a schematic diagram of a SONOS device structure according to a preferred embodiment of the present invention.

Fig. 2 schematically shows a device structure diagram of the first step of the method for forming a SONOS device structure according to a preferred embodiment of the present invention.

Fig. 3 schematically shows a device structure diagram of the second step of the method for forming a SONOS device structure according to a preferred embodiment of the present invention.

Fig. 4 schematically shows a device structure diagram of the third step of the method for forming a SONOS device structure according to a preferred embodiment of the present invention.

Fig. 5 schematically shows a device structure diagram of the fourth step of the method for forming a SONOS device structure according to a preferred embodiment of the present invention.

Fig. 6 schematically shows a schematic view of the device structure of the fifth step and the sixth step of the method for forming the SONOS device structure according to a preferred embodiment of the present invention.

Explanation of reference marks:

101: silicon substrate; 201: source; 301: drain; 401: polysilicon control gate; 402: tunneling silicon oxide layer; 403: silicon nitride layer; 404: blocking silicon oxide layer; 501: first gate sidewall; 502 : the second gate sidewall.

It should be noted that the accompanying drawings are used to illustrate the present invention, but not to limit the present invention. Note that drawings showing structures may not be drawn to scale. And, in the drawings, the same or similar elements are marked with the same or similar symbols.

detailed description

In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

Fig. 1 schematically shows a schematic diagram of a SONOS device structure according to a preferred embodiment of the present invention.

As shown in Figure 1, the SONOS device structure according to the preferred embodiment of the present invention includes: a silicon substrate 101, a source electrode 201 and a drain electrode 301 formed in the silicon substrate 101, a multilayer structure formed on the silicon substrate 101 The gate; wherein the gate includes from bottom to top: a tunneling silicon oxide layer 402, a silicon nitride layer 403, a blocking silicon oxide layer 404 and a polysilicon control gate 401, the tunneling silicon oxide layer 402 and the silicon substrate 101 phase contact; wherein, a first gate spacer 501 is formed on the side wall of the polysilicon control gate 401, and the first gate spacer 501 and the tunneling silicon oxide layer 402, the silicon nitride layer 403, and the blocking silicon oxide layer A second gate spacer 502 is formed on the sidewall of 404 .

Preferably, the material of the first gate spacer 501 is silicon oxide. Preferably, the thickness of the first gate spacer 501 is between 50A˜200A.

Preferably, the second gate spacer 502 is in contact with the silicon substrate 101 . Moreover, preferably, the material of the second gate spacer 502 is silicon nitride. Preferably, the thickness of the second gate spacer 502 is between 50A˜200A.

In the manufacture of the SONOS device, before the etching of the ONO film on both sides of the gate, the deposition of the first gate spacer 501 is added, and then through self-aligned etching, the first gate spacer 501501 of silicon dioxide is used as the The etch stop layer protects the tunneling silicon oxide layer 402 , the silicon nitride layer 403 , and the blocking silicon oxide layer 404 under the first gate spacer 501 from being etched, so as to increase the effective length of the storage film ONO in the channel.

2 to 6 schematically show device structure diagrams of various steps in the method for forming a SONOS device structure according to a preferred embodiment of the present invention.

As shown in Figures 2 to 6, the SONOS device structure forming method according to a preferred embodiment of the present invention includes:

The first step: sequentially prepare an ONO stack including a tunneling silicon oxide layer 402, a silicon nitride layer 403 and a blocking silicon oxide layer 404 on a silicon substrate; specifically, form the SONOS device with a storage function by etching The ONO stack, that is, the tunneling silicon oxide layer 402, the silicon nitride layer 403, and the blocking silicon oxide layer 404;

The second step: preparing a polysilicon control gate 401 on the surface of the blocking silicon oxide layer 404, wherein the size of the polysilicon control gate 401 on a plane parallel to the substrate surface is smaller than that of the ONO stack;

Specifically, the polysilicon control gate 401 of the SONOS device is formed by etching, the size of the polysilicon control gate 401 formed after the polysilicon gate is etched is smaller than the ONO stack, and the etching stops at the blocking silicon oxide layer 404 on the surface of the ONO;

The third step: preparing a first gate spacer material layer on the surface of the device;

Preferably, the first gate spacer material layer is a silicon oxide layer;

Preferably, the thickness of the first gate spacer material layer is between 50A˜200A.

Step 4: Perform self-aligned etching, etch the first gate spacer material layer, leaving only the first gate spacer material layer on the sidewall of the polysilicon control gate 401, and etch away the material layer beyond the polysilicon Controlling the ONO stack of the first gate spacer material layer on the sidewall of the gate 401 to form the first gate spacer 501 on the ONO stack;

The fifth step: preparing a second gate spacer material layer on the surface of the above-mentioned device, and self-aligning etching the second gate spacer material layer so as to tunnel through the first gate spacer 501 and the silicon oxide layer 402 1. A second gate spacer 502 is formed on the sidewalls of the silicon nitride layer 403 and the blocking silicon oxide layer 404;

Preferably, the second gate spacer material layer is a silicon nitride layer, and the thickness of the second gate spacer material layer is between 50A˜300A.

Sixth step: forming a source 201 and a drain 301 in the silicon substrate 101 .

Aiming at the smaller erasing and writing window of the miniaturized SONOS device under the advanced technology node, the present invention discloses a method of adding a step of deposition of silicon dioxide sidewalls, self-aligned etching to form silicon dioxide sidewalls, thereby obtaining higher erasing, Write windows for SONOS devices. The SONSO device provided by the present invention has a larger equivalent channel length under limited area and size, improves the erasing and writing window or can further improve the shrinking ability of the SONOS device unit, and the process integration is simple and stable, and can be used in advanced manufacturing processes The next mass production.

In addition, it should be noted that, unless otherwise specified or pointed out, the terms “first”, “second”, “third” and other descriptions in the specification are only used to distinguish each component, element, step, etc. in the specification, and It is not used to represent the logical relationship or sequential relationship between various components, elements, and steps.

It can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or be modified to be equivalent to equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Furthermore, it is to be understood that this invention is not limited to the particular methods, compounds, materials, fabrication techniques, usages and applications described herein, which may vary. It should also be understood that the terminology described herein is used to describe particular embodiments only and is not intended to limit the scope of the present invention. It must be noted that as used herein and in the appended claims, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "an element" means a reference to one or more elements and includes equivalents thereof known to those skilled in the art. Similarly, as another example, a reference to "a step" or "a means" means a reference to one or more steps or means, and may include sub-steps as well as sub-means. All conjunctions used should be understood in their broadest sense. Therefore, the word "or" should be understood as having a logical "or" definition rather than a logical "exclusive-or", unless the context clearly indicates the contrary meaning. Structures described herein are to be understood as also referring to functional equivalents of the structures. Language that may be construed as approximation should be construed as such, unless the context clearly dictates otherwise.

Claims (10)

1. a SONOS device architecture, it is characterised in that including: silicon substrate, form source electrode in a silicon substrate and drain electrode, formation The grid of multiple structure on a silicon substrate；Wherein said grid includes from bottom to up: tunnel oxide silicon layer, silicon nitride layer, resistance Gear silicon oxide layer and polysilicon control grid, described tunnel oxide silicon layer contacts with silicon substrate；Wherein, in polysilicon control grid side First grid side wall it is formed with, at first grid side wall and tunnel oxide silicon layer, silicon nitride layer, barrier oxidation silicon layer on wall Second grid side wall it is formed with on sidewall.

SONOS device architecture the most according to claim 1, it is characterised in that the material of first grid side wall is silicon oxide.

SONOS device architecture the most according to claim 1 and 2, it is characterised in that the thickness of first grid side wall between Between 50A～200A.

SONOS device architecture the most according to claim 1 and 2, it is characterised in that second grid side wall connects with silicon substrate Touch.

SONOS device architecture the most according to claim 1 and 2, it is characterised in that the material of second grid side wall is nitridation Silicon, the thickness of second grid side wall is between 50A～200A.

6. a SONOS device architecture forming method, it is characterised in that including:

First step: be sequentially prepared the ONO comprising tunnel oxide silicon layer, silicon nitride layer and barrier oxidation silicon layer on a silicon substrate and fold Layer；

Second step: prepare polysilicon control grid in barrier oxidation silicon surface, wherein polysilicon control grid with substrate surface It is smaller in size than ONO lamination in parallel plane；

Third step: prepare first grid spacer material layer at above-mentioned device surface；

4th step: perform Self-aligned etching, etch described first grid spacer material layer, only leave polysilicon control grid sidewall On first grid spacer material layer, and etch away beyond the first grid spacer material layer on polysilicon control grid sidewall ONO lamination, forms the first grid side wall being on ONO lamination；

5th step: prepare second grid spacer material layer at above-mentioned device surface, and second grid described in Self-aligned etching Spacer material layer so as first grid side wall and tunnel oxide silicon layer, silicon nitride layer, barrier oxidation silicon layer sidewall on shape Become second grid side wall；

6th step: form source electrode and drain electrode in a silicon substrate.

SONOS device architecture forming method the most according to claim 6, it is characterised in that first grid spacer material layer It it is silicon oxide layer.

8. according to the SONOS device architecture forming method described in claim 6 or 7, it is characterised in that described first grid side wall The thickness of material layer is between 50A～200A.

9. according to the SONOS device architecture forming method described in claim 6 or 7, it is characterised in that second grid spacer material Layer is silicon nitride layer.

10. according to the SONOS device architecture forming method described in claim 6 or 7, it is characterised in that described second grid side The thickness of the walling bed of material is between 50A～300A.