CN106301343B - A kind of customized multi-protocols digital audio and video signals generating system of level and method - Google Patents

Abstract

The invention discloses a level self-defining multi-protocol digital audio signal generation system, which includes a host computer, an FPGA, and a digital-to-analog converter. The host computer is connected to the FPGA, and the FPGA is connected to the digital-to-analog converter; the FPGA includes a state Code memory, waveform generation module, amplitude adjustment module, data encoding module, clock frequency division module and protocol output module. The beneficial effect of the invention is that a hardware circuit capable of realizing various digital audio protocol standards is built, and the output logic level can be customized, and quantitative testing and analysis of the logic level compatibility performance of the tested equipment can be realized.

Description

A level custom multi-protocol digital audio signal generation system and method

technical field

The invention relates to the field of audio analysis, in particular to a level-defining multi-protocol digital audio signal generation system and method.

Background technique

At present, there are many different types of digital audio interfaces in the digital audio field. The mainstream interface standards include two standards: consumer digital audio interface S/PDIF digital audio interconnection and professional digital audio interface AES/EBU digital audio interface. The digital audio generation and analysis function of the current audio analyzer is mainly aimed at the generation and analysis of the signals of the two standards of the S/PDIF interface and the AES/EBU interface. During the test, the audio analyzer generates digital signals that meet the corresponding digital audio protocol standards and inputs them into the digital audio receiving device to detect the decoding performance of the digital audio receiving device. The audio analyzer outputs digital signals of different logic levels to test the level compatibility of digital audio receiving equipment.

The general audio analyzer uses a dedicated digital audio protocol encoding chip to generate digital audio signals. The functional block diagram of the general audio analyzer is shown in Figure 1. The working principle is as follows: the CPU writes the digital audio protocol parameters and digital audio data into the professional digital audio In the register corresponding to the coding chip, start the signal output function. The digital audio signal output by the encoding chip passes through the level selection circuit, and the fixed level generated by the logic level generation circuit is applied to the digital signal to realize the encoding output of different logic levels and different digital audio protocols.

The digital audio signal generation scheme of the general audio analyzer is complicated, and a special logic level generation circuit needs to be designed; the digital audio standard is single, and each digital audio standard requires a special encoding chip to realize the digital audio signal generation; the flexibility is poor, and it can only output Several typical logic levels such as +5V, +3.3V, +2.5V, +1.8V and +1.2V can only give qualitative indicators of typical logic levels when testing the logic level compatibility of receiving equipment, but cannot give Quantitative indicators of specific logic level compatibility.

Contents of the invention

The object of the present invention is to provide a system and method for generating a level-definable multi-protocol digital audio signal in order to overcome the above-mentioned deficiencies in the prior art.

To achieve the above object, the present invention adopts the following technical solutions:

A level self-defining multi-protocol digital audio signal generation system, comprising a host computer, an FPGA, and a digital-to-analog converter, the host computer is connected to the FPGA, and the FPGA is connected to the digital-to-analog converter;

The FPGA includes a state code memory, a waveform generation module, an amplitude adjustment module, a data encoding module, a clock frequency division module and a protocol output module;

The state code memory, which is connected to the input of the host computer, is used to store the state code in the digital audio coding;

The waveform generation module is used to generate waveform data;

The data encoding module is used to perform protocol encoding on the status code stored in the status code memory and the waveform data generated by the waveform generation module;

The clock frequency division module is used to generate the bit clock required by the protocol output module;

The amplitude adjustment module is used to adjust the amplitude of the data generated by the data encoding module and store it in a temporary RAM memory;

The protocol output module, driven by the bit clock provided by the clock frequency division module, sequentially transmits the amplitude-adjusted data to the digital-to-analog converter.

Preferably, the signal conditioning circuit includes a gain adjustment circuit and a single-ended differential switching circuit;

The gain adjustment circuit is used to adjust the gain of the signal level output by the digital-to-analog converter, so that the output level meets the range of 0-5V;

The single-ended differential switching circuit is used to switch the transmission mode of the output audio signal, so as to meet the requirements of different audio protocol standards.

Preferably, the digital-to-analog converter is a high-precision digital-to-analog converter.

The method for customizing a multi-protocol digital audio signal generation system based on levels comprises the following steps:

Step 1, select the protocol standard of the digital audio signal in the host computer software setting interface, and the host computer dynamically loads the interface circuit with the corresponding digital audio protocol encoding program code through the FPGA according to the selected protocol standard;

Step 2, the upper computer software setting interface configures each channel status code of each frame in the digital audio protocol standard, and sends the configuration information to the status code memory of the FPGA for storage. The data stream of digital audio waveform data, the digital audio protocol standard defines the number and structure of frames in a data stream, the position of each channel status code in each frame, and the length and format of digital audio data.

Step 3: The digital audio protocol encoding setting is performed inside the FPGA, and the channel status code of each frame is sequentially read from the status code memory, and combined with the waveform data generated by the waveform generation module to obtain the digital audio encoding data stream;

Step 4: According to the logic level set by the host computer, the FPGA adjusts the amplitude of the digital audio coded data stream and stores it in the temporary RAM memory, and outputs it to the digital-to-analog converter driven by the bit clock output by the clock frequency division circuit ;

Step 5, the digital-to-analog converter receives the amplitude-adjusted digital audio data stream, performs digital-to-analog conversion, and outputs a single-ended or differential digital audio signal waveform, and outputs it to the signal conditioning circuit;

Step 6: The signal conditioning circuit receives single-ended or differential digital audio signal waveforms, performs shaping and filtering on the single-ended or differential digital audio signal waveforms, and outputs digital audio signals conforming to digital audio signal protocol standards.

Preferably, in the second step, the configuration information includes each bit status code of each channel of each frame.

Preferably, in the second step, the protocol standard of the digital audio signal includes AES/EBU or S/PDIF general digital audio protocol and other standard digital audio protocols.

Preferably, in the step four, the FPGA uses an amplitude calibration algorithm to adjust the amplitude of the digital audio data stream.

The beneficial effects of the present invention are:

1. The present invention adopts a high-precision digital-to-analog converter chip, which has good output voltage linearity and high precision, and can realize any logic level between 0-+5V voltage;

2. The present invention can realize the continuous output of 0~+5V voltage, so it can provide the compatibility of the tested equipment to the logic level, and can test the maximum and minimum values of the logic high level and the maximum value of the logic low level. Quantitative indicators of parameters such as value and minimum value can realize quantitative analysis.

Description of drawings

Fig. 1 is the principle block diagram of digital audio signal generation of general audio analyzer;

Fig. 2 is a functional block diagram of the level self-defining multi-protocol digital audio signal generation system;

Figure 3 is a block diagram of the FPGA internal circuit.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

As shown in Figure 2, a kind of level self-defining multi-protocol digital audio signal generation system comprises host computer, FPGA, digital-to-analog converter, and described host computer is connected with FPGA, and described FPGA is connected with digital-to-analog converter;

As shown in Figure 3, the FPGA includes a state code memory, a waveform generation module, an amplitude adjustment module, a data encoding module, a clock frequency division module and a protocol output module;

The state code memory, which is connected to the input of the host computer, is used to store the state code in the digital audio coding;

The waveform generation module is used to generate waveform data;

The data encoding module is used to perform protocol encoding on the status code stored in the status code memory and the waveform data generated by the waveform generation module;

The clock frequency division module is used to generate the bit clock required by the protocol output module;

The amplitude adjustment module is used to adjust the amplitude of the data generated by the data encoding module and store it in a temporary RAM memory;

The protocol output module, driven by the bit clock provided by the clock frequency division module, sequentially transmits the amplitude-adjusted data to the digital-to-analog converter.

Preferably, the signal conditioning circuit includes a gain adjustment circuit and a single-ended differential switching circuit;

The gain adjustment circuit is used to adjust the gain of the signal level output by the digital-to-analog converter, so that the output level meets the range of 0-5V;

The single-ended differential switching circuit is used to switch the transmission mode of the output audio signal, so as to meet the requirements of different audio protocol standards.

Preferably, the digital-to-analog converter is a high-precision digital-to-analog converter.

The method for customizing a multi-protocol digital audio signal generation system based on levels comprises the following steps:

Step 1, select the protocol standard of the digital audio signal in the host computer software setting interface, and the host computer dynamically loads the interface circuit with the corresponding digital audio protocol encoding program code through the FPGA according to the selected protocol standard;

Step 2, the upper computer software setting interface sets the configuration information for the digital audio protocol standard, and sends the configuration information to the status code memory of the FPGA for storage;

Step 3: The digital audio protocol encoding setting is performed inside the FPGA, and the channel status code of each frame is sequentially read from the status code memory, and combined with the waveform data generated by the waveform generation module to obtain the digital audio encoding data stream;

Step 4: According to the logic level set by the host computer, the FPGA adjusts the amplitude of the digital audio coded data stream and stores it in the temporary RAM memory, and outputs it to the digital-to-analog converter driven by the bit clock output by the clock frequency division circuit ;

Step 5, the digital-to-analog converter receives the amplitude-adjusted digital audio data stream, performs digital-to-analog conversion, and outputs a single-ended or differential digital audio signal waveform, and outputs it to the signal conditioning circuit;

Step 6: The signal conditioning circuit receives single-ended or differential digital audio signal waveforms, performs shaping and filtering on the single-ended or differential digital audio signal waveforms, and outputs digital audio signals conforming to digital audio signal protocol standards.

Preferably, in the second step, the configuration information includes each bit status code of each channel of each frame.

Preferably, in the second step, the protocol standard of the digital audio signal includes AES/EBU or S/PDIF general digital audio protocol and other standard digital audio protocols.

Preferably, in the step four, the FPGA uses an amplitude calibration algorithm to adjust the amplitude of the digital audio data stream.

The amplitude calibration algorithm is specifically as follows: first, the output signal is calibrated in sections according to the set output logic level and the gain adjustment circuit, and then the difference between the set voltage and the actual output voltage measured by the multimeter is compared to calculate the amplitude adjustment coefficient and offset value, which are stored in the onboard EEPROM; when adjusting the amplitude, the adjustment coefficient and offset value stored in the EEPROM must be called according to the set output logic level, and the accurate logic level can be output.

The invention adopts a high-precision digital-to-analog converter chip, has good output voltage linearity and high precision, and can realize any logic level between 0-+5V voltage.

The general audio analyzer digital audio generation scheme only uses several typical logic level output signals such as +5V, +3.3V, +2.5V. During the test, the user can only judge whether the device under test is compatible under these several logic levels. If the logic level can be identified, it will be judged as compatible, otherwise it will be judged as incompatible, and only qualitative analysis can be performed.

The invention can realize the continuous output of 0-+5V voltage, so it can provide the compatibility of the tested equipment to the logic level, and can test the maximum and minimum values of the logic high level and the maximum and minimum values of the logic low level. Quantitative indicators of parameters such as the minimum value can realize quantitative analysis.

Although the specific implementation of the present invention has been described above in conjunction with the accompanying drawings, it does not limit the protection scope of the present invention. Those skilled in the art should understand that on the basis of the technical solution of the present invention, those skilled in the art do not need to pay creative work Various modifications or variations that can be made are still within the protection scope of the present invention.

Claims (6)

1. A level self-defining multi-protocol digital audio signal generation system is characterized in that, comprising host computer, FPGA, digital-analog converter, described host computer is connected with FPGA, and described FPGA is connected with digital-analog converter; The FPGA includes a state code memory, a waveform generation module, an amplitude adjustment module, a data encoding module, a clock frequency division module and a protocol output module; The state code memory, which is connected to the input of the host computer, is used to store the state code in the digital audio coding; The waveform generation module is used to generate waveform data; The data encoding module is used to perform protocol encoding on the status code stored in the status code memory and the waveform data generated by the waveform generation module; The clock frequency division module is used to generate the bit clock required by the protocol output module; The amplitude adjustment module is used to adjust the amplitude of the data generated by the data encoding module and store it in a temporary RAM memory; The protocol output module, driven by the bit clock provided by the clock frequency division module, sequentially transmits the data after amplitude adjustment to the digital-to-analog converter; A level self-defining multi-protocol digital audio signal generation system also includes a signal conditioning circuit; the signal conditioning circuit includes a gain adjustment circuit and a single-ended differential switching circuit; The gain adjustment circuit is used to adjust the gain of the signal level output by the digital-to-analog converter; The single-ended differential switching circuit is used to switch the transmission mode of the output audio signal. 2. The level self-defining multi-protocol digital audio signal generation system as claimed in claim 1, wherein the digital-to-analog converter adopts a high-precision digital-to-analog converter. 3. The level self-defining multi-protocol digital audio signal generation method based on the arbitrary described system of claim 1 to 2, is characterized in that, comprises the following steps: Step 1, select the protocol standard of the digital audio signal in the host computer software setting interface, and the host computer dynamically loads the interface circuit with the corresponding digital audio protocol encoding program code through the FPGA according to the selected protocol standard; Step 2, the upper computer software setting interface sets the configuration information for the digital audio protocol standard, and sends the configuration information to the status code memory of the FPGA for storage; Step 3: The digital audio protocol encoding setting is performed inside the FPGA, and the channel status code of each frame is sequentially read from the status code memory, and combined with the waveform data generated by the waveform generation module to obtain the digital audio encoding data stream; Step 4: According to the logic level set by the host computer, the FPGA adjusts the amplitude of the digital audio coded data stream and stores it in the temporary RAM memory, and outputs it to the digital-to-analog converter driven by the bit clock output by the clock frequency division circuit ; Step 5, the digital-to-analog converter receives the amplitude-adjusted digital audio data stream, performs digital-to-analog conversion, and outputs a single-ended or differential digital audio signal waveform, and outputs it to the signal conditioning circuit; Step 6: The signal conditioning circuit receives single-ended or differential digital audio signal waveforms, performs shaping and filtering on the single-ended or differential digital audio signal waveforms, and outputs digital audio signals conforming to digital audio signal protocol standards. 4. The level self-defining multi-protocol digital audio signal generation method as claimed in claim 3, characterized in that, in said step 2, said configuration information includes each bit status code of each channel of each frame. 5. level self-defining multi-protocol digital audio signal generation method as claimed in claim 3, is characterized in that, in described step 2, the protocol standard of described digital audio signal comprises AES/EBU or S/PDIF general digital audio frequency protocol. 6. the self-defining multi-protocol digital audio signal generation method of level as claimed in claim 3 is characterized in that, in described step 4, FPGA utilizes amplitude calibration algorithm to carry out amplitude adjustment to digital audio data flow.