CN106354186A - Low-voltage-difference linear voltage stabilizer - Google Patents

Abstract

The invention discloses a low-voltage-difference linear voltage stabilizer. The voltage stabilizer comprises an error amplifier (10), a voltage follower (20), an output circuit (30) and a compensation circuit (40). The output end of the error amplifier (10) has the high impedance characteristic, a pole p1 is formed at the output end, the output end of the error amplifier (10) is connected with the input end of the voltage follower (20), parasitic capacitance of the output end of the error amplifier is reduced, so the formed pole is far away from the original point, and the pole p1 is compensated for through a first compensation unit; besides, the compensation circuit (40) compensates a pole p2 formed by the grid electrode of a compensation power tube MP301, stability of loops in a full-load range is guaranteed in the compensation mode, accordingly influences of the pole of the error amplifier on the PSRR are eliminated, and characteristics of the PSRR are improved. An LDO circuit effectively expands the bandwidth of the loops, transient characteristics are improved, and a circuit implementation mode is simple.

Description

A kind of low pressure difference linear voltage regulator

Technical field

The invention belongs to electronic circuit technology field is and in particular to arrive a kind of low pressure difference linear voltage regulator.

Background technology

It is little, electric that low pressure difference linear voltage regulator (ldo, low-dropout regulator) has output noise The advantages of line structure is simple, chip occupying area is little and voltage ripple is little, is important in electric power management circuit Ingredient.Ldo can provide output ripple and low for noise-sensitive circuit such as analog circuit and radio circuits Power supply and preferable PSRR (psrr, power supply rejection ration), and relatively low The performance of noise, thus be widely used in handheld device and portable type electronic product.

With the fast development of integrated circuit, working frequency of chip improves constantly, the psrr performance of ldo Decrease, power supply noise affects the performance of whole system by ldo, leads to system can not meet high frequency The application requirement of working environment.For example, in the ldo cascading with Switching Power Supply, if the ldo of rear class High frequency psrr characteristic is not high, and the high frequency output ripple voltage leading to Switching Power Supply is transferred to ldo output Level, thus affecting the performance of ldo load circuit, the such as noise-sensitive module such as digital-to-analogue conversion, radio frequency, Weaken and even deteriorate systematic function.

As can be seen here, the psrr characteristic improving ldo is the problem of current urgent need to resolve.

Content of the invention

The present invention provides a kind of low pressure difference linear voltage regulator, in order to improve the psrr characteristic of ldo.

The embodiment of the present invention provides a kind of low pressure difference linear voltage regulator to include: error amplifier (10), voltage Follower (20), output circuit (30) and compensation circuit (40)；

The first input end of error amplifier (10) connects to reference voltage output terminal, output circuit (30) Voltage output end directly or connect to the second input of error amplifier (10) after partial pressure；

The input of voltage follower (20) connects to the outfan of error amplifier (10), voltage follow The outfan of device (20) connects to the input of output circuit (30)；

Output circuit (30) includes power tube mp301 and the first compensating unit, the source of power tube mp301 Pole connects to voltage input end, the grid of power tube mp301 as output circuit (30) input with The outfan of voltage follower (20) connects, and the drain electrode of power tube mp301 connects to output circuit (30) Outfan, the first compensating unit is connected between outfan and the earth terminal of output circuit (30)；

The input of compensation circuit (40) connects to the outfan of output circuit (30), compensation circuit (40) Outfan connect to the outfan of error amplifier (10), compensation circuit (40) includes electric capacity c401.

Preferably, voltage follower (20) includes the first amplifier a201, the second amplifier a202 and the Two compensating units；The first input end of the first amplifier a201 connects to the grid of power tube mp301, the Second input of one amplifier a201, as the input of voltage follower (20), connects and puts to error The outfan of big device (10), the outfan of the first amplifier a201 connects to the second amplifier a202's Input；The outfan of the second amplifier a202 as the outfan of voltage follower (20), connect to The grid of power tube mp301；Second compensating unit is connected to input and the output of the second amplifier a202 Between end, the second compensating unit includes the electric capacity c201 being connected in series and resistance r201.

Preferably, the first compensating unit includes the electric capacity c301 connecting side by side and resistance r301.

Preferably, also include in output circuit (30) for carrying out to the output voltage of output circuit (30) The partial pressure unit of partial pressure, the outfan of described partial pressure unit is connected with the second input of error amplifier (10) Connect, the voltage between the outfan of described partial pressure unit and earth terminal is less than the outfan of output circuit (30) Voltage and earth terminal between.

Preferably, described voltage follower (20) include pmos pipe mp201, pmos pipe mp202, Pmos pipe mp203, nmos pipe mn201, nmos pipe mn202, nmos pipe mn203, Nmos pipe mn204, and electric capacity c201 and resistance r201；The grid of pmos pipe mp201 is respectively It is connected with the grid of pmos pipe mp202 and the drain electrode of pmos pipe mp201, nmos pipe mn201 Drain electrode be connected with the drain electrode of nmos pipe mn202 and the source electrode of nmos pipe mn203 respectively, The drain electrode of pmos pipe mp201 source electrode and the pmos pipe mp201 with nmos pipe mn201 respectively Grid connect, the drain electrode of pmos pipe mp202 is connected with the source electrode of nmos pipe mn202, pmos The drain electrode of pipe mp203 respectively with the source electrode of nmos pipe mn204 and the grid of nmos pipe mn202 Pole connects；The source electrode of pmos pipe mp201, the source electrode of pmos pipe mp202, pmos pipe mp203 Source electrode connect voltage input end respectively, the grid of nmos pipe mn203, nmos pipe mn204 Grid connects the first biased electrical pressure side, the drain electrode of nmos pipe mn203, nmos pipe mn204 respectively Drain electrode connect earth terminal respectively；Electric capacity c201 and resistance r201 is connected on the leakage of pmos pipe mp203 Between the drain electrode of pole and pmos pipe mp202；The grid of nmos pipe mn201 and error amplifier (10) outfan connects, and the drain electrode of pmos pipe mp203 is connected with the input of output circuit (30) Connect.

Preferably, compensation circuit (40) is located at the output stage of error amplifier (10), compensation circuit (40) Including pmos pipe mp401, nmos pipe mn401, nmos pipe mn402 and compensating electric capacity c401； The drain electrode of pmos pipe mp401 connects to the source electrode of nmos pipe mn401, nmos pipe mn401's Drain electrode connects to the source electrode of nmos pipe mn402；The source electrode of pmos pipe mp401 connects to described electricity Pressure input, the grid of nmos pipe mn401 connects the second biased electrical pressure side, nmos pipe mn402 Grid connect the first biased electrical pressure side, the drain electrode of nmos pipe mn402 connects to earth terminal；Electric capacity c401 It is connected between the drain electrode of power tube mp401 and the voltage output end of output circuit (30)；Pmos manages The drain electrode of mp401 is connected with the input of voltage follower (20) as the outfan of compensation circuit (40).

Preferably, described output circuit (30) include electric capacity c301, resistance r301, resistance r302 and Resistance r303；Resistance r302 and resistance r303 series connection after connect to output circuit (30) outfan and Between earth terminal, form described partial pressure unit, the outfan of described partial pressure unit connects to error amplifier (10) the second input, the voltage between the outfan of described partial pressure unit and earth terminal is less than output electricity Voltage between the outfan on road (30) and earth terminal；Electric capacity c301 is connected with after resistance r301 parallel connection To the output and ground of output circuit (30).

Preferably, described error amplifier (10) include pmos pipe mp101, pmos pipe mp102, Pmos pipe mp103, pmos pipe mp104, pmos pipe mp401, nmos pipe mn101, nmos Pipe mn102, nmos pipe mn401, nmos pipe mn402.

The drain electrode of pmos pipe mp101 is managed with the source electrode of pmos pipe mp102 and pmos respectively The source electrode of mp103 connects, and the drain electrode of pmos pipe mp102 is connected with the drain electrode of nmos pipe mn101, The drain electrode of pmos pipe mp103 is connected with the drain electrode of nmos pipe mn401；Pmos pipe mp104's Grid is connected with the grid of pmos pipe mp401 and the drain electrode of pmos pipe mp104 respectively, pmos The drain electrode of pipe mp104 respectively with the source electrode of nmos pipe mn101 and the grid of pmos pipe mp104 Connect；The drain electrode of nmos pipe m101 is managed with the drain electrode of pmos pipe mp103 and nmos respectively The source electrode of m102 connects, the drain electrode of nmos pipe m401 respectively with the drain electrode of pmos pipe mp102, The source electrode of nmos pipe m402 and electric capacity c401 connect.

The grid of nmos pipe m102, nmos pipe mn402 connects the first biased electrical pressure side, nmos respectively The grid of pipe m101, nmos pipe mn401 connects the second biased electrical pressure side, pmos pipe mp101 respectively Grid connect the 3rd biased electrical pressure side；Pmos pipe mp101, pmos pipe mp104, pmos manage The source electrode of mp401 connects voltage input end respectively；Nmos pipe mn102, nmos pipe mn402's Drain electrode connects earth terminal respectively.

The drain electrode of pmos pipe mp401 is managed with nmos respectively as the outfan of error amplifier (10) The grid of the source electrode of mn401 and nmos pipe mn201 connects；The grid of pmos pipe mp102 is made For the first input end of error amplifier (10), it is connected with reference voltage output terminal；Pmos pipe mp103 Grid be connected with the outfan of partial pressure unit as the second input of error amplifier (10).

Preferably, described power tube mp301 manages for pmos.

Preferably, described first input end is inverting input, and described second input is normal phase input end.

The low pressure difference linear voltage regulator of the present invention, including error amplifier (10), voltage follower (20), Output circuit (30) and compensation circuit (40), output circuit (30) includes power tube mp301 and the One compensating unit.Generally, error amplifier (10) outfan has high-impedance behavior, can be in its outfan Limit p can be formed₁.The embodiment of the present invention by the outfan of error amplifier (10) connect to voltage with With the input of device (20), thus reducing the parasitic capacitance of error amplifier output so that what it formed Limit is away from initial point, and utilizes the first compensating unit to this limit p₁Compensate；Additionally, compensation circuit (40) Compensate limit p that power tube mp301 grid is formed₂, full load model be ensure that by above compensation way Enclosing the stability of inner ring road, thus eliminating the impact to psrr for the error amplifier limit, improve psrr Characteristic.

Brief description

For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to institute in embodiment description Need the accompanying drawing using to briefly introduce it should be apparent that, drawings in the following description are only the present invention Some embodiments, for those of ordinary skill in the art, in the premise not paying creative labor Under, other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 is a kind of circuit theory diagrams of low pressure difference linear voltage regulator in prior art；

Fig. 2 is a kind of circuit theory diagrams of low pressure difference linear voltage regulator provided in an embodiment of the present invention；

Fig. 3 is a kind of poles and zeros assignment provided in an embodiment of the present invention and phase margin curve synoptic diagram；

Fig. 4 is a kind of a kind of electricity of the circuit theory diagrams of low pressure difference linear voltage regulator provided in an embodiment of the present invention Road implementation；

Fig. 5 is a kind of a kind of electricity of the circuit theory diagrams of low pressure difference linear voltage regulator provided in an embodiment of the present invention The equivalent circuit diagram of compensation circuit in the implementation of road.

Specific embodiment

In order that the object, technical solutions and advantages of the present invention are clearer, below in conjunction with accompanying drawing to this Bright be described in further detail it is clear that described embodiment is only a part of embodiment of the present invention, Rather than whole embodiments.Based on the design concept of the embodiment of the present invention, those of ordinary skill in the art exist Do not make under the premise of creative work by the type of transistor is replaced etc. with the institute that mode is obtained There are other embodiments also should fall under the scope of the present invention.

What Fig. 1 was exemplary shows the basic circuit schematic diagram of ldo in prior art.As illustrated, ldo Include error amplifier a1, power tube mp0, power tube mp1 and power tube mp2, feedback resistance R1 and feedback resistance r2, output capacitance c1 and output capacitance dead resistance r3, output resistance r4.Its In, power tube mp1 and power tube mp2 constitutes caching, for driving power pipe mp0.Error amplifier A1 amplifies the difference between fed-back output voltage and reference voltage, thus increase or reduce power tube mp0 carrying For electric current be electric capacity c1 discharge and recharge, realize stablizing of output voltage.

The circuit theory of the prior art according to Fig. 1, with error amplifier a1 end for a point, power tube The intersection point of the drain electrode of the grid of mp0, the source electrode of power tube mp1 and power tube mp2 is b point, draws ring Road open-loop transfer function is:

$\begin{array}{c}{a}_{oloop}=\frac{r_2}{r_1+r_2}\frac{g_{mea}{r}_{oa}{g}_{mmp1}{r}_{ob}{g}_{mmp0}{r}_{dsmp0}\left(1+{\mathrm{sr}}_3{c}_1\right)}{\left(1+{\mathrm{sr}}_{oa}{c}_a\right)\left(1+{\mathrm{sr}}_{ob}{c}_b\right)\left\{1+s\[\left(r_1+r_2\right)\left|\right|r_4\left|\right|r_{dsmp0}\]c_1\right\}}\\ =\frac{r_2}{r_1+r_2}\frac{g_{mea}{r}_{oa}{g}_{mmp1}{r}_{ob}{g}_{mmp0}{r}_{dsmp0}\left(1+\frac{s}{z_{r3}}\right)}{\left(1+\frac{s}{p_a}\right)\left(1+\frac{s}{p_b}\right)\left(1+\frac{s}{p_c}\right)}\end{array}---\left(1\right)$

In formula (1), g_meaFor the equivalent transconductance of error amplifier a1, g_mmp1、g_mmp0It is respectively power tube Mp1, the mutual conductance of power tube mp0, r_oa、r_obIt is respectively a point, the equivalent output impedance of b point, r_dsmp0For The equiva lent impedance of power tube mp0, c_a、c_bIt is respectively a point, the parasitic capacitance of b point.

Wherein, loop zero pole point z_r3And p_a、p_b、p_cIt is respectively as follows:

$p_a=\frac{1}{r_{oa}{c}_a},$

$p_b=\frac{1}{r_{ob}{c}_b},$

$p_c=\frac{1}{\[(r_1+r_2)\left|\right|r_4\left|\right|r_{dsmp0}\]c_1},$

$z_{r3}=\frac{1}{r_3{c}_1}.$

Outfan parasitic poles p comprising error amplifier a1 in open-loop transfer function are obtained by formula (1)_a、 Power tube mp0 parasitic gate limit p_b, output limit p_c3 limits, one by output capacitance c1 and defeated Go out the high frequency zero of capacitive parasitic resistance r3 formation.

In ldo circuit, the zero point in loop gain and loop, pole location are closely related.Work as loop When a limit, loop gain is declined with the slope of -20db/dec；When one zero point occurs, loop Gain is risen with the slope of+20db/dec.

The PSRR psrr of ldo is in the case that input voltage is for small-signal sinusoidal excitation, output The quantitative description of the steady-state response of voltage.Do not consider error amplifier and reference voltage vref for power supply The impact of rejection ratio psrr, input voltage vin is represented by the gain of output end voltage vout:

$\frac{vout}{vin}=\frac{1+g_{mmp0}{r}_{dsmp0}}{1+\frac{r_{dsmp0}}{z_l}+\frac{r_{dsmp0}}{r_1+r_2}+\frac{r_2}{r_1+r_2}\frac{g_{mmp0}{r}_{dsmp0}{g}_{mea}{r}_{oa}{g}_{mmp1}{r}_{ob}(1+r_3{c}_{1}s)}{(1+{\mathrm{sr}}_{oa}{c}_a)(1+{\mathrm{sr}}_{ob}{c}_b)}}---\left(2\right)$

Wherein:

$z_l=\frac{r_4(1+r_3{c}_{1}s)}{1+(r_4+r_3)c_{1}s}\≈\frac{r_4(1+r_3{c}_{1}s)}{1+r_4{c}_{1}s}$

Abbreviation can be distinguished in the case of low frequency (s=0) and high frequency (s=∞) is:

$\frac{vout}{vin}(s=0)\≈\frac{1}{g_{mea}{r}_{oa}{g}_{mmp1}{r}_{ob}\frac{r_2}{r_1+r_2}}---\left(3\right)$

$\frac{vout}{vin}(s=\mathrm{\∞})\≈\frac{r_3}{r_{dsmp0}+r_3}---\left(4\right)$

In formula (2), the PSRR psrr of ldo depends on output limit p_a, p_bAnd gainDue to p_a, p_bLess, with the increase of frequency, psrr is leading Decay at limit, loop gain rapid decrease, power supply noise produces noise electricity by power tube mp0 Flow to outfan, thus limiting psrr；Especially in the case of heavy duty, power tube mp0 enters linear zone, Its equiva lent impedance r_dsmp0Progressively reduce so that numerator value quickly levels off to denominator value in formula (4), lead The psrr characteristic causing ldo deteriorates further in medium-high frequency.

In order to improve the psrr characteristic of ldo, the embodiment of the present invention by such scheme is improved and Extension.What Fig. 2 was exemplary shows that a kind of circuit of low pressure difference linear voltage regulator that inventive embodiments provide is former Reason figure, comprising: error amplifier 10, voltage follower 20, output circuit 30 and compensation circuit 40.

As shown in Fig. 2 the first input end of error amplifier 10 connects to reference voltage output terminal, export The voltage output end of circuit 30 directly or connects to the second input of described error amplifier 10 after partial pressure； The input of voltage follower 20 connects to the outfan of error amplifier 10, voltage follower 20 defeated Go out end to connect to the input of output circuit 30；Output circuit 30 includes power tube mp301 and first benefit Repay unit, the source electrode of power tube mp301 connects to voltage input end, the grid conduct of power tube mp301 The input of output circuit 30 is connected with the outfan of voltage follower 20, the drain electrode of power tube mp301 Connect to the outfan of output circuit 30, the first compensating unit is connected to the outfan of output circuit 30 and connects Between ground terminal, the first compensating unit includes the electric capacity c301 connecting side by side and resistance r301；Compensation circuit 40 input connects to the outfan of output circuit 30, and the outfan of compensation circuit 40 connects to be put to error The outfan of big device 10, compensation circuit 40 includes electric capacity c401.

Wherein, power tube mp301 can manage for pmos.

In embodiments of the present invention, the first input end of error amplifier and voltage follower is anti-phase input End, the second input of error amplifier and voltage follower is normal phase input end.Certainly, without departing from this When the spirit and scope of application are deformed, first input end can also be normal phase input end, the second input Can also be inverting input, the embodiment of the present invention is without limitation.

Output voltage vout obtains feedback voltage vfb, vfb and reference voltage vref after electric resistance partial pressure Carry out differential amplification through error amplifier 10, obtain a point voltage va, voltage va is through voltage follower 20 obtain c point voltage vc, and voltage vc controls the conducting state of power tube mp301, thus adjusting defeated Go out voltage vout.Realizing the stable feedback procedure of output voltage vout is: when vout raises, vfb liter Height, error amplifier 10 outfan a point voltage va raises, voltage follower 20 outfan c point voltage Vc increases, and voltage vc makes power tube mp301 pressure drop increase, and output voltage vout reduces.Defeated Go out voltage vout reduction feedback procedure to be similar to therewith, will not be described in detail herein.

Because error amplifier 10 outfan has high-impedance behavior, a limit can be formed in its outfan p₁, the outfan of error amplifier 10 is connected to the input of voltage follower 20, reduces error and amplify The parasitic capacitance of device 10 outfan is so that the limit of its formation is away from initial point, and utilizes the first compensating unit To this limit p₁Compensate；Additionally, compensation circuit 40 compensates the pole that power tube mp301 grid is formed Point p₂, ensure that the stability of full-load range inner ring road by above compensation way, thus eliminate error putting The impact to psrr for the limit that big device 10 is formed, improves psrr characteristic.

Preferably, voltage follower 20 includes the first amplifier a201, the second amplifier a202 and second Compensating unit；The first input end of the first amplifier a201 connects to the grid of power tube mp301, and first Second input of amplifier a201, as the input of voltage follower 20, connects to error amplifier 10 outfan；The outfan of the first amplifier a201 connects to the input of the second amplifier a202, The outfan of the second amplifier a202, as the outfan of voltage follower 20, connects to power tube mp301 Grid；Second compensating unit is connected between input and the outfan of the second amplifier a202, and second Compensating unit includes the electric capacity c201 being connected in series and resistance r201.

Wherein, the first amplifier a201 can adopt differential operational amplifier, and the second amplifier a202 can So that using common source operational amplifier, the second compensating unit can be realized by Miller's compensating circuit.

Reduce the parasitic electricity of error amplifier 10 outfan by the two stage amplifer structure of voltage follower 20 Hold so that limit p1 of its formation is away from initial point；The output impedance of voltage follower 20 is less simultaneously, makes The parasitic poles obtaining c point are approached to high frequency, and ensure its stability by miller compensation.

Preferably, the first compensating unit includes the electric capacity c301 connecting side by side and resistance r301, the first compensation Unit is connected between outfan and the earth terminal of described output circuit 30.Output capacitance c301 and its parasitism Resistance r304 forms parasitic zero point z₁, this zero compensation output limit p of error amplifier 10₁, thus Eliminate the impact to psrr for the error amplifier limit, improve the psrr characteristic of ldo.

Preferably, output circuit 30 includes partial pressure unit, and partial pressure unit is used for carrying out partial pressure to output voltage, At least include resistance r302, the outfan after resistance r302 partial pressure to error amplifier 10 is just connected To input.Specifically, partial pressure unit includes resistance r302 and the resistance r303 connecting, and sets resistance The resistance of r302 and resistance r303 can obtain different feedback voltage level.

Preferably, in compensation circuit 40, one end of electric capacity c401 connects to output voltage terminal, the other end and mistake A power tube mn401 in difference amplifier 10 is connected.Compensation circuit 40 forms zero point z₂, profit Parasitic poles p being formed with this zero compensation power tube mp301 grid₂.

Transmission function below by input small-signal is capable of entirely carrying load to the ldo of the embodiment of the present invention The principle of scope loop stability and raising psrr is specifically described:

As illustrated in fig. 2, it is assumed that a point, b point, the input mutual conductance of c point, output impedance are respectively as follows: g_ma、 g_mb、g_mp, r_oa、r_ob、r_oc；The mutual conductance of power tube mp301, equiva lent impedance and parasitic capacitance are respectively g_mmp0、 r_dsmp0And c_p；The value of electric capacity c401 is c_m1, the value of electric capacity c201 is c_m2, power tube mp301 grid Parasitic capacitance be c_p, the value of electric capacity c301 is c₁And its value of dead resistance r304 is r₃；Resistance r201 Value be r_m2, the value of resistance r301 is r₄, the value of resistance r302 is r₂, the value of resistance r303 is r₁； The equivalent transconductance of error amplifier 10 is g_mea；The equiva lent impedance of power tube mn401 in error amplifier 10 For 1/g_m.

The transmission function of a point to c point is represented by:

$\begin{array}{c}{a}_{\frac{v_c}{v_a}}=\frac{a_2{a}_3\[1+{\mathrm{sc}}_{m2}\left(r_{m2}-\frac{1}{g_{mb}}\right)\]/\left\{\[1+{\mathrm{sc}}_{m2}\left(r_{m2}+g_{mb}{r}_{ob}{r}_{oc}\right)\]\[1+\frac{c_p\left(r_{ob}+r_{m2}\right)r_{oc}}{r_{m2}+g_{mb}{r}_{ob}{r}_{oc}}\]\right\}}{1+a_2{a}_3\[1+{\mathrm{sc}}_{m2}\left(r_{m2}-\frac{1}{g_{mb}}\right)\]/\left\{\[1+{\mathrm{sc}}_{m2}\left(r_{m2}+g_{mb}{r}_{ob}{r}_{oc}\right)\]\[1+\frac{c_c\left(r_{ob}+r_{m2}\right)r_{oc}}{r_{m2}+g_{mb}{r}_{ob}{r}_{oc}}\]\right\}}\\ =\frac{1+{\mathrm{sc}}_{m2}\left(r_{m2}-\frac{1}{g_{mb}}\right)}{1+{\mathrm{sc}}_{m2}\left(r_{m2}-\frac{1}{g_{mb}}+\frac{1}{g_{ma}}\right)+\frac{s^2{c}_p{c}_{m2}}{g_{ma}{g}_{mb}}}\\ =\frac{1+{\mathrm{sc}}_{m2}\left(r_{m2}-\frac{1}{g_{mb}}\right)}{\[1+{\mathrm{sc}}_{m2}\left(r_{m2}-\frac{1}{g_{mb}}+\frac{1}{g_{ma}}\right)\]\[1+\frac{{\mathrm{sc}}_p}{g_{ma}{g}_{mb}{r}_{m2}-g_{ma}+g_{mb}}\]}\\ \≈\frac{1}{1+\frac{{\mathrm{sc}}_p}{g_{ma}{g}_{mb}{r}_{m2}-g_{ma}+g_{mb}}}\end{array}---\left(5\right)$

Wherein:

$z_{buffer0}=\frac{1}{c_{m2}(r_{m2}-\frac{1}{g_{mb}})},$

$p_{buffer0}=\frac{g_{ma}{g}_{mb}{r}_{m2}-g_{ma}+g_{mb}}{c_p},$

$p_{buffer1}=\frac{1}{c_{m2}(r_{m2}-\frac{1}{g_{mb}}+\frac{1}{g_{ma}})}$

Wherein, low-frequency pole p_buffer0, high frequency poles p_buffer1And low frequency zero point z_buffer0Respectively in voltage follower Formed in 20, low frequency zero point z_buffer0Compensate low-frequency pole p_buffer0So that voltage follower only has in loop One high frequency poles p_buffer1, weaken the impact to psrr for this limit, improve psrr midband characteristic, And improve the response speed of loop.

Loop small-signal transmission function is:

$\begin{array}{c}{a}_{oloop}=\frac{r_2}{r_1+r_2}\frac{g_{mea}{r}_{oa}{g}_{mmp0}{r}_{oeq}\left(1+s\frac{c_{m1}}{g_m}\right)\left(1+{\mathrm{sr}}_3{c}_1\right)}{\left(1+s\frac{r_{oa}{c}_a{c}_1}{c_1+g_{mmp0}{r}_{oa}{c}_{m1}}\right)\left\{1+{\mathrm{sr}}_{oeq}\left(c_1+g_{mmp0}{r}_{oa}{c}_{m1}\right)\right\}\left(1+\frac{{\mathrm{sc}}_p}{g_{ma}{g}_{mb}{r}_{m2}-g_{ma}+g_{mb}}\right)}\\ =g_{mea}{r}_{oa}{g}_{mmp0}{r}_{oeq}\frac{1}{1+\frac{s}{p_0}}\frac{1+\frac{s}{z_1}}{1+\frac{s}{p_1}}\frac{1+\frac{s}{z_2}}{1+\frac{s}{p_2}}\end{array}---\left(6\right)$

Wherein:

$r_{oeq}=(r_1+r_2)\left|\right|r_4\left|\right|r_{dsmp0},$

$p_0=\frac{1}{r_{oeq}(c_1+g_{mmp0}{r}_{oa}{c}_{m1})},$

$p_1=\frac{c_1+g_{mmp0}{r}_{oa}{c}_{m1}}{r_{oa}{c}_a{c}_1},$

$p_2=\frac{g_{ma}{g}_{mb}{r}_{m2}-g_{ma}+g_{mb}}{c_p},$

$z_1=\frac{1}{r_3{c}_1},$

$z_2=\frac{g_m}{c_{m1}}.$

Wherein, symbol | | represent in parallel.

Can be drawn by formula (6), in the ldo loop of the embodiment of the present invention, remove dominant pole p₀Outward, other Limit, zero point are corresponding.With the difference of load capacity, in the case of not increasing any extra power consumption, all Can effectively ensure that the loop stability of ldo.

Under case of heavy load, in bandwidth range, comprise limit p₀、p₁、p₂And zero point z₁、z₂, pole in loop Point p₁、p₂Respectively by zero point z₁、z₂Compensate so that only existing a dominant pole p in loop₀It is ensured that ring The stability on road；In the case of underloading, dominant pole p₀Move so that gain reduction point reduces to initial point, bandwidth Reduce, in limit p of bandwidth range inner ring road₁By zero point z₁Compensate, limit p₂And zero point z₂Outside bandwidth, Do not consider it is ensured that only having a dominant pole p in loop₀, realize loop stability, improve psrr characteristic.

What Fig. 3 was exemplary shows a kind of poles and zeros assignment and the phase margin curve chart of the embodiment of the present invention. As shown in figure 3, solid line represents the gain versus frequency change curve under light load condition, dotted line represents heavy duty In the case of Phase-Frequency change curve.It can be seen that, limit p₁Approximate Zeros z₁, limit p₂Approach z₂, lead to Zero crossing compensates limit, the target of realization raising psrr characteristic, and the ldo's of the embodiment of the present invention Psrr characteristic is improved under underloading and case of heavy load.

The psrr transmission function of the ldo of the embodiment of the present invention is represented by:

$\frac{vout}{vin}=\frac{1+g_{mmp0}{r}_{dsmp0}}{1+\frac{r_{dsmp0}}{z_l}+\frac{r_{dsmp0}}{r_1+r_2}+\frac{g_{mea}{r}_{oa}{g}_{mmp0}{r}_{dsp}{r}_2}{r_1+r_2}\frac{1+\frac{s}{z_1}}{1+\frac{s}{p_1}}\frac{1+\frac{s}{z_2}}{1+\frac{s}{p_2}}}---\left(7\right)$

Can be obtained by formula (7), the ldo of the embodiment of the present invention utilizes output stage zero point z of output circuit 30₁And Zero point z that compensation circuit 40 is formed₂Compensate for output limit p of error amplifier 10₁And voltage follower 20 Output limit p₂, weaken the effect that two limits reduce loop gain, it is achieved thereby that improving medium-high frequency The effect of psrr.

Fig. 2 shows the circuit theory of low pressure difference linear voltage regulator provided in an embodiment of the present invention.Based on Fig. 2 And the above-mentioned description to low differential voltage linear voltage stabilizer circuit principle, in actual applications, pmos can be passed through Pipe, the device such as nmos pipe, electric capacity, resistance, realize the low pressure difference linear voltage regulator equivalent with Fig. 2.

What Fig. 4 was exemplary shows that a kind of circuit of low pressure difference linear voltage regulator provided in an embodiment of the present invention is former A kind of circuit implementations of reason figure, the error amplifier 10 of this low pressure difference linear voltage regulator, voltage follower 20th, output circuit 30 and compensation circuit 40, is separated to distinguish by the 4 of in figure dotted line frames.

In the embodiment of the present invention, the first bias voltage, the second bias voltage, the 3rd bias voltage are used respectively Vb1, vb2, vb3 represent, and bias voltage can be provided by external circuit it is also possible to pass through to increase partially Circuits internally produce, and this is not restricted.

Error amplifier 10 include pmos pipe mp101, pmos pipe mp102, pmos pipe mp103, Pmos pipe mp104, pmos pipe mp401, nmos pipe mn101, nmos pipe mn102, Nmos pipe mn401, nmos pipe mn402.

The drain electrode of pmos pipe mp101 is managed with the source electrode of pmos pipe mp102 and pmos respectively The source electrode of mp103 connects, and the drain electrode of pmos pipe mp102 is connected with the drain electrode of nmos pipe mn101, The drain electrode of pmos pipe mp103 is connected with the drain electrode of nmos pipe mn401；Pmos pipe mp104's Grid is connected with the grid of pmos pipe mp401 and the drain electrode of pmos pipe mp104 respectively, pmos The drain electrode of pipe mp104 respectively with the source electrode of nmos pipe mn101 and the grid of pmos pipe mp104 Connect；The drain electrode of nmos pipe m101 is managed with the drain electrode of pmos pipe mp103 and nmos respectively The source electrode of m102 connects, the drain electrode of nmos pipe m401 respectively with the drain electrode of pmos pipe mp102, The source electrode of nmos pipe m402 and electric capacity c401 connect.

The grid of nmos pipe m102, nmos pipe mn402 connects the first biased electrical pressure side, nmos respectively The grid of pipe m101, nmos pipe mn401 connects the second biased electrical pressure side, pmos pipe mp101 respectively Grid connect the 3rd biased electrical pressure side.

The source electrode of pmos pipe mp101, pmos pipe mp104, pmos pipe mp401 connects electricity respectively Pressure input, the drain electrode of nmos pipe mn102, nmos pipe mn402 connects earth terminal respectively.

The drain electrode of pmos pipe mp401 is managed with nmos respectively as the outfan of error amplifier (10) The grid of the source electrode of mn401 and nmos pipe mn201 connects；The grid of pmos pipe mp102 is made For the first input end of error amplifier (10), it is connected with reference voltage output terminal；Pmos pipe mp103 Grid be connected with the outfan of partial pressure unit as the second input of error amplifier (10).

Wherein, the outfan of partial pressure unit is the tapping end of resistance r302 and resistance r303.

Voltage follower 20 includes pmos pipe mp201, pmos pipe mp202, pmos pipe mp203, Nmos pipe mn201, nmos pipe mn202, nmos pipe mn203, nmos pipe mn204, And electric capacity c201 and resistance r201.

Wherein, the grid of pmos pipe mp201 grid and the pmos with pmos pipe mp202 respectively The drain electrode of pipe mp201 connects, the drain electrode leakage with nmos pipe mn202 respectively of nmos pipe mn201 The source electrode of pole and nmos pipe mn203 connects, the drain electrode of pmos pipe mp201 respectively with nmos The grid of the source electrode of pipe mn201 and pmos pipe mp201 connects, the drain electrode of pmos pipe mp202 It is connected with the source electrode of nmos pipe mn202, the drain electrode of pmos pipe mp203 is managed with nmos respectively The grid of the source electrode of mn204 and nmos pipe mn202 connects.

The source electrode of pmos pipe mp201, the source electrode of pmos pipe mp202, the source of pmos pipe mp203 Pole connects voltage input end, the grid of nmos pipe mn203, the grid of nmos pipe mn204 respectively Connect vb1 end respectively, the drain electrode of nmos pipe mn203, the drain electrode of nmos pipe mn204 connect respectively Connect earth terminal；Electric capacity c201 and resistance r201 is connected on drain electrode and the pmos of pmos pipe mp203 Between the drain electrode of pipe mp202；The grid of nmos pipe mn201 is connected with the outfan of error amplifier 10 Connect, the drain electrode of pmos pipe mp203 is connected with the input of output circuit 30.

Output circuit 30 includes output capacitance c301, output load resistance r301, divider resistance r302 and r303.Connect between output voltage terminal and earth terminal after divider resistance r302 and r303 series connection, obtain Outfan after partial pressure connects the grid of the mp103 to error amplifier 10；Output capacitance c301 with defeated Connect between output voltage terminal and earth terminal after going out load resistance r301 parallel connection.

Compensation circuit 40 is located at the output stage of error amplifier 10, and compensation circuit 40 includes pmos pipe Mp401, nmos pipe mn401, nmos pipe mn402 and compensating electric capacity c401.

The drain electrode of pmos pipe mp401 connects to the source electrode of nmos pipe mn401, nmos pipe mn401 Drain electrode connect to nmos pipe mn402 source electrode；The source electrode of pmos pipe mp401 connects to described Voltage input end, the grid of nmos pipe mn401 connects vb2 end, the grid of nmos pipe mn402 Connect vb1 end, the drain electrode of nmos pipe mn402 connects to earth terminal；Electric capacity c401 is connected to power Between the voltage output end of the drain electrode of pipe mp401 and output circuit 30；The drain electrode of pmos pipe mp401 Outfan as compensation circuit 40 is connected with the input of voltage follower 20.

Wherein, compensation circuit 40 is simultaneously as the output stage of error amplifier 10, its equivalent circuit such as Fig. 5 Shown, can obtain the low frequency small-signal gain of ldo in the embodiment of the present invention:

A=g_mmn2r_out=g_mmn2[(g_mmn2r_omn2r_omn4)||r_omp5] (8)

Wherein, g_mmn2Equivalent transconductance value for mn401, r_omn2、r_omn4、r_omp5Respectively mn401, The equivalent impedance of mn402, mp401.

By above description as can be seen that adopting voltage follower (20) driving power pipe mp301, pass through The compensating action of the second compensating unit make to be formed in voltage follower (20) low-frequency pole, one high Frequency limit and a low frequency zero point, the internal low-frequency pole within low frequency zero compensation of voltage follower (20) Point, therefore voltage follower (20) only have high frequency poles in loop, weaken this limit to psrr Impact, improve response speed and the psrr medium-high frequency characteristic of loop.Ldo proposed by the invention Circuit has expanded loop bandwidth effectively, improves transient response, and circuit implementations are simple.

The foregoing is only the preferred embodiment of the application, be not limited to the application, all the application's Within spirit and principle, any modification, equivalent substitution and improvement made etc., should be included in the protection of the application Within the scope of.

The application is the stream with reference to method, equipment (system) and computer program according to the embodiment of the present application Journey figure and/or block diagram are describing.It should be understood that can be by computer program instructions flowchart and/or block diagram In each flow process and/or the flow process in square frame and flow chart and/or block diagram and/or square frame combination. Can provide these computer program instructions to general purpose computer, special-purpose computer, Embedded Processor or other can compile The processor of journey data handling equipment is to produce a machine so that processing by computer or other programmable datas The instruction of the computing device of equipment produces for realizing in one flow process of flow chart or multiple flow process and/or block diagram The device of the function of specifying in one square frame or multiple square frame.

These computer program instructions may be alternatively stored in and can guide computer or other programmable data processing device with spy Determine in the computer-readable memory that mode works so that the instruction being stored in this computer-readable memory produces Including the manufacture of command device, this command device is realized in one flow process of flow chart or multiple flow process and/or square frame The function of specifying in one square frame of figure or multiple square frame.

These computer program instructions also can be loaded in computer or other programmable data processing device so that Series of operation steps is executed on computer or other programmable devices to produce computer implemented process, thus On computer or other programmable devices, the instruction of execution is provided for realizing in one flow process of flow chart or multiple flow process And/or the step of the function of specifying in one square frame of block diagram or multiple square frame.

Although having been described for the preferred embodiment of the application, those skilled in the art once know basic wound The property made concept, then can make other change and modification to these embodiments.So, claims are intended to solve It is interpreted as including preferred embodiment and fall into being had altered and changing of the application scope.

Obviously, those skilled in the art can carry out various changes and modification without deviating from the application's to the application Spirit and scope.So, if these modifications of the application and modification belong to the application claim and its equivalent skill Within the scope of art, then the application is also intended to comprise these changes and modification.

Claims (10)

1. a kind of low pressure difference linear voltage regulator is it is characterised in that include: error amplifier (10), voltage Follower (20), output circuit (30) and compensation circuit (40)；

The first input end of error amplifier (10) connects to reference voltage output terminal, output circuit (30) Voltage output end directly or connect to the second input of error amplifier (10) after partial pressure；

The input of voltage follower (20) connects to the outfan of error amplifier (10), voltage follow The outfan of device (20) connects to the input of output circuit (30)；

Output circuit (30) includes power tube mp301 and the first compensating unit, the source electrode of power tube mp301 Connect to voltage input end, the grid of power tube mp301 is as the input of output circuit (30) and voltage The outfan of follower (20) connects, and the drain electrode of power tube mp301 connects defeated to output circuit (30) Go out end, the first compensating unit is connected between outfan and the earth terminal of output circuit (30)；

The input of compensation circuit (40) connects to the outfan of output circuit (30), compensation circuit (40) Outfan connect to the outfan of error amplifier (10), compensation circuit (40) includes electric capacity c401.

2. low pressure difference linear voltage regulator as claimed in claim 1 is it is characterised in that voltage follower (20) Including the first amplifier a201, the second amplifier a202 and the second compensating unit；

The first input end of the first amplifier a201 connects to the grid of power tube mp301, the first amplifier Second input of a201, as the input of voltage follower (20), connects to error amplifier (10) Outfan, the outfan of the first amplifier a201 connects to the input of the second amplifier a202；

The outfan of the second amplifier a202, as the outfan of voltage follower (20), connects to power tube The grid of mp301；

Second compensating unit is connected between input and the outfan of the second amplifier a202.

3. low pressure difference linear voltage regulator as claimed in claim 2 is it is characterised in that the second compensating unit bag Include the electric capacity c201 being connected in series and resistance r201.

4. low pressure difference linear voltage regulator as claimed in claim 1 is it is characterised in that the first compensating unit bag Include the electric capacity c301 and resistance r301 of connection arranged side by side.

5. low pressure difference linear voltage regulator as claimed in claim 1 is it is characterised in that output circuit (30) In also include for the output voltage of output circuit (30) is carried out with partial pressure partial pressure unit, described partial pressure list Unit outfan be connected with the second input of error amplifier (10), the outfan of described partial pressure unit and Voltage between earth terminal is less than the voltage between the outfan of output circuit (30) and earth terminal.

6. the low pressure difference linear voltage regulator as any one of claim 1 to 5 is it is characterised in that institute State voltage follower (20) and include pmos pipe mp201, pmos pipe mp202, pmos pipe mp203, Nmos pipe mn201, nmos pipe mn202, nmos pipe mn203, nmos pipe mn204, And electric capacity c201 and resistance r201；

The grid of pmos pipe mp201 grid and the pmos pipe mp201 with pmos pipe mp202 respectively Drain electrode connect, drain electrode drain electrode and the nmos with nmos pipe mn202 respectively of nmos pipe mn201 The source electrode of pipe mn203 connects, the drain electrode source with nmos pipe mn201 respectively of pmos pipe mp201 Grid connection, the drain electrode of pmos pipe mp202 and the nmos pipe mn202 of pole and pmos pipe mp201 Source electrode connect, drain electrode source electrode and the nmos with nmos pipe mn204 respectively of pmos pipe mp203 The grid of pipe mn202 connects；

The source electrode of pmos pipe mp201, the source electrode of pmos pipe mp202, the source of pmos pipe mp203 Pole connects voltage input end respectively, and the grid of nmos pipe mn203, the grid of nmos pipe mn204 divide Do not connect the first biased electrical pressure side, the drain electrode of nmos pipe mn203, the drain electrode of nmos pipe mn204 divide Lian Jie not earth terminal；

Electric capacity c201 and resistance r201 is connected on drain electrode and the pmos pipe mp202 of pmos pipe mp203 Drain electrode between；

The grid of nmos pipe mn201 is connected with the outfan of error amplifier (10), pmos pipe mp203 Drain electrode be connected with the input of output circuit (30).

7. the low pressure difference linear voltage regulator as any one of claim 1 to 5 is it is characterised in that mend Repay the output stage that circuit (40) is located at error amplifier (10), compensation circuit (40) includes pmos pipe Mp401, nmos pipe mn401, nmos pipe mn402 and compensating electric capacity c401；

The drain electrode of pmos pipe mp401 connects to the source electrode of nmos pipe mn401, nmos pipe mn401 Drain electrode connect to nmos pipe mn402 source electrode；

The source electrode of pmos pipe mp401 connects to described voltage input end, the grid of nmos pipe mn401 Connect the second biased electrical pressure side, the grid of nmos pipe mn402 connects the first biased electrical pressure side, nmos The drain electrode of pipe mn402 connects to earth terminal；

Electric capacity c401 be connected to the drain electrode of power tube mp401 and output circuit (30) voltage output end it Between；

The drain electrode of pmos pipe mp401 is as outfan and the voltage follower (20) of compensation circuit (40) Input connect.

8. the low pressure difference linear voltage regulator as any one of claim 1 to 5 is it is characterised in that institute State output circuit (30) and include electric capacity c301, resistance r301, resistance r302 and resistance r303；

Resistance r302 and resistance r303 series connection after connect to output circuit (30) output and ground it Between, form described partial pressure unit, the outfan of described partial pressure unit connects to the of error amplifier (10) Two inputs, the voltage between the outfan of described partial pressure unit and earth terminal is less than output circuit (30) Voltage between outfan and earth terminal；

Be connected after electric capacity c301 and resistance r301 parallel connection to output circuit (30) output and ground it Between.

9. the low pressure difference linear voltage regulator as any one of claim 1 to 5 is it is characterised in that institute State error amplifier (10) include pmos pipe mp101, pmos pipe mp102, pmos pipe mp103, Pmos pipe mp104, pmos pipe mp401, nmos pipe mn101, nmos pipe mn102, nmos Pipe mn401, nmos pipe mn402；

The drain electrode of pmos pipe mp101 source electrode and the pmos pipe mp103 with pmos pipe mp102 respectively Source electrode connect, the drain electrode of pmos pipe mp102 is connected with the drain electrode of nmos pipe mn101, pmos The drain electrode of pipe mp103 is connected with the drain electrode of nmos pipe mn401；

The grid of pmos pipe mp104 grid and the pmos pipe mp104 with pmos pipe mp401 respectively Drain electrode connect, drain electrode source electrode and the pmos with nmos pipe mn101 respectively of pmos pipe mp104 The grid of pipe mp104 connects；The drain electrode of the nmos pipe m101 drain electrode with pmos pipe mp103 respectively And the source electrode of nmos pipe m102 connects, the drain electrode of nmos pipe m401 respectively with pmos pipe mp102 Drain electrode, the source electrode of nmos pipe m402 and electric capacity c401 connect；

The grid of nmos pipe m102, nmos pipe mn402 respectively with the first biased electrical press bond, The grid of nmos pipe m101, nmos pipe mn401 respectively with the second biased electrical press bond, pmos The grid of pipe mp101 and the 3rd biased electrical press bond；

The source electrode of pmos pipe mp101, pmos pipe mp104, pmos pipe mp401 connects voltage respectively Input, the drain electrode of nmos pipe mn102, nmos pipe mn402 connects earth terminal respectively；

The drain electrode of pmos pipe mp401, as the outfan of error amplifier (10), is managed with nmos respectively The grid of the source electrode of mn401 and nmos pipe mn201 connects；The grid conduct of pmos pipe mp102 The first input end of error amplifier (10), is connected with reference voltage output terminal；Pmos pipe mp103's Grid, as the second input of error amplifier (10), is connected with the outfan of partial pressure unit.

10. the low pressure difference linear voltage regulator as any one of claim 1 to 5 it is characterised in that Described first input end is inverting input, and described second input is normal phase input end.