CN106383762B - A kind of verification method for dram controller - Google Patents
A kind of verification method for dram controller Download PDFInfo
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- CN106383762B CN106383762B CN201610794864.4A CN201610794864A CN106383762B CN 106383762 B CN106383762 B CN 106383762B CN 201610794864 A CN201610794864 A CN 201610794864A CN 106383762 B CN106383762 B CN 106383762B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
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Abstract
A kind of verification method for dram controller of the present invention, including, step 1 initializes dram controller according to the system schema of design；Step 2 is written test data to DRAM memory by dram controller, is verified；Step 3, after terminating verifying, read test data are compared, and check whether verification result passes through；If passed through, verifying is exited；Otherwise following steps are executed；Step 1, it after emulation of the emulator to dram controller, executes timing information and extracts script；From the output information of emulator, the timing warning information of DRAM clock working frequency and DRAM is extracted；Step 2, it for the timing information extracted, executes and calculates script；Judge whether actual DRAM clock working frequency meets the range of system schema permission, if there is the time sequence allowance of permission, goes to step 3 and execute update verifying script, otherwise, go to step 4 implementing result notice script.
Description
Technical field
The present invention relates to chip logic checking field, specially a kind of verification method for dram controller.
Background technique
Since DRAM working mechanism is more complicated, it is related to the configuration adjustment of numerous parameters, and DRAM work is higher
Working frequency, it is very high for timing requirements, so being an extremely complex job to the verifying of dram controller.At present
The mode taken, firstly, initialization controller, is then written test data to DRAM memory by dram controller, then,
Read test data are compared again.When due to DRAM work, it is related to numerous time sequence parameters, sequence alarm when present causes
It is currently that verifying personnel need manually to check DRAM clock working frequency and timing announcement from type information when authentication failed
Alert information, and then calculated accordingly, if there is the time sequence allowance of permission, then adjust the register of corresponding dram controller
Configuration, restarting verifying are this if needing to carry out timing optimization from the angle of design beyond the time sequence allowance allowed
There are problems that inefficient and accuracy by method manually.
Summary of the invention
Aiming at the problems existing in the prior art, the present invention provides a kind of verification method for dram controller, flexibly
Property height and reusability are strong, effectively increase the efficiency of chip development, increase the controllability of chip development process.
The present invention is to be achieved through the following technical solutions:
A kind of verification method for dram controller, includes the following steps,
Step 1 initializes dram controller according to the system schema of design；
Step 2 is written test data to DRAM memory by dram controller, is verified；
Step 3, after terminating verifying, read test data are compared, and check whether verification result passes through；If passed through,
Then exit verifying；Otherwise following steps are executed；
Step 1, it after emulation of the emulator to dram controller, executes timing information and extracts script；From emulator
Output information in, extract DRAM clock working frequency and DRAM timing warning information；
Step 2, it for the timing information extracted, executes and calculates script；Judging actual DRAM clock working frequency is
The no range for meeting system schema permission goes to step 3 if there is the time sequence allowance of permission, otherwise, goes to step 4；
Step 3, it executes and updates verifying script, according to the timing information extracted, update and alert related DRAM with timing
The timing register configuration file of controller, and the timing register configuration file based on dram controller after update re-starts
The verifying of dram controller, i.e. the timing register configuration file based on dram controller after update, repeat step 1；
Step 4, implementing result notifies script；Provide the result that DRAM timing needs to be optimized.
Preferably, the specific steps are obtain database required for verifying, base according to the system schema of design to step 1
In DRAM timing indicator specification and DRAM clock working frequency target value, the register initial value of dram controller is inputted, is completed
The initialization of dram controller.
Preferably, in step 1, emulator output information is recorded as artificial intelligence record file.
Further, in step 2, when actual DRAM clock working frequency meets the range of system schema permission,
lowerlimit<CKa/CKt<upperlimit；
Wherein, CKa is DRAM clock working frequency actual value；
CKt is DRAM clock working frequency target value；
Lowerlimit is the lower limit of system schema allowed band；
Upperlimit is the upper limit of system schema allowed band.
Further, wherein the range of lowerlimit is 0.9-0.95；The range of upperlimit is 1.05-1.10.
Preferably, in step 3, the updated value in the time sequence parameter of DRAM calculates as follows:
UR*CKa >=IR*CKt=DRAMtimingofspecification；
Wherein, CKa is DRAM clock working frequency actual value；
CKt is DRAM clock working frequency target value；
UR is the updated value that relevant register is alerted to timing；
IR is the initial value that relevant register is alerted to timing；
DRAMtimingofspecification is DRAM time sequence parameter index specification relevant to timing alarm.
Compared with prior art, the invention has the following beneficial technical effects:
The present invention extracts script by timing information, so that can quickly and accurately mention after this authentication in dram controller
Get information needed；Script is calculated by executing, accurately the timing information that dram controller generates can be carried out quick
Accurate judgement；Script is verified by updating, the time sequence parameter of dram controller quickly accurately update；Pass through result
It notifies script, the design problem of system schema is fed back；To give full play to the high flexible in programming of scripting language
With reusability, and carry out in chip development field using effectively increasing the efficiency of chip development, increase chip development mistake
The controllability of journey.
Detailed description of the invention
Fig. 1 is the flow chart of verification method of the present invention.
Fig. 2 is the flow chart of step 2 in verification method of the present invention.
Specific embodiment
Below with reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
A kind of verification method for dram controller of the present invention, is based on scripting language, carries out timing information extraction, analysis
With the corresponding timing register configuration file of generation.
Step 1 obtains database required for verifying according to the system schema of design, is based on DRAM timing indicator specification
With DRAM clock working frequency target value, the register initial value of dram controller is inputted, the initialization of dram controller is completed；
Step 2 is written test data to DRAM memory by dram controller, is verified；
Step 3, after terminating verifying, read test data are compared, and check whether verification result passes through；If passed through,
Then exit verifying；Otherwise following steps are executed；
Step 1, it after emulation of the emulator to dram controller, executes timing information and extracts script；From emulator
Output information in, extract DRAM clock working frequency and DRAM timing warning information；Wherein, emulator output information records
File is recorded for artificial intelligence.
Step 2, it for the timing information extracted, executes and calculates script；Judging actual DRAM clock working frequency is
The no range for meeting system schema permission goes to step 3 if there is the time sequence allowance of permission, otherwise, goes to step 4；Specifically sentence
The disconnected range met is as follows:
lowerlimit<CKa/CKt<upperlimit；
Wherein, CKa is DRAM clock working frequency actual value；
CKt is DRAM clock working frequency target value；
Lowerlimit is the lower limit of system schema allowed band, range 0.9-0.95；
Upperlimit is the upper limit of system schema allowed band, range 1.05-1.10.
Step 3, it executes and updates verifying script, according to the timing information extracted, update and alert related DRAM with timing
The timing register configuration file of controller, and the timing register configuration file based on dram controller after update re-starts
The verifying of dram controller, i.e. the timing register configuration file based on dram controller after update, repeat step 1.
Specifically, since the time sequence parameter index of DRAM is based on lower limit value, so it is necessary to meet following condition:
UR*CKa >=IR*CKt=DRAMtimingofspecification；
Wherein, UR is the updated value that relevant register is alerted to timing；
IR is the initial value that relevant register is alerted to timing；
DRAMtimingofspecification is DRAM time sequence parameter index specification relevant to timing alarm.
Step 4, implementing result notifies script；Provide the instruction that DRAM timing needs to be optimized.
Designer can need to improve result instruction according to what is obtained, optimize to DRAM timing further progress, accorded with
The optimization design of system scenario requirements is closed, then is provided as designer and to carry out testing again after database required for new verifying
Card.
Claims (5)
1. a kind of verification method for dram controller, which is characterized in that include the following steps,
Step 1 initializes dram controller according to the system schema of design；
Step 2 is written test data to DRAM memory by dram controller, is verified；
Step 3, after terminating verifying, read test data are compared, and check whether verification result passes through；If passed through, move back
It verifies out；Otherwise following steps are executed；
Step 1, it after emulation of the emulator to dram controller, executes timing information and extracts script；From the defeated of emulator
Out in information, the timing warning information of DRAM clock working frequency and DRAM is extracted；
Step 2, it for the timing information extracted, executes and calculates script；Judge whether actual DRAM clock working frequency is full
The range that pedal system scheme allows is gone to if there is the time sequence allowance of permission
Step 3, otherwise, step 4 is gone to；
Step 3, it executes and updates verifying script, according to the timing information extracted, update and timing alerts related DRAM and controls
The timing register configuration file of device, and the timing register configuration file based on dram controller after update re-starts DRAM
The verifying of controller, i.e. the timing register configuration file based on dram controller after update, repeat step 1；
Wherein, the updated value in the time sequence parameter of DRAM calculates as follows:
UR*CKa >=IR*CKt=DRAMtimingofspecification；
Wherein, CKa is DRAM clock working frequency actual value；
CKt is DRAM clock working frequency target value；
UR is the updated value that relevant register is alerted to timing；
IR is the initial value that relevant register is alerted to timing；
DRAMtimingofspecification is DRAM time sequence parameter index specification relevant to timing alarm；
Step 4, implementing result notifies script；Provide the result that DRAM timing needs to be optimized.
2. a kind of verification method for dram controller according to claim 1, which is characterized in that step 1 specifically walks
It suddenly is according to the system schema of design, to obtain database required for verifying, be based on DRAM timing indicator specification and DRAM clock
Working frequency target value inputs the register initial value of dram controller, completes the initialization of dram controller.
3. a kind of verification method for dram controller according to claim 1, which is characterized in that in step 1, emulation
Device output information is recorded as artificial intelligence record file.
4. a kind of verification method for dram controller according to claim 1, which is characterized in that practical in step 2
DRAM clock working frequency meet system schema permission range when,
lowerlimit<CKa/CKt<upperlimit；
Wherein, CKa is DRAM clock working frequency actual value；
CKt is DRAM clock working frequency target value；
Lowerlimit is the lower limit of system schema allowed band；
Upperlimit is the upper limit of system schema allowed band.
5. a kind of verification method for dram controller according to claim 4, which is characterized in that wherein,
The range of lowerlimit is 0.9-0.95；The range of upperlimit is 1.05-1.10.
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| CN109324938A (en) * | 2018-10-08 | 2019-02-12 | 郑州云海信息技术有限公司 | A method for batch detection of RAM information |
| CN111177997B (en) * | 2019-12-27 | 2022-07-12 | 广东高云半导体科技股份有限公司 | Method, device and system for controlling layout and wiring based on clock frequency |
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| US20030154428A1 (en) * | 2002-02-11 | 2003-08-14 | Intel Corporation | Method of testing computer system components |
| CN102385547A (en) * | 2010-08-31 | 2012-03-21 | 安凯(广州)微电子技术有限公司 | Method and system for verifying timing sequence calibration function of dynamic random access memory (DRAM) controller |
| US20120198292A1 (en) * | 2010-04-19 | 2012-08-02 | Advantest Corporation | Test apparatus and test method |
| CN103049363B (en) * | 2013-02-01 | 2015-02-04 | 山东华芯半导体有限公司 | Verification method of NAND (neither agree not disagree) Flash controller |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030154428A1 (en) * | 2002-02-11 | 2003-08-14 | Intel Corporation | Method of testing computer system components |
| US20120198292A1 (en) * | 2010-04-19 | 2012-08-02 | Advantest Corporation | Test apparatus and test method |
| CN102385547A (en) * | 2010-08-31 | 2012-03-21 | 安凯(广州)微电子技术有限公司 | Method and system for verifying timing sequence calibration function of dynamic random access memory (DRAM) controller |
| CN103049363B (en) * | 2013-02-01 | 2015-02-04 | 山东华芯半导体有限公司 | Verification method of NAND (neither agree not disagree) Flash controller |
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