CN106409677B - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method for forming the same, wherein the method for forming the semiconductor device comprises: providing a substrate, the substrate has an interlayer dielectric layer on the surface, and the interlayer dielectric layer has grooves in the interlayer dielectric layer, and the grooves expose the substrate forming a gate dielectric layer covering the bottom and sidewalls of the groove; forming a first barrier layer covering the gate dielectric layer; amorphizing the first barrier layer so that the first barrier layer is transformed into a second barrier layer A barrier layer; a metal layer covering the second barrier layer is formed, and the surface of the metal layer is flush with the surface of the interlayer dielectric layer. The semiconductor device and method of forming the same improve the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a method for forming the same.

Background technique

MOS transistors are one of the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the substrate, a source region located in the semiconductor substrate on one side of the gate structure, and a drain region located in the semiconductor substrate on the other side of the gate structure. MOS transistors generate switching signals by applying a voltage across the gate structure, regulating the current through the channel at the bottom of the gate structure.

As the integration of MOS transistors becomes higher and higher, the voltage and current required for MOS transistors to operate continues to decrease, and the speed of transistor switching is accelerated, and the requirements for semiconductor technology are greatly increased. Therefore, the industry finds a high dielectric constant material (High-K Material) that replaces SiO ₂ as a gate dielectric layer to better isolate the gate structure from other parts of the MOS transistor and reduce leakage. At the same time, in order to be compatible with high-K (K greater than 3.9) dielectric constant materials, metal materials are used to replace the original polysilicon as the gate electrode layer. The leakage of the MOS transistor with the metal gate electrode of the high-K gate dielectric layer is further reduced.

However, as the feature size is further reduced, the performance of the MOS transistors formed in the prior art is poor.

SUMMARY OF THE INVENTION

The problem solved by the present invention is to provide a semiconductor device and a method for forming the same to improve the performance of the semiconductor device.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, the surface of the substrate has an interlayer dielectric layer, and the interlayer dielectric layer has grooves in the interlayer dielectric layer, and the grooves expose the substrate forming a gate dielectric layer covering the bottom and sidewalls of the groove; forming a first barrier layer covering the gate dielectric layer; amorphizing the first barrier layer so that the first barrier layer is transformed into a second barrier layer A barrier layer; a metal layer covering the second barrier layer is formed, and the surface of the metal layer is flush with the surface of the interlayer dielectric layer.

Optionally, the method further includes: before forming the gate dielectric layer, forming an interface layer, the interface layer covering the bottom and sidewalls of the groove.

Optionally, the method further includes: before forming the metal layer, forming a work function layer covering the second barrier layer.

Optionally, when the semiconductor device is an N-type MOS transistor, the material of the work function layer is TiAl; when the semiconductor device is a P-type MOS transistor, the material of the work function layer is TaN.

Optionally, the base includes a substrate and a fin on a surface of the substrate; the groove exposes a top surface and sidewalls of the fin.

Optionally, the base is a substrate, and the groove exposes a surface of the substrate.

Optionally, the material of the gate dielectric layer is a high-K dielectric material.

Optionally, the material of the first barrier layer is TiN or TaN.

Optionally, the amorphization treatment method is as follows: using a first ion implantation process to dope the first ions in the first barrier layer; performing a first annealing treatment on the first barrier layer doped with the first ions, The first barrier layer is transformed into a second barrier layer.

Optionally, the parameters of the first ion implantation process are: the implanted ions are silicon ions, the implantation energy is 0.5KeV～5KeV, the implantation dose is 1E 15atom/cm ² ～ 5E 16atom/cm ² , and the implantation angle is 7°～ 20 degrees.

Optionally, the first annealing treatment is spike annealing, the gas used is N ₂ or Ar, and the annealing temperature is 950 degrees Celsius to 1050 degrees Celsius.

Optionally, when the first barrier layer is TiN and the first ion is Si ion, the second barrier layer formed is TiSiN.

Optionally, the amorphization treatment method is: forming a silicon layer covering the first barrier layer; performing a second annealing treatment on the silicon layer and the first barrier layer, so that silicon atoms in the silicon layer enter the first barrier layer In the process, the second barrier layer is formed; after the second barrier layer is formed, the silicon layer is removed.

Optionally, the process for forming the silicon layer is a low pressure chemical vapor deposition process, and the specific process parameters are: the gas used is SiH ₄ , the flow rate of SiH ₄ is 10 sccm to 60 sccm, the temperature is 350 degrees Celsius to 500 degrees Celsius, and the deposition chamber is The chamber pressure is 0.4torr to 2torr.

Optionally, the thickness of the silicon layer is 40 angstroms to 100 angstroms.

Optionally, the second annealing treatment is spike annealing, the gas used is N ₂ or Ar, and the annealing temperature is 800 degrees Celsius to 1000 degrees Celsius.

Optionally, when the first barrier layer is TiN, the second barrier layer is TiSiN.

Optionally, the thickness of the second barrier layer is 10 angstroms to 30 angstroms.

Optionally, the metal layer is W, Al, Ti, Cu, Mo or Pt.

The present invention also provides a semiconductor device formed by any one of the above methods, comprising: a substrate; a surface of the substrate has an interlayer dielectric layer, and a groove is formed in the interlayer dielectric layer, and the groove exposes the surface of the substrate a gate dielectric layer covering the bottom and sidewalls of the groove; a second barrier layer covering the gate dielectric layer, the second barrier layer having an amorphous structure; a metal layer covering the second barrier layer, the metal layer The surface of the layer is flush with the surface of the interlayer dielectric layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the method for forming a semiconductor device provided by the present invention, since the first barrier layer is amorphized, the first barrier layer is transformed into a second barrier layer, and the second barrier layer has an amorphous structure, so that the first barrier layer is transformed into a second barrier layer. The blocking effect of the second barrier layer is greater than that of the first barrier layer, and the second barrier layer can effectively prevent the metal atoms in the metal layer from entering the gate dielectric layer; in addition, in the process of forming the metal layer, the second barrier layer can The intermediate products generated by the precursor are effectively blocked from entering the gate dielectric layer.

Further, before forming the gate dielectric layer, an interface layer covering the bottom and sidewalls of the groove is formed. The interface layer acts as a transition layer between the substrate and the gate dielectric layer, so as to avoid the phenomenon that the gate dielectric layer is directly bonded to the substrate and is not firmly bonded. At the same time, the second barrier layer can effectively block metal atoms in the metal layer from entering the interface layer, and in the process of forming the metal layer, effectively prevent intermediate products generated by the precursor from entering the interface layer.

Further, a work function layer is formed between the second barrier layer and the metal layer. The work function layer can adjust the threshold voltage of the semiconductor device. Meanwhile, the second blocking layer can effectively block the metal atoms in the work function layer from entering the gate dielectric layer.

Further, the amorphization treatment method is as follows: forming a silicon layer covering the first barrier layer; performing a second annealing treatment on the silicon layer and the first barrier layer, so that silicon atoms in the silicon layer enter the first barrier layer , forming a second barrier layer; after forming the second barrier layer, remove the silicon layer. The amorphization treatment method can transform the first barrier layer into the second barrier layer; in addition, during the second annealing treatment, the silicon layer can adsorb oxygen atoms in the interface layer, so that the interface layer, etc. The thickness of the effective oxide is reduced, thereby improving the performance of the semiconductor device.

In the semiconductor device provided by the present invention, since the second barrier layer has an amorphous structure, the barrier effect of the second barrier layer is strong, and the second barrier layer can effectively prevent the metal atoms in the metal layer from entering the gate dielectric. In addition, the second barrier layer can effectively block the intermediate products generated in the process of forming the metal layer from entering the gate dielectric layer.

Description of drawings

1 to 3 are schematic diagrams illustrating a process of forming a semiconductor device according to an embodiment of the present invention;

4 to 13 are schematic diagrams illustrating a process of forming a semiconductor device in another embodiment of the present invention;

14 to 18 are schematic diagrams illustrating a process of forming a semiconductor device according to still another embodiment of the present invention.

Detailed ways

As the feature size is further reduced, the performance of the semiconductor devices formed in the prior art is poor.

FIG. 1 to FIG. 3 are schematic structural diagrams of a formation process of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1 , a base is provided, the base includes a substrate 100 and fins 120 located on the surface of the substrate 100 ; an interlayer dielectric layer 130 is formed on the surface of the base, and grooves are formed in the interlayer dielectric layer 130 131 , the grooves 131 expose the top surface and sidewalls of the fins 120 .

Referring to FIG. 2 , a gate dielectric layer 140 covering the bottom and sidewalls of the groove 131 (refer to FIG. 1 ) is formed; a barrier layer 141 covering the gate dielectric layer 140 is formed; a metal layer 142 covering the barrier layer 141 is formed , the entire surface of the metal layer 142 is higher than the surface of the interlayer dielectric layer 130 .

The material of the barrier layer 141 is TiN, and the material of the metal layer 142 is W.

Referring to FIG. 3 , using the interlayer dielectric layer 130 as a stop layer, the metal layer 142 , the barrier layer 141 and the gate dielectric layer 140 are planarized so that the metal layer 142 , the barrier layer 141 and the gate dielectric layer 140 are flush with the interlayer dielectric layer 130 .

The study found that the reasons for the poor performance of the semiconductor device formed by the above method are:

In the process of forming the metal layer, a fluorine-containing precursor, such as WF ₆ is used to form the metal layer, and the precursor produces a fluorine-containing intermediate product, and the fluorine atoms in the intermediate product are easily diffused into the gate dielectric layer. . In addition, since the material of the barrier layer is TiN, TiN has a polycrystalline structure, and the barrier effect of the barrier layer is weak, so that the fluorine atoms of the intermediate product are easily diffused into the gate dielectric layer through the grain boundaries in the barrier layer , so that defects are formed in the gate dielectric layer, so that the threshold voltage of the semiconductor device is unstable.

On this basis, another embodiment of the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, a surface of the substrate has an interlayer dielectric layer, and a groove is formed in the interlayer dielectric layer, and the concave The groove exposes the surface of the substrate; a gate dielectric layer covering the bottom and sidewalls of the groove is formed; a first barrier layer covering the gate dielectric layer is formed; the first barrier layer is amorphized to make the first barrier layer transforming into a second barrier layer; forming a metal layer covering the second barrier layer, the surface of the metal layer being flush with the surface of the interlayer dielectric layer.

Compared with the previous embodiment, since the first barrier layer is amorphized, the first barrier layer is transformed into a second barrier layer, and the second barrier layer has an amorphous structure, so that the second barrier layer has an amorphous structure. The blocking effect is greater than that of the first blocking layer, and the second blocking layer can effectively block the metal atoms in the metal layer from entering the gate dielectric layer; in addition, in the process of forming the metal layer, the second blocking layer can effectively block the precursor. The resulting intermediate product enters the gate dielectric layer.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

4 to 13 are schematic diagrams illustrating a process of forming a semiconductor device according to another embodiment of the present invention. In this embodiment, the semiconductor device is a fin field effect transistor as an example for description.

4 and 5, FIG. 5 is a cross-sectional view taken along the extension direction of the fins (A-A1 axis) in FIG. 4, providing a base including a substrate 200 and fins located on the surface of the substrate 200 220 ; the surface of the fin portion 220 has a dummy gate structure 230 across the fin portion 220 , and the dummy gate structure 230 covers part of the top surface and sidewalls of the fin portion 220 .

The substrate 200 provides a process platform for the subsequent formation of semiconductor devices.

The substrate 200 can be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the substrate 200 can also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide; the substrate 200 can be a bulk material, It can also be a composite structure, such as silicon-on-insulator; in this embodiment, the material of the substrate 200 is silicon.

The steps of forming the fins 220 are: forming a patterned mask layer on the surface of the substrate 200 , the patterned mask layer defines the position of the fins 220 ; using the patterned mask layer as a mask to etch A partial thickness of the substrate 200 is etched to form the fins 220 .

Since the fins 220 are formed by etching the substrate 200 , the material of the fins 220 is the same as the material of the substrate 200 . In other embodiments, the material of the fins 220 may be different from the material of the substrate 200 .

In this embodiment, three fins 220 are used as an example, which does not represent the number of fins 220 in an actual process. In the actual process, the specific number of the fins 220 can be selected as required.

The surface of the substrate 200 also has an isolation structure 210 , the surface of the isolation structure 210 is lower than the top surface of the fins 220 , and the isolation structures 210 are used to electrically isolate the adjacent fins 220 . The material of the isolation structure 210 includes silicon oxide or silicon oxynitride. In this embodiment, the material of the isolation structure 210 is silicon oxide.

The dummy gate structure 230 includes a dummy gate dielectric layer 231 spanning the fins 220 and a dummy gate electrode layer 232 covering the dummy gate dielectric layer 231 . The dummy gate dielectric layer 231 is located on the surface of the isolation structure 210 and covers part of the top surface and sidewalls of the fins 220 . In this embodiment, the material of the dummy gate dielectric layer 231 is silicon oxide, and the material of the dummy gate electrode layer 232 is polysilicon.

In this embodiment, one dummy gate structure 230 is used as an example, which does not represent the number of dummy gate structures 230 in an actual process. In an actual process, the number of the dummy gate structures 230 can be selected as required.

Referring to FIG. 6, FIG. 6 is a schematic diagram formed on the basis of FIG. 5, forming sidewall spacers 240 covering the sidewalls on both sides of the dummy gate structure 230; forming a source region (not shown) and a drain region (not shown), so The source region is located in the fin portion 220 on one side of the spacer 240 and the dummy gate structure 230, and the drain region is located in the fin portion 220 on the other side of the sidewall spacer 240 and the dummy gate structure 230; the source region and the drain region are formed Then, an interlayer dielectric layer 250 is formed on the surface of the substrate, the interlayer dielectric layer 250 covers the sidewalls of the spacers 240 , and the surface of the interlayer dielectric layer 250 is flush with the surface of the dummy gate structure 230 .

The material of the interlayer dielectric layer 250 is silicon oxide, silicon oxynitride or silicon oxycarbide.

The steps of forming the interlayer dielectric layer 250 are: forming an interlayer dielectric material layer covering the fins 220, the dummy gate structure 230, the isolation structure 210 and the substrate 200, and the entire surface of the interlayer dielectric material layer is higher than The top surface of the dummy gate structure 230 ; the interlayer dielectric material layer is planarized until the top surface of the dummy gate structure 230 is exposed to form the interlayer dielectric layer 250 .

Referring to FIG. 7 , the dummy gate structures 230 (refer to FIG. 6 ) are removed to form recesses 251 .

The dummy gate structure 230 is etched and removed by a dry etching process or a wet etching process.

After the dummy gate structure 230 is removed, the top surface and sidewalls of the fins 220 are exposed to form the grooves 251 .

Referring to FIG. 8 , a gate dielectric layer 260 covering the bottom and sidewalls of the groove 251 (refer to FIG. 7 ) is formed.

The function of the gate dielectric layer 260 is to isolate the substrate from other material layers subsequently formed on the surface of the gate dielectric layer.

The material of the gate dielectric layer 260 is a high-K (K greater than 3.9) dielectric material, such as HfO ₂ , HfSiO, HfSiON, Al ₂ O ₃ or ZrO ₂ . In the embodiment of the present invention, the material of the gate dielectric layer 260 is HfO ₂ .

The process of forming the gate dielectric layer 260 is a deposition process, such as an atomic layer deposition process or a plasma chemical vapor deposition process. In this embodiment, the gate dielectric layer 260 is formed by a plasma chemical vapor deposition process.

In this embodiment, an interface layer (not shown) may also be formed at the bottom of the gate dielectric layer 260 as a transition layer between the substrate and the gate dielectric layer 260 to avoid the problem that the gate dielectric layer 260 is not firmly bonded directly to the substrate.

The material of the interface layer is SiO ₂ or SiON. In this embodiment, the material of the interface layer is silicon oxide.

The process of forming the interface layer is a deposition process, such as atomic layer deposition process, chemical vapor deposition process, thermal oxidation process and nitridation process. In this embodiment, the interface layer is formed by a thermal oxidation process.

Continuing to refer to FIG. 8 , a first barrier layer 261 covering the gate dielectric layer 260 is formed.

The functions of the first barrier layer 261 are: to prevent the metal atoms in the subsequently formed metal layer from diffusing into the gate dielectric layer 260 and the interface layer; to prevent intermediate products generated in the process of forming the metal layer from entering the gate dielectric layer 260 in the interface layer

The material of the first barrier layer 261 is TiN or TaN. In this embodiment, the material of the first barrier layer 261 is TiN.

The thickness of the first barrier layer 261 is 10 angstroms to 30 angstroms.

The process of forming the first barrier layer 261 is a deposition process, such as an atomic layer deposition process or a plasma chemical vapor deposition process. In this embodiment, the first barrier layer 261 is formed by a plasma chemical vapor deposition process.

Since the first barrier layer 261 has a polycrystalline structure, in the subsequent process of forming the metal layer, an intermediate product will be generated, and the intermediate product will easily enter the gate dielectric layer 260. For example, when the material of the metal layer is W, the intermediate product The product contains fluorine atoms, which are easily diffused into the gate dielectric layer 260 through the grain boundaries in the first barrier layer 261 , increasing defects in the gate dielectric layer 260 and making the threshold voltage of the semiconductor device unstable. That is, the blocking effect of the first barrier layer 261 on the fluorine atoms in the intermediate product is weak, so in this embodiment, a method of amorphizing the first barrier layer 261 is adopted, so that the first barrier layer 261 is transformed into a The second barrier layer of the amorphous structure, the first barrier layer 261 has a strong barrier effect, which can prevent intermediate products generated in the process of forming the metal layer from entering the gate dielectric layer 260 .

In one embodiment, the amorphization treatment method is as follows: doping the first barrier layer 261 with first ions by using a first ion implantation process; An annealing process converts the first barrier layer 261 into the second barrier layer.

The principle of transforming the first barrier layer 261 into the second barrier layer is as follows: the first ion implantation is used to make the first ions enter the grain boundary gap of the first barrier layer 261 , and the first ions strike the atoms in the first barrier layer 261 and leave the crystal lattice The position enters the lattice gap while leaving vacancies; during the first annealing process, the first ions occupy the vacancies and combine with atoms in the first barrier layer 261 to form bonds, thereby changing the composition of the first barrier layer 261 and crystal orientation to form a second barrier layer, the second barrier layer has an amorphous structure.

In a specific embodiment, the parameters of the first ion implantation process are: the implanted ions are silicon ions, the implantation energy is 0.5KeV～5KeV, the implantation dose is 1E 15atom/cm ² ～5E 16atom/cm ² , and the implantation angle is 7 degrees to 20 degrees. The implantation angle is an angle formed with the normal line of the substrate 200 .

The first annealing treatment is spike annealing, the gas used is N ₂ or Ar, and the annealing temperature is 950 degrees Celsius to 1050 degrees Celsius.

It should be noted that the first ions are not limited to silicon ions, and in other embodiments, other ions may be used to convert the first barrier layer 261 into the second barrier layer of amorphous structure. Preferably, the ion radius of the first ions is larger than the size of the lattice gap of the first barrier layer 261, so that after the first ions are implanted into the first barrier layer 261, the lattice distortion of the first barrier layer 261 is enhanced, which is conducive to the formation of amorphous the second barrier layer.

In this embodiment, the material of the first barrier layer 261 is TiN, the implanted ions used in the first ion implantation are silicon ions, and the material of the formed second barrier layer is TiSiN.

In another embodiment, the amorphization treatment method is: forming a silicon layer covering the first barrier layer 261; performing a second annealing treatment on the silicon layer and the first barrier layer 261, so that the silicon atoms in the silicon layer are Entering into the first barrier layer 261, a second barrier layer is formed; after the second barrier layer is formed, the silicon layer is removed.

Referring to FIG. 9, a silicon layer 262 covering the first barrier layer 261 is formed.

The process for forming the silicon layer 262 is a deposition process, such as an atomic layer deposition process, a plasma chemical vapor deposition process or a low pressure chemical vapor deposition process.

In this embodiment, the silicon layer 262 is formed by a low pressure chemical vapor deposition process. The specific process parameters are: the gas used is SiH ₄ , the flow rate of SiH ₄ is 10 sccm-60 sccm, the temperature is 350-500 degrees Celsius, the deposition chamber is The chamber pressure is 0.4torr to 2torr.

The thickness of the silicon layer 262 is 40 angstroms to 100 angstroms.

Referring to FIG. 10 , a second annealing process is performed on the silicon layer 262 and the first barrier layer 261 (refer to FIG. 9 ), so that silicon atoms in the silicon layer 262 enter the first barrier layer 261 to form a second barrier layer 263 .

The principle of converting the first barrier layer 261 into the second barrier layer 263 is as follows: during the second annealing process, the silicon atoms in the silicon layer 262 enter the first barrier layer 261, and the silicon atoms and the first barrier layer The atoms in 261 recombine to form bonds, thereby changing the composition and crystal orientation of the first barrier layer 261 to form a second barrier layer 263, and the second barrier layer 263 has an amorphous structure.

The second annealing treatment is peak annealing, the gas used is N ₂ or Ar, and the annealing temperature is 800 degrees Celsius to 1000 degrees Celsius.

In this embodiment, the material of the first barrier layer 261 is TiN, and the material of the formed second barrier layer 263 is TiSiN.

The first barrier layer 261 is transformed into the second barrier layer 263 after the above-mentioned amorphization process.

The functions of the second barrier layer 263 are: to prevent the metal atoms in the subsequently formed metal layer from diffusing into the gate dielectric layer 260 and the interface layer; to prevent intermediate products generated in the process of forming the metal layer from entering the gate dielectric layer 260 and the interface layer.

Since the second barrier layer 263 has an amorphous structure, the barrier effect of the second barrier layer 263 is stronger than that of the first barrier layer 261 , which can effectively prevent the intermediate products generated during the formation of the metal layer from entering the gate dielectric. layer 260 and the interface layer.

The thickness of the second barrier layer 263 is 10 angstroms˜30 angstroms.

In this embodiment, the entire thickness of the first barrier layer 261 is amorphized. In other embodiments, a partial thickness of the first barrier layer 261 may be amorphized, that is, only the upper portion of the first barrier layer 261 may be amorphized.

Referring to FIG. 11, the silicon layer 262 (refer to FIG. 10) is removed.

The process of removing the silicon layer 262 is a wet etching process or a dry etching process. In this embodiment, the silicon layer 262 is removed by a wet etching process.

In a specific embodiment, the parameters of the wet etching process used to remove the silicon layer 262 are: the etching solution is a tetramethyl ammonium hydroxide solution, and the mass percentage concentration of tetramethyl ammonium hydroxide is 10% to 25% %, the etching temperature is 40 degrees Celsius to 90 degrees Celsius.

It should be noted that when the semiconductor device has the interface layer, and the amorphization treatment method adopted is: forming the silicon layer 262 covering the first barrier layer 261; The second annealing process causes the silicon atoms in the silicon layer 262 to enter the first barrier layer 261 to form the second barrier layer 263; after the second barrier layer 263 is formed, the silicon layer 262 is removed, and during the second annealing process , the silicon layer 262 can adsorb oxygen atoms in the interface layer, so that the equivalent oxide thickness of the interface layer is reduced, thereby improving the performance of the semiconductor device.

Referring to FIG. 12 , a metal layer 264 covering the second barrier layer 263 is formed, and the entire surface of the metal layer 264 is higher than the surface of the interlayer dielectric layer 250 .

The metal layer 264 serves as the metal gate of the semiconductor device.

The material of the metal layer 264 is W, Al, Ti, Cu, Mo or Pt. In this embodiment, the material of the metal layer 264 is W.

The process of forming the metal layer 264 is a chemical vapor deposition process, a physical vapor deposition process or an electroplating process. In this embodiment, the metal layer 264 is formed by a chemical vapor deposition process.

In a specific embodiment, the process parameters for forming the metal layer 264 are: the gas used is WF ₆ and SiH ₄ , the flow rate of WF ₆ is 300 sccm-800 sccm, the flow rate of SiH ₄ is 30 sccm-100 sccm, and the temperature is 350 ℃～ At 500 degrees Celsius, the deposition chamber pressure is 40torr to 130torr.

In the process of forming the metal layer 264 , the precursor for forming the metal layer 264 is a fluorine-containing precursor, and the precursor will generate a fluorine-containing intermediate product, and the fluorine atoms in the intermediate product can easily diffuse into the gate dielectric layer 260 . However, since the first barrier layer 261 is amorphized, the first barrier layer 261 is transformed into the second barrier layer 263 having an amorphous structure, so that the barrier effect of the second barrier layer 263 is greater than that of the second barrier layer 263. With the blocking effect of the first barrier layer 261, during the formation of the metal layer 264, the second barrier layer 263 can effectively block the intermediate products generated by the precursor from entering the gate dielectric layer 260 and the interface layer, so as to stabilize the threshold voltage of the semiconductor device.

In this embodiment, before the metal layer 264 is formed, a work function layer (not shown) covering the second barrier layer 263 may also be formed, and after the work function layer is formed, the metal layer 264 covering the work function layer is formed. The work function layer can adjust the threshold voltage of the semiconductor device.

When the semiconductor device is a P-type fin field effect transistor, the material of the work function layer is TaN; when the semiconductor device is an N-type fin field effect transistor, the material of the work function layer is TiAl.

The process of forming the work function layer is a deposition process, such as a chemical vapor deposition process or an atomic layer deposition process.

In this embodiment, the atomic layer deposition process is used to form the work function layer. When the material of the work function layer is TaN, the precursor reactants are penta(dimethylamino) tantalum (PDMAT) and ammonia (NH ₃ ). ); when the material of the work function layer is TiAl, the precursor reactants are titanium chloride (TiCl4) and trimethyl aluminum (Tri methyl Al, MTA).

When the semiconductor device has the work function layer, the second barrier layer 263 also has the function of blocking the metal atoms in the work function layer from entering the gate dielectric layer 260 and the interface layer.

Especially, when the semiconductor device is an N-type fin field effect transistor and the material of the work function layer is TiAl, the aluminum atoms in TiAl are easily diffused into other media, and since the second barrier layer 263 has an amorphous structure, It can effectively block aluminum atoms from entering the gate dielectric layer 260 and the interface layer. The dielectric constant of the gate dielectric layer 260 is stabilized, so that the reliability of the interface layer is enhanced.

Referring to FIG. 13 , the gate dielectric layer 260 , the second barrier layer 263 and the metal layer 264 above the surface of the interlayer dielectric layer 250 are removed.

The process of removing the gate dielectric layer 260 , the second barrier layer 263 and the metal layer 264 higher than the surface of the interlayer dielectric layer 250 is a chemical mechanical polishing (CMP) process.

When the semiconductor device further has an interface layer and a work function layer, the interface layer and the work function layer above the surface of the interlayer dielectric layer 250 also need to be removed.

In this embodiment, the gate dielectric layer 260 , the second barrier layer 263 and the metal layer 264 above the surface of the interlayer dielectric layer 250 are removed in the same step, which effectively saves process steps. In other embodiments of the present invention, the gate dielectric layer 260 , the second barrier layer 263 and the metal layer 264 which are higher than the surface of the interlayer dielectric layer 250 may also be removed in multiple steps. Part of the surface of the dielectric layer 230 is removed.

14 to 18 illustrate a method for forming a semiconductor device provided by yet another embodiment. In this embodiment, the semiconductor device is an example of a planar MOS transistor for description.

Referring to FIG. 14 , a base is provided, which is a substrate 300 , and a surface of the base has an interlayer dielectric layer 350 , and the interlayer dielectric layer 350 has grooves 351 throughout its thickness.

In this embodiment, the base surface also has sidewalls 340 .

It should be noted that, before the interlayer dielectric layer 350 is formed, a dummy gate structure is formed on the surface of the substrate 300, and the sidewall spacers 340 cover the sidewalls of the dummy gate structure; then a source region (not shown) and a drain are formed region (not shown), the source region is located in the substrate 300 on one side of the dummy gate structure and the spacer 340, and the drain region is located in the substrate 300 on the other side of the dummy gate structure and the spacer 340; After the source region and the drain region are formed, an interlayer dielectric layer 350 is formed, the interlayer dielectric layer 350 covers the sidewalls of the sidewall spacers 340 , and the surface of the interlayer dielectric layer 350 is flush with the surface of the dummy gate structure; forming an interlayer After the dielectric layer 350 , the dummy gate structure is removed to form the groove 351 .

Referring to FIG. 15 , a gate dielectric layer 360 covering the bottom and sidewalls of the groove 351 (refer to FIG. 14 ) is formed; a first barrier layer 361 covering the gate dielectric layer 360 is formed.

Referring to FIG. 16 , an amorphization process is performed on the first barrier layer 361 (refer to FIG. 15 ), so that the first barrier layer 361 is transformed into the second barrier layer 363 .

Referring to FIG. 17, a metal layer 364 covering the second barrier layer 363 is formed.

The entire surface of the metal layer 364 is higher than the surface of the interlayer dielectric layer 350 .

Referring to FIG. 18 , the gate dielectric layer 360 , the second barrier layer 363 and the metal layer 364 above the surface of the interlayer dielectric layer 350 are removed.

The method for forming the substrate 300 , the interlayer dielectric layer 350 , the groove 351 , the gate dielectric layer 360 , the first barrier layer 361 , the second barrier layer 363 , and the metal layer 364 refers to the foregoing embodiments. The method for removing the gate dielectric layer 360 , the second barrier layer 363 and the metal layer 364 higher than the surface of the interlayer dielectric layer 350 refers to the foregoing embodiments and will not be described in detail again.

In this embodiment, an interface layer can also be formed at the bottom of the gate dielectric layer 360 , and the interface layer covers the sidewalls and the bottom of the groove 351 ; in this embodiment, an interface layer can also be formed between the second barrier layer 363 and the metal layer 364 . Form a success function layer.

The method for forming the interface layer and the work function refers to the foregoing embodiments, and will not be described in detail again.

Still another embodiment of the present invention provides a semiconductor device, comprising: a substrate, the surface of the substrate has an interlayer dielectric layer, and the interlayer dielectric layer has grooves in the interlayer dielectric layer, the grooves expose the surface of the substrate; A gate dielectric layer on the bottom and sidewalls of the groove; a second barrier layer covering the gate dielectric layer, the second barrier layer having an amorphous structure; a metal layer covering the second barrier layer, the surface of the metal layer being The surface of the interlayer dielectric layer is flush.

When the semiconductor device is a fin field effect transistor, referring to FIGS. 7 and 13 , the base includes a substrate 200 and a fin 220 located on the surface of the substrate 200; the surface of the base has an interlayer dielectric layer 250, and all The interlayer dielectric layer 250 has grooves 251, the grooves 251 expose the top surface and sidewalls of the fins 220; the gate dielectric layer 260 covers the bottom and sidewalls of the grooves 251; covers the gate dielectric The second barrier layer 263 of the layer 260, the second barrier layer 263 has an amorphous structure; the metal layer 264 covering the second barrier layer 263, the surface of the metal layer 264 is flush with the surface of the interlayer dielectric layer 250 .

The method for forming the substrate 200 , the fins 220 , the interlayer dielectric layer 250 , the grooves 251 , the gate dielectric layer 260 , the second barrier layer 263 and the metal layer 264 refers to the foregoing embodiments and will not be described in detail.

When the semiconductor device is a planar MOS transistor, referring to FIG. 14 and FIG. 18 , the base is a substrate 300 , the surface of the substrate 300 has an interlayer dielectric layer 350 , and the interlayer dielectric layer 350 has recesses in it. A groove 351, the groove 351 exposes the surface of the substrate 300; a gate dielectric layer 360 covering the bottom and sidewalls of the groove 351; a second barrier layer 363 covering the gate dielectric layer 360, the second blocking layer The layer 363 has an amorphous structure; the metal layer 364 covers the second barrier layer 363 , and the surface of the metal layer 364 is flush with the surface of the interlayer dielectric layer 350 .

The method for forming the substrate 300 , the interlayer dielectric layer 350 , the groove 351 , the gate dielectric layer 360 , the second barrier layer 363 and the metal layer 364 refers to the foregoing embodiments and will not be described in detail again.

The semiconductor device may further include: an interface layer (not shown) located at the bottom of the gate dielectric layer, the interface layer covering the sidewalls and the bottom of the groove and the interlayer dielectric layer; located between the second barrier layer and the metal layer The work function layer (not shown).

The method for forming the interface layer and the work function layer refers to the foregoing embodiments and will not be described in detail again.

Because the second barrier layer has an amorphous structure, the barrier effect of the second barrier layer is strong, and the second barrier layer can effectively prevent the metal atoms in the metal layer from entering the gate dielectric layer; in addition, the second barrier layer It can effectively block the intermediate products generated in the process of forming the metal layer from entering the gate dielectric layer.

To sum up, the technical solution of the present invention has the following advantages:

In the method for forming a semiconductor device provided by the present invention, since the first barrier layer is amorphized, the first barrier layer is transformed into a second barrier layer, and the second barrier layer has an amorphous structure, so that the first barrier layer is transformed into a second barrier layer. The blocking effect of the second barrier layer is greater than that of the first barrier layer, and the second barrier layer can effectively prevent the metal atoms in the metal layer from entering the gate dielectric layer; in addition, in the process of forming the metal layer, the second barrier layer can effectively The intermediate product generated by the blocking precursor enters the gate dielectric layer.

Further, before forming the gate dielectric layer, an interface layer covering the bottom and sidewalls of the groove is formed. The interface layer acts as a transition layer between the substrate and the gate dielectric layer, so as to avoid the phenomenon that the gate dielectric layer is directly bonded to the substrate and is not firmly bonded. At the same time, the second barrier layer can effectively block the metal atoms in the metal layer from entering the interface layer, and in the process of forming the metal layer, effectively prevent intermediate products generated by the precursor from entering the interface layer.

Further, a work function layer is formed between the second barrier layer and the metal layer. The work function layer can adjust the threshold voltage of the semiconductor device. Meanwhile, the second blocking layer can effectively block the metal atoms in the work function layer from entering the gate dielectric layer.

Further, the amorphization treatment method is as follows: forming a silicon layer covering the first barrier layer; performing a second annealing treatment on the silicon layer and the first barrier layer, so that silicon atoms in the silicon layer enter the first barrier layer , forming a second barrier layer; after forming the second barrier layer, remove the silicon layer. The amorphization treatment method can transform the first barrier layer into the second barrier layer; in addition, during the second annealing treatment, the silicon layer can adsorb oxygen atoms in the interface layer, so that the interface layer, etc. The thickness of the effective oxide is reduced, thereby improving the performance of the semiconductor device.

In the semiconductor device provided by the present invention, since the second barrier layer has an amorphous structure, the barrier effect of the second barrier layer is strong, and the second barrier layer can effectively prevent the metal atoms in the metal layer from entering the gate dielectric. In addition, the second barrier layer can effectively block the intermediate products generated in the process of forming the metal layer from entering the gate dielectric layer.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (13)

1. A method of forming a semiconductor device, comprising:

providing a substrate, wherein the surface of the substrate is provided with an interlayer dielectric layer, a groove is arranged in the interlayer dielectric layer, and the groove is exposed out of the surface of the substrate;

forming an interface layer, wherein the interface layer covers the bottom and the side wall of the groove;

forming a gate dielectric layer covering the interface layer;

forming a first barrier layer covering the gate dielectric layer;

carrying out non-crystallizing treatment on the first barrier layer to convert the first barrier layer into a second barrier layer;

forming a metal layer covering the second barrier layer, wherein the surface of the metal layer is flush with the surface of the interlayer dielectric layer;

the method for the non-crystallizing treatment comprises the following steps: forming a silicon layer covering the first barrier layer; carrying out second annealing treatment on the silicon layer and the first barrier layer to enable silicon atoms in the silicon layer to enter the first barrier layer to form a second barrier layer; and after the second barrier layer is formed, removing the silicon layer.

2. The method for forming a semiconductor device according to claim 1, further comprising: forming a work function layer overlying the second barrier layer prior to forming the metal layer.

3. The method for forming a semiconductor device according to claim 2, wherein when the semiconductor device is an N-type MOS transistor, a material of the work function layer is TiAl; when the semiconductor device is a P-type MOS transistor, the work function layer is made of TaN.

4. The method for forming the semiconductor device according to claim 1 or 2, wherein the base comprises a substrate and a fin portion located on the surface of the substrate; the recess exposes a top surface and sidewalls of the fin.

5. The method according to claim 1 or 2, wherein the base is a substrate, and the groove exposes a surface of the substrate.

6. The method for forming the semiconductor device according to claim 1 or 2, wherein the material of the gate dielectric layer is a high-K dielectric material.

7. The method for forming a semiconductor device according to claim 1 or 2, wherein a material of the first barrier layer is TiN or TaN.

8. The method of claim 1, wherein the silicon layer is formed by a low pressure chemical vapor deposition process, and the specific process parameters are as follows: the gas used is SiH₄，SiH₄The flow rate of the deposition chamber is 10-60 sccm, the temperature is 350-500 ℃, and the pressure of the deposition chamber is 0.4-2 torr.

9. The method for forming a semiconductor device according to claim 1, wherein the silicon layer has a thickness of 40to 100 angstroms.

10. The method of claim 1, wherein the second annealing process is spike annealing and the gas used is N₂Or Ar, the annealing temperature is 800-1000 ℃.

11. The method according to claim 1, wherein when the first barrier layer is TiN, the second barrier layer is TiSiN.

12. The method for forming a semiconductor device according to claim 1 or 2, wherein the second barrier layer has a thickness of 10 to 30 angstroms.

13. The method according to claim 1 or 2, wherein the metal layer is W, Al, Ti, Cu, Mo, or Pt.

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