CN106449850A - High efficiency silicon-based heterojunction double-sided battery and its preparation method - Google Patents

Abstract

The invention discloses a high-efficiency silicon-based heterojunction double-sided battery and a preparation method thereof, wherein the high-efficiency silicon-based heterojunction double-sided battery comprises: an N-type silicon wafer; The front is sequentially provided with a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, a transparent conductive film layer, and a metal grid electrode; the second intrinsic amorphous The electronic band gap of the silicon layer is greater than that of the first intrinsic amorphous silicon layer; on the reverse side of the N-type silicon wafer, a third intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, and a transparent conductive film are arranged in sequence. layer, metal grid electrodes. The first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer adopted in the present invention are respectively prepared in different chambers, and the preparation temperature of the first intrinsic amorphous silicon layer is higher than that of the second intrinsic amorphous silicon layer. The preparation temperature is high, so that the second intrinsic amorphous silicon layer has a relatively wide electronic band gap, which corresponds to the forbidden band width of crystalline silicon, so it can be used as a blocking layer to prevent electrons from diffusing to the emitter by utilizing the difference in bandwidth, The recombination of electrons and holes is reduced, thereby improving the electrical performance of the battery sheet.

Description

A high-efficiency silicon-based heterojunction double-sided battery and its preparation method

technical field

The invention relates to the field of solar cells, in particular to a high-efficiency silicon-based heterojunction double-sided cell and a preparation method thereof.

Background technique

A thin film solar cell is a solar cell formed by depositing a thin photoelectric material on a substrate. Thin-film solar cells can still generate electricity under weak light conditions, and their production process consumes less energy, which has the potential to greatly reduce raw material and manufacturing costs. Therefore, the market demand for thin-film solar cells is gradually increasing, and thin-film solar cell technology has become a research hotspot in recent years. Among them, improving photoelectric conversion efficiency and reducing costs are the ultimate goals of the solar industry.

Silicon-based solar cells have become more attractive in recent years as the cost of the silicon material has decreased. To improve the conversion efficiency of silicon-based solar cells: two of these techniques have been extensively studied and applied to large-scale production. One is to remove the front grid and bus bars, and integrate the emitter and collector to the back, which is called interdigitated back contact (IBC); the other is based on heterojunction technology to increase the open circuit voltage, mainly because the thin film is not Crystalline silicon has a higher electronic bandgap than crystalline silicon. Thin-film silicon contains hydrogen and is usually deposited onto the surface of a crystalline silicon wafer by chemical vapor deposition with a thickness of less than 10 nm to passivate the dangling bonds on the silicon surface. The advantage of heterojunction technology is that the process of forming a PN junction is simple, and the front and back structures are symmetrical in appearance, so both sides can absorb light. By optimizing the placement angle of the cell, the back side can also absorb scattered light in the environment to increase short circuits. Current, so that the output power of the cell can be increased by 10-20%.

Crystalline silicon heterojunction solar cells usually use N-type crystalline silicon as the substrate, mainly because N-type crystalline silicon contains less impurities and generally has a high minority carrier life. The self-built electric field is high, so it is easier to obtain a high opening voltage of the cell. Due to the high self-built electric field, it is easier to separate the carriers generated in the PN junction and in the crystalline silicon, that is, electrons and holes. However, due to the diffusion of electrons, electrons will also move to the emitter, resulting in electrons and holes being separated. The recombination of the emitter region reduces the short-circuit current of the cell and reduces the photoelectric conversion efficiency of the cell, that is, the output power.

Contents of the invention

In order to solve the problems in the prior art, the object of the present invention is to provide a high-efficiency silicon-based heterojunction double-sided battery and its preparation method, which can well prevent the electrons in the carriers from diffusing to the emitter region, reducing The recombination of electrons and holes increases the short-circuit current of the cell.

To achieve the above object, the present invention adopts the following technical solutions:

A high-efficiency silicon-based heterojunction double-sided cell, comprising: an N-type silicon wafer; a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, A P-type doped amorphous silicon layer, a transparent conductive film layer, and a metal grid electrode; the electronic band gap of the second intrinsic amorphous silicon layer is greater than that of the first intrinsic amorphous silicon layer; on the N-type silicon wafer The reverse side is sequentially provided with a third intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, a transparent conductive film layer, and a metal grid line electrode.

Preferably, the thickness of the second intrinsic amorphous silicon film layer is less than 1 nm, the thicknesses of the first intrinsic amorphous silicon film layer and the third intrinsic amorphous silicon film layer are respectively 5-10 nm, and the P-type The thicknesses of the doped amorphous silicon layer and the N-type doped amorphous silicon layer are 5-10nm respectively, the thickness of the transparent conductive film on the front side of the N-type silicon chip is 70-110nm, and the transparent conductive film on the back side of the N-type silicon chip is The thickness of the conductive film is 25-110 nm.

The present invention also provides a method for preparing a high-efficiency silicon-based heterojunction double-sided cell, comprising the following steps: providing an N-type silicon chip; Chemical vapor deposition method, depositing the first intrinsic amorphous silicon film layer and the third intrinsic amorphous silicon film layer; depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer; at a second temperature Under the condition, a second intrinsic amorphous silicon film layer and a P-type doped amorphous silicon layer are deposited on the first intrinsic amorphous silicon film layer, and the electron band gap of the second intrinsic amorphous silicon layer is larger than that of the first intrinsic amorphous silicon layer. An intrinsic amorphous silicon layer; a transparent conductive film is deposited on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer by PVD magnetron sputtering; the transparent film on the front and back sides of the N-type silicon wafer A metal grid line electrode is formed on the conductive film.

Preferably, the deposition of the first intrinsic amorphous silicon film layer and the third intrinsic amorphous silicon film layer on the front and back sides of the N-type silicon wafer by chemical vapor deposition method is specifically: under the first temperature condition , put the N-type silicon wafer in the reaction chamber, pass the mixed gas of SiH ₄ and H ₂ into the reaction chamber, and deposit the first intrinsic amorphous silicon on the front and back sides of the N-type silicon wafer by chemical vapor deposition method. a silicon film layer and a third intrinsic amorphous silicon film layer.

Preferably, the depositing the N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer is specifically: the N type that will form the first intrinsic amorphous silicon film layer and the third intrinsic amorphous silicon film layer Type silicon wafer is placed in the first doping chamber, and SiH ₄ , H ₂ and dopant-containing gas are introduced into the first doping chamber, thereby depositing N-type doped silicon on the third intrinsic amorphous silicon layer. amorphous silicon layer.

Preferably, the depositing the second intrinsic amorphous silicon film layer and the P-type doped amorphous silicon layer on the first intrinsic amorphous silicon film layer is specifically: under the second temperature condition, the third intrinsic The N-type silicon wafer with the N-type doped amorphous silicon layer formed on the non-crystalline silicon layer is put into the second doping chamber, and the mixed gas of SiH ₄ and H ₂ is introduced into the second doping chamber first, through chemical After the method of vapor phase deposition deposits the second intrinsic amorphous silicon film layer on the first intrinsic amorphous silicon film layer; continue to feed the mixed gas of SiH ₄ and H ₂ , and simultaneously feed the gas containing dopant, A P-type doped amorphous silicon layer is formed on the second intrinsic amorphous silicon film layer.

Preferably, the dopant is P or B.

Preferably, the first temperature is 150-250°C, and the first temperature is at least 20°C higher than the second temperature.

The present invention also provides another method for preparing a high-efficiency silicon-based heterojunction double-sided battery, which includes the following steps: providing an N-type silicon wafer; under the first temperature condition, chemical vapor deposition respectively depositing the third intrinsic amorphous silicon film layer; depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer; An intrinsic amorphous silicon film layer; under a second temperature condition, a second intrinsic amorphous silicon film layer and a P-type doped amorphous silicon layer are deposited on the first intrinsic amorphous silicon film layer; the first The electronic bandgap of the two intrinsic amorphous silicon layers is greater than that of the first intrinsic amorphous silicon layer; transparent conductive materials are deposited on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer by PVD magnetron sputtering respectively. film; metal grid line electrodes are simultaneously formed on the transparent conductive films on the front and back sides of the N-type silicon wafer.

The present invention also provides another method for preparing a high-efficiency silicon-based heterojunction double-sided battery, comprising the following steps: providing an N-type silicon wafer; under the first temperature condition, chemical vapor deposition The first intrinsic amorphous silicon film layer is deposited respectively by method; under the second temperature condition, the second intrinsic amorphous silicon film layer and the P-type doped amorphous silicon layer are deposited on the first intrinsic amorphous silicon film layer ; The electronic band gap of the second intrinsic amorphous silicon layer is greater than that of the first intrinsic amorphous silicon layer; the third intrinsic amorphous silicon film layer is respectively deposited by chemical vapor deposition on the reverse side of the N-type silicon wafer ; On the third intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer is deposited; on a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer, respectively, by means of PVD magnetron sputtering deposition Forming a transparent conductive film; forming metal grid line electrodes on the transparent conductive film on the front and back sides of the N-type silicon wafer at the same time.

The present invention adopts the above technical scheme, by providing a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on one side of the N-type silicon wafer, and the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer The intrinsic amorphous silicon layers are prepared in different chambers, and the preparation temperature of the first intrinsic amorphous silicon layer is higher than that of the second intrinsic amorphous silicon layer, so that the second intrinsic amorphous silicon layer has Larger electronic band gap, so it can be used as a barrier layer to prevent electrons from diffusing to the emitter, reducing the recombination of electrons and holes, thereby improving the electrical performance of the cell and increasing the photoelectric conversion efficiency of the cell, that is, the output power.

Description of drawings

Fig. 1 is a schematic structural view of a high-efficiency silicon-based heterojunction double-sided battery of the present invention;

Fig. 2 is the schematic flow chart of the first embodiment of the preparation method of the present invention;

Fig. 3 is the schematic flow chart of the second embodiment of the preparation method of the present invention;

Fig. 4 is a schematic flow diagram of Example 3 of the preparation method of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

As shown in Figure 1, the present invention discloses a high-efficiency silicon-based heterojunction bifacial battery, which includes:

N-type silicon wafer 1;

On the front side of the N-type silicon wafer 1, a first intrinsic amorphous silicon layer 2, a second intrinsic amorphous silicon layer 3, a P-type doped amorphous silicon layer 4, a transparent conductive film layer 5, Metal grid electrode 6;

A third intrinsic amorphous silicon layer 7 , an N-type doped amorphous silicon layer 8 , a transparent conductive film layer 9 , and a metal grid line electrode 10 are arranged in sequence on the reverse side of the N-type silicon chip.

Wherein, the electronic band gap of the second intrinsic amorphous silicon layer 3 is larger than that of the first intrinsic amorphous silicon layer 2 . The thickness of the second intrinsic amorphous silicon film layer is less than 1 nm, the thicknesses of the first intrinsic amorphous silicon film layer and the third intrinsic amorphous silicon film layer are respectively 5-10 nm, and the N-type doped non-crystalline silicon film layer is The thicknesses of the crystalline silicon layer and the P-type doped amorphous silicon layer are 5-10nm respectively, the thickness of the transparent conductive film arranged on the front side of the N-type silicon wafer is 70-110nm, and the thickness of the transparent conductive film arranged on the reverse side of the N-type silicon wafer is The thickness is 25-110nm.

The N-type silicon wafer described in the present invention can be a monocrystalline silicon wafer or a polycrystalline silicon wafer. Under the irradiation of sunlight, the battery of the present invention will generate a large amount of carbon dioxide in its PN junction and in the N-type crystalline silicon of the substrate. Electrons and holes, usually the self-built electric field in the PN junction will separate the generated electrons and holes. For N-type crystalline silicon, the minority electrons are holes, so the holes move to the light-receiving surface, while the majority electrons move in the opposite direction to generate current. However, due to the effect of electron diffusion, some electrons will also move to the light-receiving surface, thereby increasing the recombination probability of electrons and holes in the PN junction area, resulting in the loss of electrons and reducing the short-circuit current of the cell. In the present invention, the second intrinsic amorphous silicon layer 3 is added to the first intrinsic amorphous silicon layer 2, and the electronic band gap of the second intrinsic amorphous silicon layer 3 is larger than that of the first intrinsic amorphous silicon layer 2, so It can be used as a barrier layer to prevent electrons from diffusing to the PN junction region, that is, the emitter, which reduces the recombination of electrons and holes, thereby improving the electrical performance of the cell and increasing the photoelectric conversion efficiency of the cell, that is, the output power.

Embodiment one:

As shown in Figure 2, the present invention discloses a method for preparing a high-efficiency silicon-based heterojunction double-sided battery, which includes the following steps:

S101: providing an N-type silicon wafer;

S102: Under the first temperature condition, respectively deposit a first intrinsic amorphous silicon film layer and a third intrinsic amorphous silicon film layer by chemical vapor deposition on both sides of the N-type silicon wafer;

S103: Depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer;

S104: Depositing a second intrinsic amorphous silicon film layer and a P-type doped amorphous silicon layer on the first intrinsic amorphous silicon film layer under a second temperature condition;

S105: Depositing a transparent conductive film on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer by PVD (Physical Vapor Deposition) magnetron sputtering deposition;

S106: Simultaneously electroplating metal grid line electrodes on both sides of the transparent conductive film.

The specific steps can be as follows:

Step 1: Provide an N-type silicon wafer, clean and texture the N-type silicon wafer, then place the N-type silicon wafer in the reaction chamber at a temperature of 150-220°C, and feed SiH ₄ and H into the reaction chamber ₂ , wherein the content of _H2 is 5 to 20%, and the first intrinsic amorphous silicon film layer and the third intrinsic amorphous silicon film are deposited on both sides of the N-type silicon wafer by chemical vapor deposition. layer.

Step 2: Put the N-type silicon wafer forming the first intrinsic amorphous silicon film layer and the third intrinsic amorphous silicon film layer into the first doping chamber, and inject SiH ₄ , H ₂ and a gas containing dopant P, thereby depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer;

Step 3: Put the N-type silicon wafer with the N-type doped amorphous silicon layer formed on the third intrinsic amorphous silicon layer into the second doping chamber at a temperature at least 20°C lower than 150-220°C In the second doping chamber, the mixed gas of SiH ₄ and H ₂ is first passed into the second doping chamber, and the second intrinsic amorphous silicon film layer is deposited on the first intrinsic amorphous silicon film layer by chemical vapor deposition; continue to pass through Inject SiH ₄ and H ₂ gases, and simultaneously pass into the gas containing dopant B to form a P-type doped amorphous silicon layer on the second intrinsic amorphous silicon film layer;

Step 4: On the P-type doped amorphous silicon layer on the light-receiving surface and the N-type doped amorphous silicon layer on the backlight surface, a transparent conductive film layer and a metal stack are respectively generated by PVD magnetron sputtering, and then on the A metal grid line pattern is formed after dry film masking, exposure, and development are carried out on the metal stack; then, the leaked metal grid line pattern is thickened by electroplating.

Step 5: Remove the dry film and perform selective etching on the metal stack. The area where the metal stack is not thickened will leak the transparent conductive film layer, thereby forming a metal grid line pattern on the surface, and the battery preparation is completed.

Embodiment two:

As shown in Figure 3, different from the first embodiment, in this embodiment, the third intrinsic amorphous silicon film layer and the N-type doped amorphous silicon layer on one side of the N-type silicon wafer are prepared first, and then Then prepare the first intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer on the other side, and finally prepare a transparent conductive film layer and a metal grid line electrode, which specifically includes the following steps:

S201: providing an N-type silicon wafer;

S202: Under the first temperature condition, respectively deposit a third intrinsic amorphous silicon film layer on the reverse side of the N-type silicon wafer by chemical vapor deposition;

S203: depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer;

S204: respectively depositing a first intrinsic amorphous silicon film layer on the front side of the N-type silicon wafer by chemical vapor deposition;

S205: Depositing a second intrinsic amorphous silicon film layer and a P-type doped amorphous silicon layer on the first intrinsic amorphous silicon film layer under a second temperature condition;

S206: Form a transparent conductive film on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer by PVD magnetron sputtering deposition;

S207: electroplating metal grid line electrodes on the transparent conductive films on the front and back sides of the N-type silicon wafer at the same time.

The first temperature is at least 20°C higher than the second temperature.

Embodiment three:

As shown in Figure 4, the difference from Example 1 is that in this example, the first intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer and the P-type Doping the amorphous silicon layer, and then preparing the third intrinsic amorphous silicon film layer and the N-type doped amorphous silicon layer on the other side, and finally preparing the transparent conductive film layer and the metal grid line electrode, which specifically includes the following steps:

S301: providing an N-type silicon wafer;

S302: Depositing a first intrinsic amorphous silicon film layer on the front side of the N-type silicon wafer by chemical vapor deposition under the first temperature condition;

S303: Depositing a second intrinsic amorphous silicon film layer and a P-type doped amorphous silicon layer on the first intrinsic amorphous silicon film layer under a second temperature condition;

S304: respectively depositing a third intrinsic amorphous silicon film layer on the reverse surface of the N-type silicon wafer by chemical vapor deposition;

S305: depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer;

S306: Forming a transparent conductive film on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer by PVD magnetron sputtering deposition;

S307: Electroplating metal grid line electrodes on the transparent conductive films on the front and back sides of the N-type silicon wafer at the same time.

The first temperature is at least 20°C higher than the second temperature.

In the present invention, metal grid wire electrodes are arranged on the front and back sides of the N-type substrate, so that the front and back sides of the cell can absorb light, and the output power of the cell can be increased. The first intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer, and the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are respectively prepared in different chambers, the first intrinsic amorphous silicon layer The preparation temperature of the crystalline silicon layer is higher than that of the second intrinsic amorphous silicon layer, so that the second intrinsic amorphous silicon layer has a larger electronic band gap, so it can be used as a blocking layer to prevent electrons from diffusing to The PN junction area, that is, the emitter, reduces the loss of electrons and improves the photoelectric conversion efficiency. Among them, the "Silicon-based Heterojunction Double-sided Solar Cell Technology" disclosed in the present invention is "Silicon-based Heterojunction Double-sided Solar Cell Technology" in English, abbreviated as "HDT".

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (10)

1. A high-efficiency silicon-based heterojunction double-sided cell, characterized in that: comprising: N-type silicon wafer; A first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, a transparent conductive film layer, and a metal grid line electrode are arranged in sequence on the front side of the N-type silicon chip; The electronic band gap of the second intrinsic amorphous silicon layer is larger than that of the first intrinsic amorphous silicon layer; A third intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, a transparent conductive film layer, and a metal grid line electrode are arranged in sequence on the reverse side of the N-type silicon chip. 2. The high-efficiency silicon-based heterojunction double-sided cell according to claim 1, characterized in that: the thickness of the second intrinsic amorphous silicon film layer is less than 1 nm, and the first intrinsic amorphous silicon film layer and the second intrinsic amorphous silicon film layer The thicknesses of the three intrinsic amorphous silicon layers are 5-10nm respectively, and the thicknesses of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer are respectively 5-10nm, and are arranged on the front side of the N-type silicon wafer. The thickness of the transparent conductive film is 70-110nm, and the thickness of the transparent conductive film on the reverse side of the N-type silicon chip is 25-110nm. 3. A method for preparing a high-efficiency silicon-based heterojunction double-sided cell, comprising the following steps: Provide an N-type silicon wafer; Depositing the first intrinsic amorphous silicon film layer and the third intrinsic amorphous silicon film layer on the front and back sides of the N-type silicon wafer by chemical vapor deposition method under the first temperature condition; Depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer; Under the second temperature condition, a second intrinsic amorphous silicon film layer and a P-type doped amorphous silicon layer are deposited on the first intrinsic amorphous silicon film layer, and electrons in the second intrinsic amorphous silicon layer a bandgap greater than the first intrinsic amorphous silicon layer; Depositing a transparent conductive film by PVD magnetron sputtering on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer respectively; A metal grid line electrode is formed on the transparent conductive film on the front and back sides of the N-type silicon chip. 4. The method for preparing a high-efficiency silicon-based heterojunction double-sided battery according to claim 3, characterized in that: the first intrinsic amorphous is deposited on the front and back sides of the N-type silicon wafer by chemical vapor deposition respectively. The silicon film layer and the third intrinsic amorphous silicon film layer are as follows: under the first temperature condition, the N-type silicon chip is placed in the reaction chamber, and the mixed gas of _SiH4 and _H2 is passed into the reaction chamber, and the chemical The first intrinsic amorphous silicon film layer and the third intrinsic amorphous silicon film layer are sequentially deposited on the front and back sides of the N-type silicon wafer by vapor deposition method. 5. The method for preparing a high-efficiency silicon-based heterojunction double-sided battery according to claim 3, characterized in that: said depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer is specifically: The N-type silicon chip forming the first intrinsic amorphous silicon film layer and the third intrinsic amorphous silicon film layer is put into the first doping chamber, and SiH ₄ , H ₂ and dopant gas, thereby depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer. 6. The method for preparing a high-efficiency silicon heterojunction double-sided battery according to claim 3, characterized in that: the second intrinsic amorphous silicon film layer and the P-type silicon film layer are deposited on the first intrinsic amorphous silicon film layer. Doping the amorphous silicon layer specifically includes: placing an N-type silicon chip formed with an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer into the second doping chamber under the second temperature condition, First pass into the second doping chamber the mixed gas of SiH ₄ and H ₂ , after depositing the second intrinsic amorphous silicon film layer on the first intrinsic amorphous silicon film layer by chemical vapor deposition; continue to pass A mixed gas of SiH ₄ and H ₂ is injected, and a dopant-containing gas is simultaneously introduced to form a P-type doped amorphous silicon layer on the second intrinsic amorphous silicon film layer. 7. The method for preparing a high-efficiency silicon-based heterojunction double-sided battery according to claim 5 or 6, wherein the dopant is P or B. 8. The method for preparing a high-efficiency silicon-based heterojunction double-sided battery according to claim 3, wherein the first temperature is 150-250°C, and the first temperature is at least 20°C higher than the second temperature. 9. A method for preparing a high-efficiency silicon-based heterojunction double-sided battery, comprising the following steps: Provide an N-type silicon wafer; Under the first temperature condition, a third intrinsic amorphous silicon film layer is respectively deposited on the opposite surface of the N-type silicon wafer by chemical vapor deposition; Depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer; Depositing a first intrinsic amorphous silicon film layer on the front side of the N-type silicon wafer by chemical vapor deposition; Under the second temperature condition, a second intrinsic amorphous silicon film layer and a P-type doped amorphous silicon layer are deposited on the first intrinsic amorphous silicon film layer; electrons in the second intrinsic amorphous silicon layer a bandgap greater than the first intrinsic amorphous silicon layer; Depositing a transparent conductive film by PVD magnetron sputtering on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer respectively; The metal gate line electrodes are simultaneously formed on the transparent conductive films on the front and back sides of the N-type silicon chip. 10. A method for preparing a high-efficiency silicon-based heterojunction bifacial cell, comprising the following steps: Provide an N-type silicon wafer; Depositing a first intrinsic amorphous silicon film layer on the front side of the N-type silicon wafer by chemical vapor deposition method under the first temperature condition; Under the second temperature condition, a second intrinsic amorphous silicon film layer and a P-type doped amorphous silicon layer are deposited on the first intrinsic amorphous silicon film layer; electrons in the second intrinsic amorphous silicon layer a bandgap greater than the first intrinsic amorphous silicon layer; respectively depositing a third intrinsic amorphous silicon film layer by chemical vapor deposition on the opposite surface of the N-type silicon wafer; Depositing an N-type doped amorphous silicon layer on the third intrinsic amorphous silicon layer; A transparent conductive film is formed on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer by PVD magnetron sputtering deposition; The metal gate line electrodes are simultaneously formed on the transparent conductive films on the front and back sides of the N-type silicon chip.