CN106504721A - A shift register, its driving method, gate driving circuit and display device - Google Patents

Abstract

The invention discloses a kind of shift register, its driving method, gate driver circuit and display device, including：Input module, voltage coupling module, threshold voltage writing module, the first output module and the second output module；Wherein, by cooperating for aforementioned four module, the voltage of Section Point can be compensated, to ensure after the effective impulse signal of shift register output drive signal, the current potential of first node can be made in the stable state of invalid current potential, so as to reduce the output noise of drive signal output end, and then can avoid showing exception occur.

Description

A shift register, its driving method, gate driving circuit and display device

technical field

The invention relates to the field of display technology, in particular to a shift register, a driving method thereof, a gate driving circuit and a display device.

Background technique

With the rapid development of display technology, the display panel is more and more developed towards the direction of high integration and low cost. Among them, the gate driver on array (Gate Driver on Array, GOA) technology integrates the thin film transistor (Thin Film Transistor, TFT) gate switching circuit on the array substrate of the display panel to form a scan drive for the display panel, so that the gate driver can be omitted. The wiring space of the Bonding area of the integrated circuit (Integrated Circuit, IC) and the fan-out (Fan-out) area can not only reduce the product cost in terms of material cost and manufacturing process, but also enable the display panel to achieve Beautiful design with symmetry on both sides and narrow frame; moreover, this integrated process can also save the Bonding process in the direction of the gate scanning line, thereby improving production capacity and yield.

A general gate drive circuit is composed of a plurality of cascaded shift registers, through which the shift registers at various levels are used to sequentially input scan signals to each row of gate lines on the display panel. At present, after the shift register completes the output of the high-potential scanning signal, the shift register enters the low-potential maintenance stage, specifically: the potential of the pull-down node is high potential, and the output pull-down transistor is controlled by the signal of the pull-down node. The low-potential reference signal is provided to the drive signal output terminal, so that the drive signal output terminal is in a low-potential state; the node pull-down transistor provides the low-potential reference signal to the pull-up node under the control of the signal of the pull-down node, so that the pull-up The node becomes low potential, so that the pull-up node is in a low potential state, so as to reduce the output noise of the driving signal output terminal. However, in the low potential maintenance stage, the threshold voltage of the node pull-down transistor will drift positively, causing the node pull-down transistor to not be fully turned on, and may even cause the node pull-down transistor to be cut off, thus causing the pull-up node to be unable to maintain a low potential stably, resulting in a shift The output of the drive signal output terminal of the bit register produces noise, which may even cause abnormalities in the display.

Contents of the invention

Embodiments of the present invention provide a shift register, its driving method, a gate driving circuit and a display device, which are used to solve the problem that in the prior art, in the low potential holding stage, the pull-up node cannot stably maintain low potential, thereby causing shift The output of the drive signal output terminal of the bit register produces noise, which may even cause abnormal display problems.

Therefore, an embodiment of the present invention provides a shift register, including: an input module, a voltage coupling module, a threshold voltage writing module, a first output module, and a second output module; wherein,

The input module is respectively connected to the input signal terminal, the first reference signal terminal, the first node and the second node; the input module is used to provide the signal of the input signal terminal to the said input signal terminal under the control of the input signal terminal. The first node provides the signal of the first reference signal terminal to the second node under the control of the input signal terminal;

The voltage coupling module is respectively connected to the first clock signal terminal and the second node; the voltage coupling module is used to maintain the connection between the second node and the first node when the second node is in a floating state. The voltage difference between the clock signal terminals is stable;

The threshold voltage writing module is respectively connected to the first reset signal terminal, the first reference signal terminal, the first node and the second node; the threshold voltage writing module is used for conducting the first node and the second node under the control of the reset signal terminal, and providing the signal of the first reference signal terminal to the first node under the control of the signal of the second node;

The first output module is respectively connected to the first clock signal end, the first node, and the drive signal output end of the shift register; the first output module is used for the signal at the first node Under the control of the first clock signal end, the signal is provided to the drive signal output end, and when the first node is in a floating state, the connection between the first node and the drive signal output end is maintained Stable voltage difference;

The second output module is respectively connected to the second clock signal terminal, the second reference signal terminal, the second node, and the drive signal output terminal; the second output module is used for the signal at the second node The signal of the second reference signal terminal is provided to the drive signal output terminal under the control of the second reference signal terminal, and the signal of the second reference signal terminal is provided to the drive signal output terminal under the control of the second clock signal terminal.

Preferably, in the above-mentioned shift register provided by the embodiment of the present invention, the voltage coupling module includes: a first capacitor; wherein,

A first end of the first capacitor is connected to the second node, and a second end is connected to the first clock signal end.

Preferably, in the above-mentioned shift register provided by the embodiment of the present invention, the threshold voltage writing module includes: a first switching transistor and a second switching transistor; wherein,

The gate of the first switching transistor is connected to the first reset signal terminal, the source is connected to the first node, and the drain is connected to the second node;

The gate of the second switching transistor is connected to the second node, the source is connected to the first reference signal terminal, and the drain is connected to the first node.

Preferably, in the above-mentioned shift register provided by the embodiment of the present invention, the input module includes: a third switch transistor and a fourth switch transistor; wherein,

Both the gate and the drain of the third switch transistor are connected to the input signal terminal, and the source is connected to the first node;

The gate of the fourth switch transistor is connected to the input signal terminal, the source is connected to the first reference signal terminal, and the drain is connected to the second node.

Preferably, in the above-mentioned shift register provided by the embodiment of the present invention, the first output module includes: a fifth switching transistor and a second capacitor; wherein,

The gate of the fifth switching transistor is connected to the first node, the source is connected to the first clock signal terminal, and the drain is connected to the driving signal output terminal;

A first end of the second capacitor is connected to the first node, and a second end is connected to the driving signal output end.

Preferably, in the above-mentioned shift register provided by the embodiment of the present invention, the second output module includes: a sixth switch transistor and a seventh switch transistor; wherein,

The gate of the sixth switch transistor is connected to the second node, the source is connected to the second reference signal terminal, and the drain is connected to the driving signal output terminal;

The gate of the seventh switch transistor is connected to the second clock signal terminal, the source is connected to the second reference signal terminal, and the drain is connected to the driving signal output terminal.

Preferably, the above-mentioned shift register provided by the embodiment of the present invention further includes: a potential stabilization module; wherein,

The potential stabilizing module is respectively connected to the second reset signal terminal, the second reference signal terminal and the drive signal output terminal; the potential stabilizing module is used to control the second reset signal terminal The signals of the two reference signal terminals are provided to the driving signal output terminal.

Preferably, in the above-mentioned shift register provided by the embodiment of the present invention, the potential stabilization module includes: an eighth switch transistor; wherein,

The gate of the eighth switch transistor is connected to the second reset signal terminal, the source is connected to the second reference signal terminal, and the drain is connected to the driving signal output terminal.

Correspondingly, an embodiment of the present invention also provides a gate drive circuit, including cascaded N shift registers of any of the above-mentioned embodiments of the present invention; wherein, N is an integer greater than or equal to 4;

The input signal end of the first-stage shift register is connected to the first frame trigger signal end;

The input signal end of the second-stage shift register is connected to the second frame trigger signal end;

The input signal terminals of the nth stage shift register are respectively connected to the drive signal output terminals of the n-2th stage shift register;

The first reset signal terminal of the n-2th shift register is respectively connected to the drive signal output terminal of the n+1st shift register; wherein, n is an integer greater than or equal to 3 and less than or equal to N-1.

Correspondingly, an embodiment of the present invention also provides a display device, including any one of the above-mentioned gate driving circuits provided by the embodiments of the present invention.

Correspondingly, an embodiment of the present invention also provides a driving method for any one of the above-mentioned shift registers provided by the embodiment of the present invention, including: a first stage, a second stage, a third stage, a fourth stage, and a fifth stage and the sixth stage; where,

In the first stage, the input module provides the signal of the input signal terminal to the first node under the control of the input signal terminal, and provides the signal of the first reference signal terminal under the control of the input signal terminal The signal is provided to the second node; the first output module provides the signal of the first clock signal terminal to the driving signal output terminal under the control of the signal of the first node; the second output module providing the signal of the second reference signal terminal to the drive signal output terminal under the control of the second clock signal terminal;

In the second stage, the first output module provides the signal of the first clock signal terminal to the driving signal output terminal under the control of the signal of the first node, and when the first node is in In the floating state, keep the voltage difference between the first node and the output terminal of the driving signal stable; the input module provides the signal of the first reference signal terminal to the second node;

In the third stage, the first output module provides the signal of the first clock signal terminal to the driving signal output terminal under the control of the signal of the first node, and when the first node is in In the floating state, keep the voltage difference between the first node and the drive signal output terminal stable; when the second node is in the floating state, the voltage coupling module keeps the second node in the floating state. The voltage difference between the first clock signal terminals is stable;

In the fourth stage, the threshold voltage writing module turns on the first node and the second node under the control of the first reset signal terminal, and under the control of the signal of the second node providing the signal of the first reference signal terminal to the first node; the second output module providing the signal of the second reference signal terminal to the driving signal output terminal under the control of the second clock signal terminal ;

In the fifth stage, the voltage coupling module keeps the voltage difference between the second node and the first clock signal terminal stable when the second node is in a floating state; the second output The module provides the signal of the second reference signal terminal to the drive signal output terminal under the control of the signal of the second node; the threshold voltage writing module supplies the signal of the second node under the control of the signal of the second node providing the signal of the first reference signal terminal to the first node;

In the sixth stage, when the second node is in a floating state, the voltage coupling module keeps the voltage difference between the second node and the first clock signal terminal stable; the second output The module provides the signal of the second reference signal terminal to the driving signal output terminal under the control of the second clock signal terminal.

The beneficial effects of the present invention are as follows:

The shift register, its driving method, gate driving circuit and display device provided by the embodiments of the present invention include: an input module, a voltage coupling module, a threshold voltage writing module, a first output module, and a second output module; wherein, the input The module is used to provide the signal of the input signal terminal to the first node under the control of the input signal terminal, and to provide the signal of the first reference signal terminal to the second node under the control of the input signal terminal; the voltage coupling module is used for floating the second node When in the connected state, keep the voltage difference between the second node and the first clock signal terminal stable; the threshold voltage writing module is used to conduct the first node and the second node under the control of the first reset signal terminal, and at the second Under the control of the signal of the node, the signal of the first reference signal terminal is provided to the first node; the first output module is used for providing the signal of the first clock signal terminal to the driving signal output terminal under the control of the signal of the first node, and in When the first node is in a floating state, keep the voltage difference between the first node and the output terminal of the driving signal stable; the second output module is used to provide the signal of the second reference signal terminal to the driver under the control of the signal of the second node The signal output terminal, and the signal of the second reference signal terminal is provided to the driving signal output terminal under the control of the second clock signal terminal. Therefore, through the mutual cooperation of the above four modules, the voltage of the second node can be compensated to ensure that after the shift register outputs the effective pulse signal of the drive signal, the potential of the first node can be in a stable state of inactive potential, thereby The output noise at the drive signal output terminal is reduced, thereby avoiding display abnormalities.

Description of drawings

Fig. 1a is one of the structural schematic diagrams of the shift register provided by the embodiment of the present invention;

Fig. 1b is the second structural schematic diagram of the shift register provided by the embodiment of the present invention;

Fig. 2a is a specific structural schematic diagram of the shift register shown in Fig. 1a;

Fig. 2b is a schematic structural diagram of the shift register shown in Fig. 1b;

FIG. 3a is an input and output timing diagram of the shift register shown in FIG. 2a;

FIG. 3b is an input and output timing diagram of the shift register shown in FIG. 2b;

Fig. 4a is one of the simulation schematic diagrams of the shift register shown in Fig. 2b;

Fig. 4b is the second schematic diagram of the simulation simulation of the shift register shown in Fig. 2b;

FIG. 5 is a flowchart of a driving method of a shift register provided by an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention more clear, the specific implementations of the shift register, its driving method, gate driving circuit and display device provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only used to illustrate and explain the present invention, not to limit the present invention. And in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

An embodiment of the present invention provides a shift register, as shown in Figure 1a and Figure 1b, including: an input module 1, a voltage coupling module 2, a threshold voltage writing module 3, a first output module 4 and a second output module 5 ;in,

The input module 1 is respectively connected to the input signal terminal Input, the first reference signal terminal VSS1, the first node A and the second node B; the input module 1 is used to provide the signal of the input signal terminal Input under the control of the input signal terminal Input to The first node A provides the signal of the first reference signal terminal VSS1 to the second node B under the control of the input signal terminal Input;

The voltage coupling module 2 is respectively connected to the first clock signal terminal CLK and the second node B; the voltage coupling module 2 is used to maintain the connection between the second node B and the first clock signal terminal CLK when the second node B is in a floating state. The voltage difference is stable;

The threshold voltage writing module 3 is respectively connected to the first reset signal terminal RST1, the first reference signal terminal VSS1, the first node A and the second node B; the threshold voltage writing module 3 is used for controlling the first reset signal terminal RST1 Down-conducting the first node A and the second node B, and providing the signal of the first reference signal terminal VSS1 to the first node A under the control of the signal of the second node B;

The first output module 4 is respectively connected with the first clock signal terminal CLK, the first node A and the drive signal output terminal Output of the shift register; The signal of the clock signal terminal CLK is provided to the drive signal output terminal Output, and when the first node A is in a floating state, the voltage difference between the first node A and the drive signal output terminal Output is kept stable;

The second output module 5 is connected to the second clock signal terminal CLKB, the second reference signal terminal VSS2, the second node B, and the drive signal output terminal Output respectively; the second output module 5 is used to control the signal of the second node B The signal of the second reference signal terminal VSS2 is provided to the driving signal output terminal Output, and the signal of the second reference signal terminal VSS2 is provided to the driving signal output terminal Output under the control of the second clock signal terminal CLKB.

The above-mentioned shift register provided by the embodiment of the present invention includes: an input module, a voltage coupling module, a threshold voltage writing module, a first output module, and a second output module; wherein, the input module is used to input The signal at the signal terminal is provided to the first node, and the signal at the first reference signal terminal is provided to the second node under the control of the input signal terminal; the voltage coupling module is used to maintain the connection between the second node and the first node when the second node is in a floating state. The voltage difference between the clock signal terminals is stable; the threshold voltage writing module is used to conduct the first node and the second node under the control of the first reset signal terminal, and to convert the first reference signal to the second node under the control of the signal of the second node. The signal at the end is provided to the first node; the first output module is used to provide the signal at the first clock signal end to the drive signal output end under the control of the signal at the first node, and when the first node is in a floating state, keep the second The voltage difference between a node and the drive signal output terminal is stable; the second output module is used to provide the signal of the second reference signal terminal to the drive signal output terminal under the control of the signal of the second node, and the signal at the second clock signal terminal The signal of the second reference signal terminal is provided to the driving signal output terminal under control. Therefore, the above-mentioned shift register provided by the embodiment of the present invention can compensate the voltage of the second node through the mutual cooperation of the above-mentioned four modules, so as to ensure that the voltage of the first node can be adjusted after the shift register outputs the effective pulse signal of the driving signal. The potential is in a stable state of the invalid potential, thereby reducing the output noise at the output terminal of the driving signal, thereby avoiding abnormalities in the display.

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, when the effective pulse signal at the input signal terminal is at a high potential, the voltage amplitude of the effective pulse signal at the input signal terminal, the voltage amplitude of the first clock signal and the second The voltage amplitudes of the clock signals may all be equal. Certainly, at least two of the voltage amplitude of the effective pulse signal at the input signal terminal, the voltage amplitude of the first clock signal, and the voltage amplitude of the second clock signal may be unequal. In practical applications, the voltage amplitude of the effective pulse signal at the input signal terminal, the voltage amplitude of the signal at the first clock signal terminal, and the voltage amplitude of the signal at the second clock signal terminal need to be designed and determined according to actual application conditions, and are not limited here.

Further, after the effective pulse signal of the scan signal output by the output terminal Output of the driving signal is completed, in order to further ensure that the potential of the output terminal Output of the driving signal can be opposite to the potential of the effective pulse signal of the input signal terminal Input in time, the embodiment of the present invention provides In the above shift register, as shown in Figure 1b, also includes: a potential stabilization module 6; wherein,

The potential stabilization module 6 is connected to the second reset signal terminal RST2, the second reference signal terminal VSS2, and the drive signal output terminal Output respectively; the potential stabilization module 6 is used to control the second reference signal terminal VSS2 under the control of the second reset signal terminal RST2 The signal of is provided to the drive signal output terminal Output.

The present invention will be described in detail below in conjunction with specific embodiments. It should be noted that this embodiment is for better explaining the present invention, but not limiting the present invention.

Specifically, during specific implementation, in the above shift register provided by the embodiment of the present invention, as shown in FIG. 2a and FIG. 2b, the threshold voltage writing module 3 may specifically include: a first switch transistor M1 and a second switch transistor M1 M2; where,

The gate of the first switching transistor M1 is connected to the first reset signal terminal RST1, the source is connected to the first node A, and the drain is connected to the second node B;

The gate of the second switching transistor M2 is connected to the second node B, the source is connected to the first reference signal terminal VSS1 , and the drain is connected to the first node A.

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, when the valid pulse signal at the first reset signal end is at a high potential, the first switch transistor can be an N-type switch transistor; or, when the first reset signal terminal When the effective pulse signal at the terminal is at a low potential, the first switching transistor may be a P-type switching transistor, which is not limited herein.

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, when the effective pulse signal of the input signal terminal Input is at a high potential, as shown in FIG. 2a and FIG. 2b, the first switch transistor M1 and the second switch transistor M1 The transistor M2 can be an N-type switch transistor.

During specific implementation, in the above shift register provided by the embodiment of the present invention, when the first switching transistor is in the conducting state under the control of the first reset signal terminal, the first node and the second node are turned on. When the second switch transistor is in a conducting state under the control of the signal at the second node, it provides the signal at the first reference signal terminal to the first node.

The above is just an example to illustrate the specific structure of the threshold voltage writing module in the shift register. In actual implementation, the specific structure of the threshold voltage writing module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and can also be known by those skilled in the art. Other structures are not limited here.

Specifically, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2a and FIG. 2b, the voltage coupling module 2 may specifically include: a first capacitor C1; wherein,

A first terminal of the first capacitor C1 is connected to the second node B, and a second terminal is connected to the first clock signal terminal CLK.

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, when the second node is in a floating state, due to the bootstrap effect of the first capacitor, the voltage difference across the first capacitor can be kept stable, that is, the The voltage difference between the second node and the first clock signal terminal is stable.

The above is just an example to illustrate the specific structure of the voltage coupling module in the shift register. In actual implementation, the specific structure of the voltage coupling module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be other structures known to those skilled in the art. It is not limited here.

Specifically, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2a and FIG. 2b, the input module 1 may specifically include: a third switch transistor M3 and a fourth switch transistor M4; wherein ,

Both the gate and the drain of the third switch transistor M3 are connected to the input signal terminal Input, and the source is connected to the first node A;

The gate of the fourth switching transistor M4 is connected to the input signal terminal Input, the source is connected to the first reference signal terminal VSS1, and the drain is connected to the second node B

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, when the effective pulse signal of the input signal terminal Input is at a high potential, as shown in Figure 2a and Figure 2b, the third switch transistor M3 and the fourth switch transistor M3 The transistor M4 can be an N-type switch transistor.

During specific implementation, in the above shift register provided by the embodiment of the present invention, the fourth switch transistor provides the signal of the first reference signal terminal to the second node under the control of the input signal terminal. The third switch transistor provides the signal of the input signal terminal to the first node under the control of the input signal terminal; wherein, in practical applications, since the gate and the drain of the third switch transistor are connected to the input signal terminal, the third switch transistor The gate voltage of the gate is equal to the voltage amplitude V _Input of the effective pulse signal at the input signal terminal, and the gate-source voltage V _gs (M3) between the gate of the third switching transistor and its source is greater than the threshold voltage V of the third switching transistor _th (M3), that is, when V _gs (M3)>V _th (M3), the third switching transistor can be in the conduction state and provide the signal at the input signal terminal to the first node until the voltage at the first node V _A =V When _Input -V _th (M3), the third switching transistor will be turned off.

The above is just an example to illustrate the specific structure of the input module in the shift register. In actual implementation, the specific structure of the input module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be other structures known to those skilled in the art. Here Not limited.

Specifically, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2a and FIG. 2b, the first output module 4 may specifically include: a fifth switching transistor M5 and a second capacitor C2; in,

The gate of the fifth switching transistor M5 is connected to the first node A, the source is connected to the first clock signal terminal CLK, and the drain is connected to the driving signal output terminal Output;

A first end of the second capacitor C2 is connected to the first node A, and a second end is connected to the driving signal output end Output.

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, when the effective pulse signal of the input signal terminal Input is at a high potential, as shown in Figure 2a and Figure 2b, the fifth switch transistor can be an N-type switch transistor.

During specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, when the fifth switch transistor is in the conduction state under the control of the signal at the first node, the signal at the first clock signal terminal is provided to the drive signal output terminal . When the first node is in a floating state, due to the bootstrap function of the second capacitor, the voltage difference across the second capacitor can be kept stable, that is, the voltage difference between the first node and the output terminal of the driving signal can be kept stable.

The above is just an example to illustrate the specific structure of the first output module in the shift register. In actual implementation, the specific structure of the first output module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and can also be other known by those skilled in the art. The structure is not limited here.

Specifically, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2a and FIG. 2b, the second output module 5 may specifically include: a sixth switch transistor M6 and a seventh switch transistor M7 ;in,

The gate of the sixth switching transistor M6 is connected to the second node B, the source is connected to the second reference signal terminal VSS2, and the drain is connected to the driving signal output terminal Output;

The gate of the seventh switching transistor M7 is connected to the second clock signal terminal CLKB, the source is connected to the second reference signal terminal VSS2 , and the drain is connected to the driving signal output terminal Output.

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, when the effective pulse signal of the input signal terminal Input is at a high potential, as shown in Fig. 2a and Fig. 2b, the sixth switch transistor M6 and the seventh switch transistor M6 The transistor M7 can be an N-type switch transistor.

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, when the sixth switch transistor is in the conduction state under the control of the signal at the second node, the signal at the second reference signal terminal is provided to the drive signal output terminal . When the seventh switch transistor is in a conducting state under the control of the second clock signal terminal, it provides the signal of the second reference signal terminal to the driving signal output terminal.

The above is just an example to illustrate the specific structure of the second output module in the shift register. In actual implementation, the specific structure of the second output module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and can also be other known by those skilled in the art. The structure is not limited here.

Specifically, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2b, the potential stabilization module 6 may specifically include: an eighth switch transistor M8; wherein,

The gate of the eighth switch transistor M8 is connected to the second reset signal terminal RST2 , the source is connected to the second reference signal terminal VSS2 , and the drain is connected to the driving signal output terminal Output.

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, when the valid pulse signal at the second reset signal terminal is at a high potential, the eighth switch transistor can be an N-type switch transistor; or, when the second reset signal terminal When the valid pulse signal at the terminal is at a low potential, the eighth switch transistor may be a P-type switch transistor, which is not limited herein.

In specific implementation, in the shift register provided by the embodiment of the present invention, when the effective pulse signal of the input signal terminal Input is at a high potential, as shown in FIG. 2b, the eighth switch transistor may be an N-type switch transistor.

During specific implementation, in the above shift register provided by the embodiment of the present invention, when the eighth switch transistor is in the conduction state under the control of the second reset signal terminal, the signal of the second reference signal terminal is provided to the driving signal output terminal.

The above is only an example to illustrate the specific structure of the potential stabilization module in the shift register. In actual implementation, the specific structure of the potential stabilization module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be other structures known to those skilled in the art. It is not limited here.

In specific implementation, in the shift register provided by the embodiment of the present invention, when the effective pulse signal at the input signal terminal is at high potential, the potential at the first reference signal terminal is at low potential, and the potential at the second reference signal terminal is at low potential. Wherein, the voltage of the first reference signal terminal is greater than or equal to the voltage of the second reference signal terminal. When the voltage of the first reference signal terminal is greater than the voltage of the second reference signal terminal, the shift register can be prevented from leaking electricity. In practical applications, the voltage of the first reference signal terminal and the voltage of the second reference signal terminal need to be designed and determined according to the actual application situation, which are not limited here.

Further, during specific implementation, in the shift register provided by the embodiment of the present invention, the first reference signal terminal and the second reference signal terminal are the same signal terminal. In this way, the voltage of the first reference signal terminal is equal to the voltage of the second reference signal terminal. Moreover, the arrangement of signal lines can be further reduced, and the manufacturing process can be simplified.

Preferably, in order to simplify the manufacturing process, in the specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in Figure 2a and Figure 2b, all switch transistors can be N-type switch transistors, which are not described here. limited.

Further, in specific implementation, the N-type switching transistor is turned on under the action of a high potential, and is turned off under the action of a low potential; the P-type switching transistor is turned off under the action of a high potential, and turned on under the action of a low potential.

It should be noted that the switching transistor mentioned in the above-mentioned embodiments of the present invention may be an amorphous silicon thin film transistor (a-Si TFT) or a Metal Oxide Semiconductor Field Effect Transistor (MOS, Metal Oxide Scmiconductor). limited. In a specific implementation, the functions of the sources and drains of these transistors can be interchanged according to different types of transistors and input signals, and no specific distinction is made here.

The working process of the above-mentioned shift register provided by the embodiment of the present invention will be described below in conjunction with the circuit sequence diagram. Wherein, it is taken as an example that the voltage of the first reference signal terminal is equal to the voltage of the second reference signal terminal. In the following description, 1 represents a high-potential signal, and 0 represents a low-potential signal. Among them, 1 and 0 represent its logic potential, which is only for better explaining the working process of the above-mentioned shift register provided by the embodiment of the present invention, rather than The potential applied to the gate of each switching transistor during specific implementation.

Embodiment one,

Taking the structure of the shift register shown in Figure 2a as an example to describe its working process, wherein, in the shift register shown in Figure 2a, all switching transistors are N-type switching transistors, and each N-type switching transistor is in the It is turned on under the action of high potential and cut off under the action of low potential; the potential of the first reference signal terminal VSS1 is low potential, and the corresponding input and output timing diagram is shown in Figure 3a, specifically, the input and output shown in Figure 3a is selected There are six stages in the sequence diagram: the first stage T1, the second stage T2, the third stage T3, the fourth stage T4, the fifth stage T5 and the sixth stage T6.

In the first stage T1, Input=1, RST1=0, CLK=0, CLKB=1.

Since Input=1, both the third switch transistor M3 and the fourth switch transistor M4 are turned on. Since the third switching transistor M3 is turned on and provides the signal of the input signal terminal Input with a high potential to the first node A, and since both the gate and the drain of the third switching transistor M3 are connected to the input signal terminal Input, and the third The voltage of the gate of the switching transistor M3 is equal to the voltage V _Input of the input signal terminal Input, and the gate-source voltage V _gs (M3) between the gate of the third switching transistor M3 and its source is greater than the threshold of the third switching transistor M3 Voltage V _th (M3), that is, when V _gs (M3)>V _th (M3), the third switching transistor M3 is in a conducting state and provides the signal of the input signal terminal Input to the first node A until the first node A is in When the voltage V _A at high potential = V _Input -V _th (M3), the third switching transistor M3 will be turned off, so that the potential of the first node A is high potential, and the voltage V _{A of the first node A} = V _Input -V _th (M3). Since the potential of the first node A is high potential, the fifth switch transistor M5 is turned on and provides the signal of the low potential first clock signal terminal CLK to the drive signal output terminal Output, so the second capacitor C2 is charged, and the drive signal output The potential of the terminal Output is a low potential, that is, the driving signal output terminal Output outputs a low potential driving signal. Since the fourth switch transistor M4 is turned on and provides the signal of the first reference signal terminal VSS1 with a low potential to the second node B, the potential of the second node B is low. Since the potential of the second node B is low, both the second switch transistor M2 and the sixth switch transistor M6 are turned off. Since CLKB=1, the seventh switch transistor M7 is turned on and provides the signal of the low potential second reference signal terminal VSS2 to the driving signal output terminal Output, further ensuring that the potential of the driving signal output terminal Output is low. Since RST1=0, the first switching transistor M1 is turned off.

In the second phase T2, Input=1, RST1=0, CLK=1, CLKB=0.

Since Input=1, the fourth switching transistor M4 is turned on. Since the fourth switching transistor M4 is turned on and provides the signal of the low potential first reference signal terminal VSS1 to the second node B, the potential of the second node B is low. Since CLK=1 and the potential of the second node B is low, the first capacitor C1 is charged, and the second switching transistor M2 and the sixth switching transistor M6 are both turned off. Although the gate of the third switching transistor M3 is connected to the input signal terminal Input, due to the bootstrap effect of the second capacitor C2, the first node A is kept at a high potential with the voltage V _A =V _Input -V _th (M3), so The third switching transistor M3 is turned off, so that the first node A is in a floating state. Since the potential of the first node A remains at a high potential, the fifth switching transistor M5 is turned on and provides the signal of the high potential first clock signal terminal CLK to the driving signal output terminal Output, so the potential of the driving signal output terminal Output is High potential, that is, the driving signal output terminal Output outputs a high potential driving signal. Due to the bootstrapping effect of the second capacitor C2, in order to keep the voltage difference between the first node A and the output terminal Output of the driving signal stable, the potential of the first node A is further pulled up, ensuring that the fifth switching transistor M5 is completely turned on. is turned on, so as to provide the signal of the high potential first clock signal terminal CLK to the driving signal output terminal Output. Since RST1=0, the first switching transistor M1 is turned off. Since CLKB=0, the seventh switching transistor M7 is turned off.

In the third stage T3, Input=0, RST1=0, CLK=1, CLKB=0.

Since Input=0, both the third switch transistor M3 and the fourth switch transistor M4 are turned off, so the first node A and the second node B are both in a floating state. Since the first node A is in a floating state, the bootstrap function of the second capacitor C2 can keep the voltage difference across it stable, so the first node A can be kept at a voltage V _A = V _Input -V _th (M3). high potential. Since the potential of the first node A remains at a high potential, the fifth switching transistor M5 is turned on and provides the signal of the high potential first clock signal terminal CLK to the driving signal output terminal Output, so the potential of the driving signal output terminal Output is High potential, that is, the driving signal output terminal Output outputs a high potential driving signal. Due to the bootstrapping effect of the second capacitor C2, in order to keep the voltage difference between the first node A and the output terminal Output of the driving signal stable, the potential of the first node A is further pulled up, ensuring that the fifth switching transistor M5 is completely turned on. is turned on, so as to provide the signal of the high potential first clock signal terminal CLK to the driving signal output terminal Output. Since the bootstrap function of the first capacitor C1 can keep the voltage difference between the two terminals stable, the potential of the second node B remains low. Since the potential of the second node B is low, both the second switch transistor M2 and the sixth switch transistor M6 are turned off. Since RST1=0, the first switching transistor M1 is turned off. Since CLKB=0, the seventh switching transistor M7 is turned off.

In the fourth stage T4, Input=0, RST1=1, CLK=0, CLKB=1.

Since Input=0, both the third switch transistor M3 and the fourth switch transistor M4 are turned off. Since RST1=1, the first switching transistor M1 is turned on. Since the first switch transistor M1 is turned on, the first node A and the second node B are turned on, so that the potential of the second node B is a high potential. Since the potential of the second node B is a high potential, the second switch transistor M2 is turned on and provides the signal of the low potential first reference signal terminal VSS1 to the first node A, and the gate of the second switch transistor M2 is connected to the The drains are connected to form a diode structure, so that the high potential of the first node A is discharged through the second switching transistor M2 forming a diode structure until the gate-source voltage V _gs (M2) of the second switching transistor M2 is equal to the second switching transistor M2 The threshold voltage V _th (M2), that is, when V _gs (M2)=V _th (M2), the second switching transistor M2 is turned off, so that both the first node A and the second node B are low with the voltage V _th (M2) potential. Since the potential of the first node A is low, the fifth switching transistor M5 is turned off. Since the potential of the second node B is low, both the second switch transistor M2 and the sixth switch transistor M6 are turned off. Since CLKB=1, the seventh switching transistor M7 is turned on and provides the signal of the low-potential second reference signal terminal VSS2 to the drive signal output terminal Output, so the potential of the drive signal output terminal Output is low potential, that is, the drive signal output The terminal Output outputs a driving signal of low potential. Since both the first node A and the second node B have a low potential of voltage V _th (M2), the voltage difference across the first capacitor C1 is V _th (M2) and the voltage difference across the second capacitor C2 is V _th (M2).

In the fifth stage T5, Input=0, RST1=0, CLK=1, CLKB=0.

Since Input=0, both the third switch transistor M3 and the fourth switch transistor M4 are turned off, so the first node A and the second node B are both in a floating state. Since the second node B is in a floating state, and CLK=1 and the bootstrap effect of the first capacitor C1, in order to keep the voltage difference between its two ends stable, the potential of the second node B is pulled up to have the voltage V _th (M2 )+V _comp is a high potential, so the potential of the second node B is a high potential. Since the potential of the second node B is a high potential, both the second switch transistor M2 and the sixth switch transistor M6 are turned on. Since the second switch transistor M2 is turned on and provides the signal of the low-potential first reference signal terminal VSS1 to the first node A, the first node A is at a low potential, and since the first node A is at a low potential, the fifth switch Transistor M5 is off. Since the sixth switching transistor M6 is turned on and provides the signal of the low-potential second reference signal terminal VSS2 to the drive signal output terminal Output, the potential of the drive signal output terminal Output is a low potential, that is, the drive signal output terminal Output outputs a low potential drive signal. Since RST1=0, the first switching transistor M1 is turned off. Since CLKB=0, the seventh switching transistor M7 is turned off.

In the sixth phase T6, Input=0, RST1=0, CLK=0, CLKB=1.

Since Input=0, both the third switch transistor M3 and the fourth switch transistor M4 are turned off, so the first node A and the second node B are both in a floating state. Since the second node B is in a floating state, and CLK=0 and the bootstrap effect of the first capacitor C1, in order to keep the voltage difference between its two ends stable, the potential of the second node B is low with the voltage V _th (M2) Therefore, the potential of the second node B is low, and both the second switch transistor M2 and the sixth switch transistor M6 are turned off. Since CLKB=1, the seventh switching transistor M7 is turned on and provides the signal of the low-potential second reference signal terminal VSS2 to the drive signal output terminal Output, so the potential of the drive signal output terminal Output is low potential, that is, the drive signal output The terminal Output outputs a driving signal of low potential. Since RST1=0, the first switching transistor M1 is turned off.

In the above shift register provided by the embodiment of the present invention, after the sixth stage T6, the working process of the fifth stage T5 and the sixth stage T6 is repeated until the next frame starts.

Embodiment two,

Taking the structure of the shift register shown in Figure 2b as an example to describe its working process, wherein, in the shift register shown in Figure 2b, all switching transistors are N-type switching transistors, and each N-type switching transistor is in the It is turned on under the action of high potential and cut off under the action of low potential; the potential of the first reference signal terminal VSS1 is low potential, and the corresponding input and output timing diagram is shown in Figure 3b. Specifically, the input and output shown in Figure 3b are selected There are six stages in the sequence diagram: the first stage T1, the second stage T2, the third stage T3, the fourth stage T4, the fifth stage T5 and the sixth stage T6.

In the first stage T1, Input=1, RST1=0, RST2=0, CLK=0, CLKB=1. Since RST2=0, the eighth switching transistor M8 is turned off. The rest of the specific working process is the same as the working process of the first stage T1 in the first embodiment, and will not be repeated here.

In the second phase T2, Input=1, RST1=0, RST2=0, CLK=1, CLKB=0. Since RST2=0, the eighth switching transistor M8 is turned off. The rest of the specific working process is the same as the working process of the second stage T2 in the first embodiment, and will not be repeated here.

In the third stage T3, Input=0, RST1=0, RST2=0, CLK=1, CLKB=0. Since RST2=0, the eighth switching transistor M8 is turned off. The rest of the specific working process is the same as that of the third stage T3 in the first embodiment, and will not be repeated here.

In the fourth stage T4, in the first half of the time period, Input=0, RST1=1, RST2=0, CLK=0, CLKB=1. Since RST2=0, the eighth switching transistor M8 is turned off. The rest of the specific working process is the same as that of the fourth stage T4 in the first embodiment, and will not be repeated here.

In the second half of the time period, Input=0, RST1=1, RST2=1, CLK=0, CLKB=1. Since RST2=1, the eighth switch transistor M8 is turned on and provides the signal of the low-potential second reference signal terminal VSS2 to the driving signal output terminal Output, further ensuring that the potential of the driving signal output terminal Output is low. The rest of the specific working process is the same as that of the fourth stage T4 in the first embodiment, and will not be repeated here.

In the fifth stage T5, in the first half of the time period, Input=0, RST1=0, RST2=1, CLK=1, CLKB=0. Since RST2=1, the eighth switch transistor M8 is turned on and provides the signal of the low-potential second reference signal terminal VSS2 to the driving signal output terminal Output, further ensuring that the potential of the driving signal output terminal Output is low. The rest of the specific working process is the same as that of the fifth stage T5 in the first embodiment, and will not be repeated here.

In the second half of the time period, Input=0, RST1=0, RST2=0, CLK=1, CLKB=0. Since RST2=0, the eighth switching transistor M8 is turned off. The rest of the specific working process is the same as that of the fifth stage T5 in the first embodiment, and will not be repeated here.

In the sixth phase T6, Input=0, RST1=0, RST2=0, CLK=0, CLKB=1. Since RST2=0, the eighth switching transistor M8 is turned off. The rest of the specific working process is the same as that of the sixth stage T6 in the first embodiment, and will not be repeated here.

In the above shift register provided by the embodiment of the present invention, after the sixth stage T6, the second half of the fifth stage T5 and the sixth stage T6 are repeatedly executed until the next frame starts.

In the above shift register provided by the embodiment of the present invention, in the fourth stage, since the second switch transistor M2 forming a diode structure can write the threshold voltage Vth(M2) of the second switch transistor M2 into the second node, thus In the fifth stage, after the potential of the second node is pulled up by the bootstrap function of the first capacitor, the voltage of the second node is also pulled up by the voltage V _comp , so that the voltage of the second node is: V _th (M2)+ V _comp , so that Vgs(M2) of the second switch transistor M2=V _comp , so that the second switch transistor can be kept in the on state all the time, so as to provide the signal of the first reference signal end with low potential to the first node, and keep the second switch transistor M2 in the on state. The potential of one node is a low potential, thereby reducing the output noise of the driving signal output end, avoiding abnormal display, and improving the display stability of the display device.

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, in the fourth stage of its working process, the voltage V _comp satisfies the formula: Where V _CLK represents the voltage amplitude of the first clock signal terminal, c1 represents the capacitance value of the first capacitor, Cpd=c1+Cgs(M1)+Cgs(M2)+Cgd(M2)+Cgd(M4)+Cgs(M6)+ Cgd(M6), Cgs(M1) represents the parasitic capacitance between the gate and the source of the first switching transistor, Cgs(M2) represents the parasitic capacitance between the gate and the source of the second switching transistor, Cgd(M2 ) represents the parasitic capacitance between the gate and the drain of the second switching transistor, Cgd(M4) represents the parasitic capacitance between the gate and the drain of the fourth switching transistor, Cgs(M6) represents the gate of the sixth switching transistor The parasitic capacitance between the electrode and the source, Cgd(M6) represents the parasitic capacitance between the gate and the drain of the sixth switching transistor.

Taking the specific structure of the shift register shown in FIG. 2b and the voltage step size of 2V as an example, the simulation simulates that the threshold voltage Vth(M2) of the second switching transistor M2 drifts to the right corresponding to the voltage of the second node during the working process. relation. The simulation result of the threshold voltage Vth( M2 ) of the second switching transistor M2 drifting to the right is shown in FIG. 4 a , where the abscissa represents voltage and the ordinate represents current. Wherein, S1, S2, S3, S4, S5, S6 and S7 respectively represent the simulation curves of the threshold voltage Vth(M2) of the second switching transistor M2 shifting to the right by 0V, 2V, 4V, 6V, 8V, 10V and 12V. The voltage simulation diagram of the first node and the second node corresponding to S1-S7 in FIG. 4a is shown in FIG. 4b, where the abscissa represents time and the ordinate represents voltage. Wherein, S0 represents the voltage of the first node when the threshold voltage Vth(M2) of the second switching transistor M2 shifts to the right by 0V, 2V, 4V, 6V, 8V, 10V and 12V. S1'-S7' respectively represent the voltages of the second node when the threshold voltage Vth(M2) of the second switch transistor M2 shifts to the right by 0V, 2V, 4V, 6V, 8V, 10V and 12V. From FIG. 4a and FIG. 4b, it can be seen that as the threshold voltage Vth(M2) of the second switching transistor M2 increases, the voltage of the second node also increases correspondingly, so that the threshold voltage of the second switching transistor M2 can be compensated Drift of Vth(M2).

Based on the same inventive concept, an embodiment of the present invention also provides a driving method for any of the above-mentioned shift registers provided by the present invention, as shown in FIG. 5 , including: the first stage, the second stage, the third stage, the first The fourth stage, the fifth stage and the sixth stage; among them,

S501. In the first stage, the input module provides the signal of the input signal terminal to the first node under the control of the input signal terminal, and provides the signal of the first reference signal terminal to the second node under the control of the input signal terminal; the first output module is Under the control of the signal of the first node, the signal of the first clock signal terminal is provided to the drive signal output terminal; the second output module provides the signal of the second reference signal terminal to the drive signal output terminal under the control of the second clock signal terminal;

S502. In the second stage, the first output module provides the signal of the first clock signal terminal to the drive signal output terminal under the control of the signal of the first node, and when the first node is in a floating state, keeps the first node and The voltage difference between the drive signal output terminals is stable; the input module provides the signal of the first reference signal terminal to the second node under the control of the input signal terminal;

S503. In the third stage, the first output module provides the signal of the first clock signal terminal to the drive signal output terminal under the control of the signal of the first node, and when the first node is in a floating state, keeps the first node and The voltage difference between the drive signal output terminals is stable; the voltage coupling module keeps the voltage difference between the second node and the first clock signal terminal stable when the second node is in a floating state;

S504. In the fourth stage, the threshold voltage writing module turns on the first node and the second node under the control of the first reset signal terminal, and provides the signal of the first reference signal terminal to the second node under the control of the signal of the second node A node; the second output module provides the signal of the second reference signal terminal to the driving signal output terminal under the control of the second clock signal terminal;

S505. In the fifth stage, the voltage coupling module keeps the voltage difference between the second node and the first clock signal terminal stable when the second node is in a floating state; the second output module is controlled by the signal of the second node providing the signal of the second reference signal terminal to the drive signal output terminal; the threshold voltage writing module provides the signal of the first reference signal terminal to the first node under the control of the signal of the second node;

S506. In the sixth stage, when the second node is in a floating state, the voltage coupling module keeps the voltage difference between the second node and the first clock signal terminal stable; the second output module will The signal at the second reference signal terminal is provided to the driving signal output terminal.

The above-mentioned driving method provided by the embodiment of the present invention can compensate the voltage of the second node, so as to ensure that the potential of the first node can be in a stable state of inactive potential after the shift register outputs the effective pulse signal of the driving signal, thereby reducing the driving force. The output noise at the signal output terminal can avoid display abnormalities.

Further, in the above driving method provided by the embodiment of the present invention, when each shift register also includes a potential stabilization module,

The fourth stage specifically includes: in the first half of the time period, the threshold voltage writing module turns on the first node and the second node under the control of the first reset signal terminal, and switches the signal of the first reference signal terminal under the control of the signal of the second node. Provided to the first node; the second output module provides the signal of the second reference signal terminal to the driving signal output terminal under the control of the second clock signal terminal;

In the second half of the time period, the threshold voltage writing module turns on the first node and the second node under the control of the first reset signal terminal, and provides the signal of the first reference signal terminal to the first node under the control of the signal of the second node ; The second output module provides the signal of the second reference signal terminal to the drive signal output terminal under the control of the second clock signal terminal; the potential stabilization module provides the signal of the second reference signal terminal to the drive signal output under the control of the second reset signal terminal end;

The fifth stage specifically includes: in the first half of the time period, when the second node is in a floating state, the voltage coupling module keeps the voltage difference between the second node and the first clock signal terminal stable; the signal of the second output module at the second node The signal of the second reference signal terminal is provided to the drive signal output terminal under the control of the second node; the threshold voltage writing module provides the signal of the first reference signal terminal to the first node under the control of the signal of the second node; the potential stabilization module is in the second Providing the signal of the second reference signal terminal to the drive signal output terminal under the control of the reset signal terminal;

In the second half of the time period, when the second node is in a floating state, the voltage coupling module keeps the voltage difference between the second node and the first clock signal terminal stable; The signals of the two reference signal terminals are provided to the drive signal output terminal; the threshold voltage writing module provides the signal of the first reference signal terminal to the first node under the control of the signal of the second node.

Based on the same inventive concept, an embodiment of the present invention also provides a gate drive circuit, as shown in FIG. 6 , including: cascaded N shift registers SR(1), SR (2), SR(3)...SR(n), SR(n-1), SR(n+1); wherein, N is an integer greater than or equal to 4;

The input signal terminal Input of the first-stage shift register SR (1) is connected to the first frame trigger signal terminal STV1;

The input signal terminal Input of the second stage shift register SR (2) is connected with the second frame trigger signal terminal STV2;

The input signal terminal Input of the shift register SR(n) of the nth stage is respectively connected with the drive signal output terminal Output of the shift register SR(n-2) of the n-2nd stage;

The first reset signal terminal RST1 of the n-2th stage shift register SR (n-2) is respectively connected with the drive signal output terminal Output of the n+1st stage shift register SR (n+1); wherein, n is greater than Or an integer equal to 3 and less than or equal to N-1.

Further, in specific implementation, in the above-mentioned driving method provided by the embodiment of the present invention, when each shift register also includes a potential stabilization module, the second reset signal terminal of the n-2th stage shift register is respectively connected to the nth The driving signal output terminals of the +2-stage shift register are connected.

Further, during specific implementation, in the above driving method provided by the embodiment of the present invention, the first reference signal terminal and the second reference signal terminal are the same signal terminal.

Specifically, the specific structure of each shift register in the above-mentioned gate driving circuit is the same in function and structure as the above-mentioned shift register in the present invention, and repeated descriptions will not be repeated here. The gate driving circuit can be applied in a liquid crystal display panel, and can also be applied in an organic electroluminescent display panel, which is not limited here.

Specifically, in the above-mentioned gate drive circuit provided by the embodiment of the present invention, as shown in FIG. 6, the first clock signal terminal CLK of the 6k+1st stage shift register is connected to the second The clock signal terminals CLKB are all connected to the same clock terminal, that is, the first clock terminal ck1; the first clock signal terminal CLK of the 6k+2 shift register and the second clock signal terminal CLKB of the 6k+5 shift register are all connected to each other. The same clock terminal is connected to the second clock terminal ck2; the first clock signal terminal CLK of the 6k+3 stage shift register and the second clock signal terminal CLKB of the 6k+6 stage shift register are all connected to the same clock terminal that is the third The clock terminal ck3 is connected; the first clock signal terminal CLK of the 6k+4th stage shift register and the second clock signal terminal CLKB of the 6k+1 stage shift register are all connected to the same clock terminal, that is, the fourth clock terminal ck4; The first clock signal terminal CLK of the 6k+5-level shift register and the second clock signal terminal CLKB of the 6k+2-level shift register are all connected to the same clock terminal, that is, the fifth clock terminal ck5; the 6k+6-level shift register Both the first clock signal terminal CLK of the register and the second clock signal terminal CLKB of the 6k+3 shift register are connected to the same clock terminal, namely the sixth clock terminal ck6; where k is an integer greater than or equal to 0.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, including any one of the above-mentioned gate driving circuits provided by the embodiments of the present invention. The display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. The other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be regarded as limitations on the present invention. For the implementation of the display device, reference may be made to the above embodiments of the shift register, and repeated descriptions will not be repeated.

The shift register, its driving method, gate driving circuit and display device provided by the embodiments of the present invention include: an input module, a voltage coupling module, a threshold voltage writing module, a first output module, and a second output module; wherein, the input The module is used to provide the signal of the input signal terminal to the first node under the control of the input signal terminal, and to provide the signal of the first reference signal terminal to the second node under the control of the input signal terminal; the voltage coupling module is used for floating the second node When in the connected state, keep the voltage difference between the second node and the first clock signal terminal stable; the threshold voltage writing module is used to conduct the first node and the second node under the control of the first reset signal terminal, and at the second Under the control of the signal of the node, the signal of the first reference signal terminal is provided to the first node; the first output module is used for providing the signal of the first clock signal terminal to the driving signal output terminal under the control of the signal of the first node, and in When the first node is in a floating state, keep the voltage difference between the first node and the output terminal of the driving signal stable; the second output module is used to provide the signal of the second reference signal terminal to the driver under the control of the signal of the second node The signal output terminal, and the signal of the second reference signal terminal is provided to the driving signal output terminal under the control of the second clock signal terminal. Therefore, through the mutual cooperation of the above four modules, the voltage of the second node can be compensated to ensure that after the shift register outputs the effective pulse signal of the drive signal, the potential of the first node can be in a stable state of inactive potential, thereby The output noise at the drive signal output terminal is reduced, thereby avoiding display abnormalities.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (11)

1. A shift register, comprising: the device comprises an input module, a voltage coupling module, a threshold voltage writing module, a first output module and a second output module; wherein,

the input module is respectively connected with an input signal end, a first reference signal end, a first node and a second node; the input module is used for providing a signal of the input signal terminal to the first node under the control of the input signal terminal and providing a signal of the first reference signal terminal to the second node under the control of the input signal terminal;

the voltage coupling module is respectively connected with a first clock signal end and the second node; the voltage coupling module is used for keeping the voltage difference between the second node and the first clock signal end stable when the second node is in a floating state;

the threshold voltage writing module is respectively connected with a first reset signal end, the first reference signal end, the first node and the second node; the threshold voltage writing module is used for conducting the first node and the second node under the control of the first reset signal terminal, and providing a signal of the first reference signal terminal to the first node under the control of a signal of the second node;

the first output module is respectively connected with the first clock signal end, the first node and the drive signal output end of the shift register; the first output module is used for providing a signal of the first clock signal end to the driving signal output end under the control of a signal of the first node, and keeping a voltage difference between the first node and the driving signal output end stable when the first node is in a floating state;

the second output module is respectively connected with a second clock signal end, a second reference signal end, the second node and the driving signal output end; the second output module is configured to provide the signal of the second reference signal terminal to the driving signal output terminal under the control of the signal of the second node, and provide the signal of the second reference signal terminal to the driving signal output terminal under the control of the second clock signal terminal.

2. The shift register of claim 1, wherein the voltage coupling module comprises: a first capacitor; wherein,

and the first end of the first capacitor is connected with the second node, and the second end of the first capacitor is connected with the first clock signal end.

3. The shift register of claim 1, wherein the threshold voltage write module comprises: a first switching transistor and a second switching transistor; wherein,

the grid electrode of the first switch transistor is connected with the first reset signal end, the source electrode of the first switch transistor is connected with the first node, and the drain electrode of the first switch transistor is connected with the second node;

and the grid electrode of the second switch transistor is connected with the second node, the source electrode of the second switch transistor is connected with the first reference signal end, and the drain electrode of the second switch transistor is connected with the first node.

4. The shift register of claim 1, wherein the input module comprises: a third switching transistor and a fourth switching transistor; wherein,

the grid electrode and the drain electrode of the third switching transistor are both connected with the input signal end, and the source electrode of the third switching transistor is connected with the first node;

and the grid electrode of the fourth switching transistor is connected with the input signal end, the source electrode of the fourth switching transistor is connected with the first reference signal end, and the drain electrode of the fourth switching transistor is connected with the second node.

5. The shift register of claim 1, wherein the first output module comprises: a fifth switching transistor and a second capacitor; wherein,

a grid electrode of the fifth switching transistor is connected with the first node, a source electrode of the fifth switching transistor is connected with the first clock signal end, and a drain electrode of the fifth switching transistor is connected with the driving signal output end;

and the first end of the second capacitor is connected with the first node, and the second end of the second capacitor is connected with the driving signal output end.

6. The shift register of claim 1, wherein the second output module comprises: a sixth switching transistor and a seventh switching transistor; wherein,

a gate of the sixth switching transistor is connected to the second node, a source thereof is connected to the second reference signal terminal, and a drain thereof is connected to the driving signal output terminal;

and the grid electrode of the seventh switching transistor is connected with the second clock signal end, the source electrode of the seventh switching transistor is connected with the second reference signal end, and the drain electrode of the seventh switching transistor is connected with the driving signal output end.

7. The shift register of any one of claims 1-6, further comprising: a potential stabilization module; wherein,

the potential stabilizing module is respectively connected with a second reset signal end, the second reference signal end and the driving signal output end; the potential stabilizing module is used for providing the signal of the second reference signal end to the driving signal output end under the control of the second reset signal end.

8. The shift register of claim 7, wherein the potential stabilization module comprises: an eighth switching transistor; wherein,

and the grid electrode of the eighth switching transistor is connected with the second reset signal end, the source electrode of the eighth switching transistor is connected with the second reference signal end, and the drain electrode of the eighth switching transistor is connected with the driving signal output end.

9. A gate drive circuit comprising a cascade of N shift registers according to any one of claims 1 to 8; wherein N is an integer greater than or equal to 4;

the input signal end of the 1 st-stage shift register is connected with the first frame trigger signal end;

the input signal end of the 2 nd-stage shift register is connected with the second frame trigger signal end;

the input signal end of the nth stage shift register is respectively connected with the driving signal output end of the nth-2 stage shift register;

the first reset signal end of the (n-2) th stage shift register is respectively connected with the driving signal output end of the (n +1) th stage shift register; wherein N is an integer greater than or equal to 3 and less than or equal to N-1.

10. A display device comprising the gate driver circuit according to claim 9.

11. A driving method of a shift register according to any one of claims 1 to 8, comprising: a first stage, a second stage, a third stage, a fourth stage, a fifth stage and a sixth stage; wherein,

in the first phase, the input module provides the signal of the input signal terminal to the first node under the control of the input signal terminal, and provides the signal of the first reference signal terminal to the second node under the control of the input signal terminal; the first output module provides a signal of the first clock signal end to the driving signal output end under the control of the signal of the first node; the second output module provides the signal of the second reference signal end to the driving signal output end under the control of the second clock signal end;

in the second stage, the first output module provides the signal of the first clock signal end to the driving signal output end under the control of the signal of the first node, and keeps the voltage difference between the first node and the driving signal output end stable when the first node is in a floating state; the input module provides the signal of the first reference signal terminal to the second node under the control of the input signal terminal;

in the third phase, the first output module provides the signal of the first clock signal end to the driving signal output end under the control of the signal of the first node, and keeps the voltage difference between the first node and the driving signal output end stable when the first node is in a floating state; when the second node is in a floating state, the voltage coupling module keeps the voltage difference between the second node and the first clock signal end stable;

in the fourth phase, the threshold voltage writing module turns on the first node and the second node under the control of the first reset signal terminal, and provides the signal of the first reference signal terminal to the first node under the control of the signal of the second node; the second output module provides the signal of the second reference signal end to the driving signal output end under the control of the second clock signal end;

in the fifth stage, when the second node is in a floating state, the voltage coupling module keeps a voltage difference between the second node and the first clock signal terminal stable; the second output module provides the signal of the second reference signal end to the driving signal output end under the control of the signal of the second node; the threshold voltage writing module provides a signal of the first reference signal terminal to the first node under the control of a signal of the second node;

in the sixth stage, when the second node is in a floating state, the voltage coupling module keeps a voltage difference between the second node and the first clock signal terminal stable; the second output module provides the signal of the second reference signal end to the driving signal output end under the control of the second clock signal end.