CN106531828B - Silicon substrate high-performance β spokes volt battery and preparation method thereof - Google Patents

Abstract

The present invention proposes a kind of silicon substrate high-performance β spokes volt battery, and the silicon substrate high-performance β spokes volt battery is made up of N-type silicon epitaxy layer, p-type protection ring, p-type active area, N-type silicon substrate, silicon dioxide layer, silicon nitride layer, electrode, electrode layer and Pyrex layer；The invention also provides the preparation method that a kind of silicon substrate high-performance β spokes lie prostrate battery；The method have the benefit that：There is provided a kind of silicon substrate high-performance β spokes volt battery and preparation method thereof, compared to prior art, spoke volt battery has higher power output and capability of resistance to radiation.

Description

Silicon-based high-performance β-voltaic battery and its manufacturing method

technical field

The invention relates to a voltaic battery, in particular to a silicon-based high-performance β voltaic battery and a manufacturing method thereof.

Background technique

Since the radiovoltaic isotope battery technology is still in the development stage, the performance of the existing radiovoltaic isotope batteries is still poor, especially the problem of low output power.

Contents of the invention

Aiming at the problems in the background technology, the present invention proposes a silicon-based high-performance β-voltaic battery, the innovation of which is: the silicon-based high-performance β-voltaic battery consists of an N-type silicon epitaxial layer, a P-type Active region, N-type silicon substrate, silicon dioxide layer, silicon nitride layer, electrode, electrode layer and borosilicate glass layer;

The N-type silicon epitaxial layer is formed on the upper surface of the N-type silicon substrate, the P-type guard ring and the P-type active region are formed in the upper surface layer of the N-type silicon epitaxial layer, and the P-type guard ring surrounds On the periphery of the P-type active area, the inner wall of the P-type guard ring is in contact with the outer wall of the P-type active area; the borosilicate glass layer is arranged on the upper end surface of the N-type silicon epitaxial layer, and the borosilicate glass layer and the P-type The circumferential profile of the active region is the same; the silicon dioxide layer is arranged on the upper end surface of the N-type silicon epitaxial layer, and the silicon dioxide layer covers the area other than the borosilicate glass layer on the upper end surface of the N-type silicon epitaxial layer; the silicon nitride layer is The layer covers the surface of the silicon dioxide layer and the borosilicate glass layer; electrode holes are arranged in the structure directly above the P-type protective ring, the electrodes are arranged in the electrode holes, and the electrode layer is arranged on the lower end surface of the N-type silicon substrate .

The biggest difference between the present invention and the prior art is that in the prior art, only a silicon dioxide film or a silicon nitride film is used to cover the top of the P-type active region, and the output power of the β voltaic cell with this structure is relatively low. Low, in order to improve product performance, the inventor conducted a large number of experiments. During the experiment, the inventor found that after changing a single silicon dioxide film or silicon nitride film into a composite layer of borosilicate glass and silicon nitride, the β radiation The output power and radiation resistance of the battery have been significantly improved. The performance comparison of the battery before and after improvement is shown in the table below:

It can be seen from the above table that after adopting the scheme of the present invention, the output open-circuit voltage and short-circuit current of a single battery are both increased by 20% compared with those before the improvement; the output power of the battery array connected in parallel after four batteries is increased by nearly 40%; After irradiation with a radiation source, the attenuation of the output short-circuit current of the battery is reduced from 42% before improvement to 8%, which greatly improves the radiation resistance of the battery.

Based on the foregoing scheme, the present invention also proposes a method for manufacturing a silicon-based high-performance β-voltaic battery. The structure of the silicon-based high-performance β-voltaic battery is as described above; the specific steps of the manufacturing method are as follows:

1) making an N-type silicon substrate;

2) using an epitaxial growth process to grow an N-type silicon epitaxial layer on the upper surface of the N-type silicon substrate;

3) A high-temperature oxidation process is used to grow a silicon dioxide layer on the surface of the device;

4) photoetching out guard ring doped regions at corresponding positions on the silicon dioxide layer, and then removing the silicon dioxide layer within the scope of the guard ring doped regions;

5) Using a high-temperature boron diffusion process, perform deep-junction boron doping on the doped region of the guard ring to obtain a P-type guard ring;

6) Photoetching an active doped region at a corresponding position on the silicon dioxide layer, and then removing the silicon dioxide layer within the scope of the active doped region;

7) Using a high-temperature boron diffusion process to perform shallow-junction boron doping on the active doped region to obtain a P-type active region and a borosilicate glass layer;

8) Deposit a silicon nitride layer on the surface of the device by using a high-temperature LPCVD process;

9) making electrodes at corresponding positions on the device;

10) Thinning the lower end surface of the N-type silicon substrate, and making an electrode layer on the lower end surface of the N-type silicon substrate.

Preferably, the resistivity of the N-type silicon epitaxial layer is 0.1-10 Ω·cm, and the thickness is 20-50 μm; the electrode adopts a Cr/Au double-layer metal film; the electrode layer adopts a Cr/Au double-layer metal film ; the doping concentration of the P-type guard ring is 5×10 ¹⁹ /cm ³ to 1×10 ²⁰ /cm ³ , and the junction depth is 1.0-1.5 μm; the doping concentration of the P-type active region is 1-1 5×10 ¹⁹ /cm ³ , the junction depth is 0.5-1.0 μm; the thickness of the borosilicate glass layer is 10-30 nm; the thickness of the silicon nitride layer is 20-30 nm.

The beneficial technical effect of the present invention is to provide a silicon-based high-performance β voltaic battery and its manufacturing method. Compared with the prior art, the voltaic battery has higher output power and radiation resistance.

Description of drawings

Fig. 1, the sectional structure schematic diagram of the present invention;

The names corresponding to each mark in the figure are: N-type silicon epitaxial layer 1, P-type guard ring 2, P-type active region 3, N-type silicon substrate 4, silicon dioxide layer 5, silicon nitride layer 6, Electrode 7 , electrode layer 8 , borosilicate glass layer 9 .

detailed description

A silicon-based high-performance β-voltaic battery, the innovation of which is that the silicon-based high-performance β-voltaic battery consists of an N-type silicon epitaxial layer 1, a P-type guard ring 2, a P-type active region 3, and an N-type silicon lining Bottom 4, silicon dioxide layer 5, silicon nitride layer 6, electrode 7, electrode layer 8 and borosilicate glass layer 9;

The N-type silicon epitaxial layer 1 is formed on the upper end surface of the N-type silicon substrate 4, and the P-type guard ring 2 and the P-type active region 3 are both formed in the upper surface layer of the N-type silicon epitaxial layer 1, and the P The type guard ring 2 surrounds the circumferential periphery of the P-type active region 3, and the inner wall of the P-type guard ring 2 is in contact with the outer wall of the P-type active region 3; the borosilicate glass layer 9 is arranged on the N-type silicon epitaxial layer 1 On the upper end face, the borosilicate glass layer 9 has the same circumferential profile as the P-type active region 3; the silicon dioxide layer 5 is arranged on the upper end face of the N-type silicon epitaxial layer 1, and the silicon dioxide layer 5 expands the N-type silicon epitaxial The upper end surface of the layer 1 is covered by the area other than the borosilicate glass layer 9; the silicon nitride layer 6 is covered on the surface of the silicon dioxide layer 5 and the borosilicate glass layer 9; the structure directly above the P-type protective ring 2 is provided with an electrode The electrode 7 is arranged in the electrode hole, and the electrode layer 8 is arranged on the lower end surface of the N-type silicon substrate 4 . Further, the resistivity of the N-type silicon epitaxial layer 1 is 0.1-10 Ω·cm, and the thickness is 20-50 μm; the electrode 7 is a Cr/Au double-layer metal film; the electrode layer 8 is a Cr/Au double-layer metal film. layer metal film; the doping concentration of the P-type guard ring 2 is 5×10 ¹⁹ /cm ³ to 1×10 ²⁰ /cm ³ , and the junction depth is 1.0-1.5 μm; the doping concentration of the P-type active region 3 The impurity concentration is 1-5×10 ¹⁹ /cm ³ , the junction depth is 0.5-1.0 μm; the thickness of the borosilicate glass layer 9 is 10-30 nm; the thickness of the silicon nitride layer 6 is 20-30 nm.

A method for manufacturing a silicon-based high-performance β-voltaic battery, the silicon-based high-performance β-voltaic battery consists of an N-type silicon epitaxial layer 1, a P-type guard ring 2, a P-type active region 3, and an N-type silicon substrate 4. Composition of silicon dioxide layer 5, silicon nitride layer 6, electrode 7, electrode layer 8 and borosilicate glass layer 9;

The N-type silicon epitaxial layer 1 is formed on the upper end surface of the N-type silicon substrate 4, and the P-type guard ring 2 and the P-type active region 3 are both formed in the upper surface layer of the N-type silicon epitaxial layer 1, and the P The type guard ring 2 surrounds the circumferential periphery of the P-type active region 3, and the inner wall of the P-type guard ring 2 is in contact with the outer wall of the P-type active region 3; the borosilicate glass layer 9 is arranged on the N-type silicon epitaxial layer 1 On the upper end face, the borosilicate glass layer 9 has the same circumferential profile as the P-type active region 3; the silicon dioxide layer 5 is arranged on the upper end face of the N-type silicon epitaxial layer 1, and the silicon dioxide layer 5 expands the N-type silicon epitaxial The upper end surface of the layer 1 is covered by the area other than the borosilicate glass layer 9; the silicon nitride layer 6 is covered on the surface of the silicon dioxide layer 5 and the borosilicate glass layer 9; the structure directly above the P-type protective ring 2 is provided with an electrode hole, the electrode 7 is arranged in the electrode hole, and the electrode layer 8 is arranged on the lower end surface of the N-type silicon substrate 4;

The steps of the preparation method are as follows:

1) making an N-type silicon substrate 4;

2) Using an epitaxial growth process to grow an N-type silicon epitaxial layer 1 on the upper surface of the N-type silicon substrate 4;

3) using a high temperature oxidation process to grow a silicon dioxide layer 5 on the surface of the device;

4) photoetching out guard ring doped regions at corresponding positions on the silicon dioxide layer 5, and then removing the silicon dioxide layer 5 within the range of the guard ring doped regions;

5) Using a high-temperature boron diffusion process to perform deep-junction boron doping on the doped region of the guard ring to obtain a P-type guard ring 2;

6) Photoetching an active doped region at a corresponding position on the silicon dioxide layer 5, and then removing the silicon dioxide layer 5 within the scope of the active doped region;

7) Using a high-temperature boron diffusion process, performing shallow junction boron doping on the active doped region to obtain a P-type active region 3 and a borosilicate glass layer 9;

8) Depositing a silicon nitride layer 6 on the surface of the device by using a high-temperature LPCVD process;

9) making electrodes 7 at corresponding positions on the device;

10) The lower end surface of the N-type silicon substrate 4 is thinned, and the electrode layer 8 is fabricated on the lower end surface of the N-type silicon substrate 4 .

Further, the resistivity of the N-type silicon epitaxial layer 1 is 0.1-10 Ω·cm, and the thickness is 20-50 μm; the electrode 7 is a Cr/Au double-layer metal film; the electrode layer 8 is a Cr/Au double-layer metal film. layer metal film; the doping concentration of the P-type guard ring 2 is 5×10 ¹⁹ /cm ³ to 1×10 ²⁰ /cm ³ , and the junction depth is 1.0-1.5 μm; the doping concentration of the P-type active region 3 The impurity concentration is 1-5×10 ¹⁹ /cm ³ , the junction depth is 0.5-1.0 μm; the thickness of the borosilicate glass layer 9 is 10-30 nm; the thickness of the silicon nitride layer 6 is 20-30 nm.

Claims (4)

1. a kind of silicon substrate high-performance β spokes lie prostrate battery, it is characterised in that：The silicon substrate high-performance β spokes lie prostrate battery by N-type silicon epitaxy layer (1), p-type protection ring (2), p-type active area (3), N-type silicon substrate (4), silicon dioxide layer (5), silicon nitride layer (6), electrode (7), Electrode layer (8) and Pyrex layer (9) composition；

The N-type silicon epitaxy layer (1) is formed on the upper surface of N-type silicon substrate (4), and the p-type protection ring (2) and p-type are active Area (3) is both formed in the top layer of N-type silicon epitaxy layer (1) upper end, and p-type protection ring (2) is looped around the circumference of p-type active area (3) Periphery, the wall contacts of p-type protection ring (2) inwall and p-type active area (3)；The Pyrex layer (9) is arranged on outside N-type silicon On the upper surface for prolonging layer (1), Pyrex layer (9) is identical with the circumferential profile of p-type active area (3)；Silicon dioxide layer (5) is set On the upper surface of N-type silicon epitaxy layer (1), silicon dioxide layer (5) by N-type silicon epitaxy layer (1) upper surface Pyrex layer (9) Region overlay in addition；Silicon nitride layer (6) is covered in the surface of silicon dioxide layer (5) and Pyrex layer (9)；P-type protection ring (2) electrode hole is provided with the structure directly over, electrode (7) is arranged in electrode hole, electrode layer (8) is arranged on N-type silicon lining On the lower surface at bottom (4).

2. silicon substrate high-performance β spokes according to claim 1 lie prostrate battery, it is characterised in that：The N-type silicon epitaxy layer (1) Resistivity is that 0.1~10 Ω cm, thickness are 20~50 μm；The electrode (7) uses Cr/Au bi-layer metal films；The electrode Layer (8) uses Cr/Au bi-layer metal films；The doping concentration of the p-type protection ring (2) is 5 × 10¹⁹/cm³~1 × 10²⁰/cm³、 Junction depth is 1.0~1.5 μm；The doping concentration of the p-type active area (3) is 1~5 × 10¹⁹/cm³, junction depth be 0.5~1.0 μm； The thickness of the Pyrex layer (9) is 10~30nm；The thickness of the silicon nitride layer (6) is 20~30nm.

3. a kind of preparation method that silicon substrate high-performance β spokes lie prostrate battery, the silicon substrate high-performance β spokes lie prostrate battery by N-type silicon epitaxy layer (1), p-type protection ring (2), p-type active area (3), N-type silicon substrate (4), silicon dioxide layer (5), silicon nitride layer (6), electrode (7), Electrode layer (8) and Pyrex layer (9) composition；

The N-type silicon epitaxy layer (1) is formed on the upper surface of N-type silicon substrate (4), and the p-type protection ring (2) and p-type are active Area (3) is both formed in the top layer of N-type silicon epitaxy layer (1) upper end, and p-type protection ring (2) is looped around the circumference of p-type active area (3) Periphery, the wall contacts of p-type protection ring (2) inwall and p-type active area (3)；The Pyrex layer (9) is arranged on outside N-type silicon On the upper surface for prolonging layer (1), Pyrex layer (9) is identical with the circumferential profile of p-type active area (3)；Silicon dioxide layer (5) is set On the upper surface of N-type silicon epitaxy layer (1), silicon dioxide layer (5) by N-type silicon epitaxy layer (1) upper surface Pyrex layer (9) Region overlay in addition；Silicon nitride layer (6) is covered in the surface of silicon dioxide layer (5) and Pyrex layer (9)；P-type protection ring (2) electrode hole is provided with the structure directly over, electrode (7) is arranged in electrode hole, electrode layer (8) is arranged on N-type silicon lining On the lower surface at bottom (4)；

It is characterized in that：The step of preparation method, is as follows：

1) N-type silicon substrate (4) is made；

2) epitaxial growth technology is used, N-type silicon epitaxy layer (1) is grown on the upper surface of N-type silicon substrate (4)；

3) high temperature oxidation process is used, in N-type silicon epitaxy layer (1) superficial growth silicon dioxide layer (5)；

4) relevant position in silicon dioxide layer (5) makes protection ring doped region by lithography, then by the range of protection ring doped region Silicon dioxide layer (5) remove；

5) high temperature boron diffusion technique is used, deep knot boron doping is carried out to protection ring doped region, p-type protection ring (2) is obtained；

6) relevant position in silicon dioxide layer (5) has made source dopant region by lithography, then will have two in the range of source dopant region Silicon oxide layer (5) removes；

7) high temperature boron diffusion technique is used, to there is source dopant region to carry out shallow junction boron doping, p-type active area (3) and borosilicate glass is obtained Glass layer (9)；

8) high temperature LPCVD techniques are used, in device surface deposit silicon nitride layer (6)；

9) relevant position on device makes electrode (7)；

10) lower surface of N-type silicon substrate (4) is thinned, electrode layer (8) is made on the lower surface of N-type silicon substrate (4).

4. the preparation method that silicon substrate high-performance β spokes according to claim 3 lie prostrate battery, it is characterised in that：Outside the N-type silicon The resistivity for prolonging layer (1) is that 0.1~10 Ω cm, thickness are 20~50 μm；The electrode (7) uses Cr/Au bi-layer metal films； The electrode layer (8) uses Cr/Au bi-layer metal films；The doping concentration of the p-type protection ring (2) is 5 × 10¹⁹/cm³~1 × 10²⁰/cm³, junction depth be 1.0~1.5 μm；The doping concentration of the p-type active area (3) is 1~5 × 10¹⁹/cm³, junction depth be 0.5 ~1.0 μm；The thickness of the Pyrex layer (9) is 10~30nm；The thickness of the silicon nitride layer (6) is 20~30nm.