CN106646204A - FPGA storage resource testing system, method and device - Google Patents

Abstract

The invention relates to an FPGA storage resource testing system, method and device. The system includes a clock management module, a data excitation module, a cross-clock domain data transmission module, a data comparison module, and a result display module; the clock management module is used to provide a first clock signal to the data excitation module and the result display module, And the second clock signal is provided to the storage resource to be tested in the data comparison module and the FPGA chip; the clock frequency of the second clock signal is higher than the clock frequency of the first clock signal; the cross-clock domain data transmission The module is used to implement data transmission between the clock domain of the first clock signal and the clock domain of the second clock signal. The invention can improve the test sequence convergence characteristics.

Description

FPGA storage resource testing system, method and device

technical field

The present invention relates to the technical field of programmable logic array (FPGA), in particular to an FPGA storage resource testing system, method and device.

Background technique

Due to its programmable, flexible and high throughput characteristics, FPGA is widely used in the fields of digital signal acquisition, compression, transmission and processing. In order to verify whether the FPGA meets the expected technical indicators, it is necessary to test the FPGA device. According to the different test purposes, it can be divided into standard test and high touch test. The standard test is to verify the compliance of the FPGA device with the technical indicators, and the high touch test is to verify the margin of the FPGA device exceeding the expected technical indicators, which reflects the Actual performance of FPGA devices.

When the traditional method is used to test the on-chip storage resources of the FPGA device, the input stimulus module, the module to be tested and the output comparison module are involved. In the test of high-speed FPGA devices, in order to ensure that the timing of the test system can be Interaction is particularly important. However, for high-speed FPGA devices, when the speed of the on-chip memory resources of the FPGA to be tested is getting higher and higher, other resources except the memory resource module to be tested limit the improvement of the test speed, so timing convergence is difficult to guarantee, the limit The speed test is difficult to achieve, and it is difficult to guarantee the test quality.

Contents of the invention

Based on this, the embodiments of the present invention provide an FPGA storage resource testing system, method and device, which can improve the test timing convergence characteristics.

The present invention provides a kind of FPGA storage resource testing system on the one hand, comprises:

Clock management module, data excitation module, cross-clock domain data transmission module, data comparison module and result display module;

The clock management module is used to provide the first clock signal to the data excitation module and the result display module, and to provide the second clock signal to the storage resources to be tested in the data comparison module and the FPGA chip; the second clock the clock frequency of the signal is higher than the clock frequency of the first clock signal;

The data excitation module is used to generate random data, and cache the random data to the cross-clock domain data transmission module;

The storage resource to be tested reads the random data from the cross-clock domain data transmission module, and performs a write operation according to the read random data;

The data comparison module is used to read the random data from the cross-clock domain data transmission module, and read the data written into the storage resource to be tested, and compare the read write data with the read random data comparing the data, and judging whether the read-write test of the storage resource to be tested under the second clock signal is qualified according to the comparison result;

The result display module is used to display the read and write test results of the storage resource to be tested.

Another aspect of the present invention provides a method for testing FPGA storage resources, comprising:

Provide the first clock signal to the preset data excitation module, and provide the second clock signal to the memory resource to be tested in the FPGA chip simultaneously; The clock frequency of the second clock signal is higher than the clock frequency of the first clock signal;

Read the random data generated by the data excitation module under the first clock signal under the second clock signal, and read the storage resource to be tested according to the random data generated by the data excitation module under the second clock signal Write data for write operations;

Comparing the read write data with the read random data, and judging whether the read/write test of the storage resource to be tested under the second clock signal is qualified according to the comparison result.

Another aspect of the present invention provides a kind of FPGA storage resource testing device, comprising:

The clock control unit is used to provide the first clock signal to the preset data excitation module, and simultaneously provide the second clock signal to the storage resource to be tested in the FPGA chip; the clock frequency of the second clock signal is higher than that of the first clock signal. the clock frequency of the clock signal;

The data acquisition unit is configured to read the random data generated by the data excitation module under the first clock signal under the second clock signal, and read the storage resource to be tested according to the data excitation under the second clock signal. The random data generated by the module is the write data for the write operation;

The judging unit is configured to compare the read write data with the read random data, and judge according to the comparison result whether the read/write test of the storage resource to be tested is qualified under the second clock signal.

Based on the FPGA storage resource testing system, method and device provided in the foregoing embodiments, the first clock signal is provided to the data excitation module and the result display module, and the first clock signal is provided to the storage resource to be tested in the data comparison module and the FPGA chip. Two clock signals; the clock frequency of the second clock signal is higher than the clock frequency of the first clock signal; the cross-clock domain data transmission module is used to realize the clock domain of the first clock signal and the second clock signal Data transfers in the clock domain. In this way, the impact of other resources on the speed of the storage resource module to be tested can be reduced, and the test timing convergence characteristic can be improved.

Description of drawings

Fig. 1 is the schematic structural diagram of the FPGA storage resource test system of an embodiment;

Fig. 2 is the schematic structural diagram of the FPGA storage resource testing system of another embodiment;

Fig. 3 is the schematic structural diagram of the FPGA storage resource testing system of another embodiment;

Fig. 4 is the schematic flowchart of the FPGA storage resource test method of an embodiment;

FIG. 5 is a schematic structural diagram of an FPGA storage resource testing device according to an embodiment.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

Fig. 1 is the schematic structural diagram of the FPGA storage resource test system of an embodiment; As shown in Figure 1, the FPGA storage resource test system in the present embodiment comprises: clock management module, data excitation module, cross-clock domain data transmission module , a data comparison module and a result display module. Each module and the test principle based on the system are described as follows.

Wherein, the clock management module is used to provide the first clock signal CLK1 to the data excitation module and the result display module, and to provide the second clock signal CLK2 to the storage resources to be tested in the data comparison module and the FPGA chip; The clock frequency of the second clock signal CLK2 is higher than the clock frequency of the first clock signal CLK1. In practical applications, CLK1 can be at the same frequency as the external input clock signal, and CLK2 is realized by frequency doubling technology. The low-frequency clock domain is used to drive the data excitation module and the result display module, and the high-frequency clock domain is used to drive the storage resources to be tested and the data comparison module. The purpose is to ensure that the data excitation module has better performance with a lower clock frequency. Timing Closure Features.

The test principle based on the above system is: the data stimulation module is used to generate random data, and buffer the random data to the cross-clock domain data transmission module. The storage resource to be tested reads the random data from the cross-clock domain data transmission module, and performs a write operation according to the read random data; the data comparison module is used to transfer data from the cross-clock domain data transmission module Read the random data, and read the data written into the storage resource to be tested, compare the read write data with the read random data, and judge according to the comparison result that the storage resource to be tested is in the Whether the read-write test under the second clock signal is qualified, output the read-write test result to the result display module; the result display module is used to display the read-write test result of the storage resource to be tested.

Wherein, the cross-clock domain data transmission module is used to realize data transmission between the clock domain of the first clock signal and the clock domain of the second clock signal; in a preferred embodiment, the cross-clock domain data transmission module adopts dual-port RAM (Random Access Memory) or FIFO (First-Input-First-Output) memory implementation. In the actual test, the on-chip storage resources of the FPGA device can also be used like the storage resources to be tested.

In a preferred embodiment, in the data comparison module, the read write data is compared with the read random data, and according to the comparison result, it is judged whether the storage resource to be tested is read or not under the second clock signal. The implementation of whether the write test is qualified can be: if the data read from the storage resource to be tested this time is consistent with the random data read from the cross-clock domain data transmission module this time, then it is judged that the The current reading and writing test of the storage resource to be tested passes; otherwise, it is determined that the current reading and writing test of the storage resource to be tested fails.

In a preferred embodiment, the storage resource to be tested can be configured as RAM, FIFO memory, shift register, etc. in the FPGA device chip.

In a preferred embodiment, as shown in FIG. 2 , the FPGA storage resource testing system includes at least two groups of data stimulation modules, cross-clock domain data transmission modules and data comparison modules. The at least two groups of data excitation modules, the cross-clock domain data transmission module and the data comparison module all output read and write test results to the result display module. In addition, the at least two groups of data excitation modules, cross-clock domain data transmission modules and data comparison modules are in one-to-one correspondence with at least two storage resources to be tested. Therefore, by realizing the test on a large-scale storage resource to be tested, the test efficiency is high.

Based on the FPGA storage resource testing system provided by the foregoing embodiments, the clock management module is used to provide the first clock signal to the data excitation module and the result display module, and to provide the storage resource to be tested in the data comparison module and the FPGA chip. The second clock signal; the clock frequency of the second clock signal is higher than the clock frequency of the first clock signal; the cross-clock domain data transmission module is used to implement the clock domain of the first clock signal and the second clock signal Data transfers in the clock domain. This can reduce the impact of other logic resources on the speed of the storage resource module to be tested, improve the test timing convergence characteristics; and can adapt to the test of large-scale storage resources, with good test coverage, simple operation, and low implementation cost.

The FPGA storage resource testing system and its testing principle of the embodiment of the present invention will be further described below in conjunction with FIG. 2 .

As shown in FIG. 2 , the FPGA storage resource testing system includes n sets of data excitation modules, a cross-clock domain data transmission module and a data comparison module, which are respectively used to test the storage resource 1 to storage resource n to be tested. The same clock management module provides clock signals for n groups of data excitation modules, cross-clock domain data transmission modules and data comparison modules. Specifically, the testing principle of the system is as follows:

Clock management module (mark ① in Figure 2): The function of the clock management module is to output two clock signals across clock domains by inputting an external signal source. The low-frequency clock domain is used to drive the excitation and display modules, and the high-frequency clock domain is used for To drive the storage resource to be tested and the data comparison module. In practical applications, CLK1 can be at the same frequency as the external input clock signal, and CLK2 is realized by frequency doubling technology.

Cross-clock domain data transmission module (marked ② in Figure 2): This module can be implemented by dual-port RAM or FIFO memory, and the purpose is to realize data transmission in different clock domains. In the actual test, it can use the same on-chip storage resources of the FPGA device as the storage resources to be tested.

Low-frequency clock domain (marked ③ in Figure 2): CLK1 is a low-frequency clock domain, and its purpose is to ensure that the data stimulus module has better timing convergence characteristics with a lower clock frequency.

High-frequency clock domain (marked ④ in Figure 2): CLK2 is a high-frequency clock domain. In order to realize the speed test of high-speed on-chip storage resources of FPGA devices, it is necessary to use high-frequency clock domains to read data from on-chip storage resources of FPGA devices. Write tests.

Flat division of storage resources to be tested (identified in Figure 2 ⑤): Divide the on-chip storage resources of the FPGA device into n smaller storage resources for testing respectively. In this way, the address length of the storage resources can be reduced, which is conducive to testing The system converges on a higher operating frequency, avoiding the limitation of the test speed of other logic resources except the storage resource to be tested. By adopting the division method, the speed test of large-scale storage resources inside the FPGA device can be realized, and the timing convergence requirement of the test system can be met.

Random data stimulus module (marked ⑥ in Figure 2): This module generates random data for the read-write test of the storage resource to be tested.

Storage resource module to be tested (marked ⑦ in Figure 2): the storage resource to be tested can be configured as RAM, FIFO, shift register, etc. in the FPGA device chip.

Data comparison module (mark ⑧ in Figure 2): This module compares the write data read from the storage resource to be tested with the expected data (that is, the random number generated by the data incentive module), and determines the storage resource to be tested according to the comparison result Whether the read and write operations are correct, in order to ensure the data throughput and real-time processing, it works in the high-frequency clock domain.

Result display module (mark ⑨ in Figure 2): This module processes the output results of different data comparison modules, and displays them in a certain way, so as to observe the results.

In another preferred embodiment, as shown in FIG. 3 , different from the FPGA storage resource testing system shown in FIG. 2 , two clock management modules can be set to be more suitable for testing the speed of on-chip storage resources in FPGA devices. Wherein, the first clock management submodule is used to provide the first clock signal to the data excitation module and the result display module; the second clock management submodule is used to provide the storage resources to be tested in the data comparison module and the FPGA chip. the second clock signal. In Figure 3, two clock management modules are used to drive different clock domains. The CLK2 clock domain can continuously increase the frequency of the external input clock signal, so as to realize the test of the speed of the storage resource to be tested.

The above-mentioned embodiment of the present invention proposes the on-chip storage resource speed test system of the FPGA device across the clock domain, and designs a flat test strategy for improving the timing margin of the FPGA device storage resource test system, reducing the incentive module, control module and Displays the limits imposed by the module on the speed of the test system. And by adopting a cross-clock domain design, the data excitation module and result display module of the test system can be separated from the storage resource module to be tested, so that the peripheral data excitation module and result display module work at a lower clock frequency to avoid The impact of peripheral test control signals, stimulus signals and display signals on the speed test of high-speed storage resources to be tested can improve the timing margin; and, by adopting a flat test strategy, the timing margin of the test system can be improved, so as to meet the timing requirements of the test system Under the premise of the high-speed large-scale FPGA device storage resources for full coverage testing. In addition, the FPGA storage resource testing system and method of the above-mentioned embodiments of the present invention can cover the test of the speed compliance item and the speed touch-up item test of the storage resource on-chip of the FPGA device.

Based on the idea of the FPGA storage resource testing system in the above embodiments, the present invention also provides an embodiment of a FPGA storage resource testing method. As shown in Figure 4, the FPGA storage resource testing method of the present embodiment comprises steps:

S11, providing the first clock signal to the preset data excitation module, and simultaneously providing the second clock signal to the storage resource to be tested in the FPGA chip; the clock frequency of the second clock signal is higher than the clock of the first clock signal frequency;

S12. Read the random data generated by the data excitation module under the first clock signal under the second clock signal, and read the random data generated by the data excitation module under the second clock signal according to the storage resource to be tested. Write data for data write operation;

S13. Comparing the read write data with the read random data, and judging whether the read/write test of the storage resource to be tested under the second clock signal is qualified according to the comparison result.

In a preferred embodiment, step S11 also includes: providing the first clock signal to the preset result display module at the same time; correspondingly, after step S13, a step is also included: sending the reading and writing test results to the result display module , using the result display module to display the read and write test results under the first clock signal.

Through the FPGA storage resource testing method of the above-mentioned embodiment, the data stimulus module is separated from the storage resource module to be tested by different clock signals, so that the peripheral data stimulus module works at a lower clock frequency, and the peripheral test control signal is avoided. , Exciting signals and display signals affect the speed test of high-speed storage resources to be tested, which can improve the timing margin.

It should be noted that for the foregoing method embodiments, for the sake of simplicity of description, they are expressed as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because Certain steps may be performed in other orders or simultaneously in accordance with the present invention. In addition, any combination of the above-mentioned embodiments can be made to obtain other embodiments.

Based on the same idea as the method for testing FPGA storage resources in the above embodiments, the present invention also provides a device for testing FPGA storage resources, which can be used to execute the above method for testing FPGA storage resources. For ease of description, in the schematic structural diagram of the embodiment of the FPGA storage resource testing device, only the parts related to the embodiment of the present invention are shown. Those skilled in the art can understand that the illustrated structure does not constitute a limitation to the device, and can include comparisons. More or fewer components are shown, or some components are combined, or different component arrangements are shown.

Fig. 5 is the schematic structural diagram of the FPGA storage resource testing device of an embodiment of the present invention; As shown in Figure 5, the FPGA storage resource testing device of the present embodiment comprises: clock management module and cross clock domain data transmission module, also includes A data excitation module, a clock control unit 510 , a data acquisition unit 520 and a judging unit 530 respectively connected to the clock management module. Each module is described as follows:

The above-mentioned clock control unit 510 is used to provide the first clock signal to the preset data excitation module, and simultaneously provide the second clock signal to the storage resource to be tested in the FPGA chip; the clock frequency of the second clock signal is higher than the clock frequency of the the clock frequency of the first clock signal;

The above-mentioned data acquisition unit 520 is configured to read the random data generated by the data excitation module under the first clock signal under the second clock signal, and read the storage resource to be tested according to the second clock signal according to the The random data generated by the data stimulus module is the write data for the write operation;

The judging unit 530 is configured to compare the read write data with the read random data, and judge whether the read/write test of the storage resource to be tested under the second clock signal is qualified according to the comparison result.

It should be noted that, in the implementation of the FPGA storage resource testing device of the above example, the content such as information interaction and execution process between the modules is based on the same idea as the foregoing method embodiment of the present invention, and the technical effect it brings is the same as The foregoing method embodiments of the present invention are the same, and for specific content, please refer to the description in the method embodiments of the present invention, which will not be repeated here.

In addition, in the implementation of the FPGA storage resource testing device of the above example, the logical division of each functional module is only an example. In actual applications, it can be based on needs, such as the configuration requirements of corresponding hardware or the convenience of software implementation. The above function allocation is completed by different functional modules, that is, the internal structure of the FPGA storage resource testing device is divided into different functional modules to complete all or part of the functions described above. Each function module can be implemented in the form of hardware or in the form of software function modules.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above-mentioned embodiments can be completed by instructing related hardware through computer programs, and the programs can be stored in a computer-readable storage medium as independent product sale or use. When the program is executed, all or part of the steps in the embodiments of the above-mentioned methods can be executed. Wherein, the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM) and the like.

In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

The above-mentioned embodiments only express several implementation modes of the present invention, and should not be construed as limiting the patent scope of the present invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. a kind of FPGA storage resource test system, it is characterized in that, comprises: clock management module, data excitation module, cross clock domain data transmission module, data comparison module and result display module; The clock management module is used to provide the first clock signal to the data excitation module and the result display module, and to provide the second clock signal to the storage resources to be tested in the data comparison module and the FPGA chip; the second clock the clock frequency of the signal is higher than the clock frequency of the first clock signal; The data excitation module is used to generate random data, and cache the random data to the cross-clock domain data transmission module; The storage resource to be tested reads the random data from the cross-clock domain data transmission module, and performs a write operation according to the read data; The data comparison module is used to read the random data from the cross-clock domain data transmission module, and read the data written into the storage resource to be tested, and compare the read write data with the read random data comparing the data, and judging whether the read-write test of the storage resource to be tested under the second clock signal is qualified according to the comparison result; The result display module is used to display the read and write test results of the storage resource to be tested under the second clock signal. 2. FPGA storage resource testing system according to claim 1, is characterized in that, described cross-clock domain data transmission module adopts dual-port RAM or FIFO memory to realize. 3. FPGA storage resource testing system according to claim 1, is characterized in that, described clock management module is specifically used for: receiving an external input signal, produces the first clock signal with the same frequency of described external signal, and by The frequency doubling technique generates a corresponding second clock signal. 4. FPGA storage resource testing system according to claim 1, is characterized in that, comprises at least two groups of data excitation modules, cross-clock domain data transmission module and data comparison module; The at least two groups of data excitation modules, the cross-clock domain data transmission module and the data comparison module all output read and write test results to the result display module; The at least two groups of data excitation modules, cross-clock domain data transmission modules, and data comparison modules are in one-to-one correspondence with at least two storage resources to be tested. 5. FPGA storage resource testing system according to claim 1, is characterized in that, the quantity of described clock management module is two; One of the clock management modules is used to provide the first clock signal to the data excitation module and the result display module; the other clock management module is used to provide the second clock signal to the storage resources to be tested in the data comparison module and the FPGA chip. clock signal. 6. The FPGA storage resource testing system according to any one of claims 1 to 5, wherein the storage resource to be tested is a RAM, a FIFO memory or a shift register. 7. according to the arbitrary described FPGA storage resource testing system of claim 1 to 5, it is characterized in that, described data comparison module is specifically used for: If the write data read from the storage resource to be tested this time is consistent with the random data read from the cross-clock domain data transmission module this time, it is judged as the current read and write of the storage resource to be tested If the test passes, otherwise, it is determined that the read/write test of the storage resource to be tested fails. 8. A method for testing FPGA memory resources, characterized in that it comprises: Provide the first clock signal to the preset data excitation module, and provide the second clock signal to the memory resource to be tested in the FPGA chip simultaneously; The clock frequency of the second clock signal is higher than the clock frequency of the first clock signal; Read the random data generated by the data excitation module under the first clock signal under the second clock signal, and read the storage resource to be tested according to the random data generated by the data excitation module under the second clock signal Write data for write operations; Comparing the read write data with the read random data, and judging whether the read/write test of the storage resource to be tested under the second clock signal is qualified according to the comparison result. 9. FPGA storage resource testing method according to claim 8, is characterized in that, provides the first clock signal to the preset data excitation module, simultaneously provides the step of the second clock signal to the storage resource to be tested in the FPGA chip, Also includes: Simultaneously provide the first clock signal to the preset result display module; After the step of judging whether the read-write test of the storage resource to be tested under the second clock signal is qualified according to the comparison result, it also includes: The read-write test result is sent to the result display module, and the read-write test result is displayed under the first clock signal through the result display module. 10. A kind of FPGA storage resource testing device, it is characterized in that, comprising: The clock control unit is used to provide the first clock signal to the preset data excitation module, and simultaneously provide the second clock signal to the storage resource to be tested in the FPGA chip; the clock frequency of the second clock signal is higher than that of the first clock signal. the clock frequency of the clock signal; The data acquisition unit is configured to read the random data generated by the data excitation module under the first clock signal under the second clock signal, and read the storage resource to be tested according to the data excitation under the second clock signal. The random data generated by the module is the write data for the write operation; The judging unit is configured to compare the read write data with the read random data, and judge according to the comparison result whether the read/write test of the storage resource to be tested is qualified under the second clock signal.