CN106776467B

CN106776467B - SPI FLASH control chip for command receiving system

Info

Publication number: CN106776467B
Application number: CN201611156694.3A
Authority: CN
Inventors: 陈尔钐; 操炜鼎; 陈永良; 张帆; 胡霄
Original assignee: CETC 20 Research Institute
Current assignee: CETC 20 Research Institute
Priority date: 2016-12-15
Filing date: 2016-12-15
Publication date: 2020-04-28
Anticipated expiration: 2036-12-15
Also published as: CN106776467A

Abstract

The invention provides an SPI FLASH control chip used for a command receiving system. A state machine module instructs a FLASH interface module to read an external SPI FLASH; the FLASH interface module receives word data and transmits it to a dual-port RAM module through the word receiving module; The machine module checks whether the signal is correct or incorrect through the data verification module. If it is wrong, the FLASH interface module re-reads data from the external SPI FLASH; if it is correct, the state machine module instructs the decoding chip interface module to read data from the dual-port RAM module. operate. The invention can meet the application requirements of the receiver command system, has stronger flexibility, stable transmission, less transmission signal lines, small area and simple application, and takes into account the requirements of device internal resource utilization, power consumption and mass production.

Description

SPI FLASH control chip for command receiving system

Technical Field

The invention belongs to the technical field of electronic components, in particular to a digital chip, and particularly relates to an SPI FLASH control chip of a command receiving system.

Background

The conventional command receiving system is composed of a power management module, a decoding chip and a receiver, and the working principle among the three is shown in fig. 1. According to the system, the decoding chip receives serial port data, handshake data information is output through the three SPI data lines, and the receiver determines whether to reply to the response operation of the decoding chip by comparing whether the handshake data information is consistent with the internal setting. The system has the following disadvantages in application:

1. because the receiver is different in manufacturing process and method in the process of batch production, the internal handshake data information of the receiver is different, and the decoding chip cannot communicate with the receiver module if the decoding chip adopts the fixed handshake data information, so that the system does not respond.

2. High-power-consumption components such as an FPGA (field programmable gate array) and a single chip microcomputer are adopted to realize the function of the controller chip, the resource utilization efficiency is low, and the packaging volume is larger than that of a common IC (integrated circuit) chip. The design of components and parts with high resource utilization rate, low power consumption and small volume is the development direction for improving the practicability of military equipment.

3. Foreign devices are adopted and directly applied to the system, so that the use confidentiality is high, and the risk of forbidden transport is faced. Therefore, the independent development of the SPI FLASH control chip of the system has important significance in the localization of components.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides the SPI FLASH control chip for the command receiving system, and according to the advantages of stable data transmission, small area and few signal lines of the SPI FLASH, the configuration of the handshake data inside the decoding chip is realized by controlling the SPI FLASH outside the decoding chip, so that the application requirement of the decoding chip in the command receiving system is realized.

The technical scheme adopted by the invention for solving the technical problems is as follows: an SPIFLASH control chip for a command receiving system comprises a frequency division module, a double-port RAM module, a data verification module, a FLASH interface module, a state machine module and a decoding chip interface module.

The FLASH interface module comprises a shift register, a word receiving module and a read instruction sending module; the decoding chip interface module comprises a read address sending module and a shift register; the frequency division module adopts a decoding chip clock to generate a frequency division clock, and the frequency division clock is provided for the double-port RAM module, the data verification module, the FLASH interface module, the state machine module and the decoding chip interface module; the state machine module sends a read instruction signal to the FLASH interface module, and the read instruction sending module of the FLASH interface module outputs three SPI signals including chip selection, clock and data input and reads an external SPI FLASH; the shift register of the FLASH interface module samples and converts the external SPIFLASH data output signal in serial-parallel mode according to the SPI clock and chip selection signal generated by the read instruction sending module, and the received data is transmitted to the word receiving module; the word receiving module transmits the word data to the double-port RAM module through the word receiving completion and the word data signal to receive and store the word data; after the data is received, the state machine module verifies whether the signal is correct or wrong through the data verification module, if the signal is verified to be wrong, the state machine module indicates the FLASH interface module to close the write enabling signal, resends the SPI FLASH read operation instruction, and performs data reading operation on the external SPIFLASH; if the check is correct, the state machine module opens the read enable signal to indicate the decoding chip interface module to prepare for data reading operation on the dual-port RAM module, the decoding chip interface module controls the dual-port RAM module to output stored word data by providing a read address in cooperation with a read clock and the read enable signal, the read address sending module receives parallel data output by the dual-port RAM module and transmits the parallel data to a shift register of the decoding chip interface module to generate three SPI signals, the requirement of handshake data writing time sequence of the decoding chip is met, and therefore the purpose of internal data configuration is achieved.

The invention has the beneficial effects that:

1) the invention overcomes the defect that the internal handshake data information of the decoding chip can not be modified by adopting the mode of the SPI FLASH and the control chip, can meet the application requirement of a receiver instruction system and has stronger flexibility.

2) The invention adopts the mode of the SPI FLASH and the control chip, wherein the SPI FLASH has the advantages of stable data transmission, less transmission signal lines, small area and simple application, and simultaneously meets the time sequence requirement between the SPI FLASH and the SPI data read-write time sequence of the decoding chip, so that the SPI FLASH can be directly applied to a command receiving system.

3) The invention adopts the mode of SPI FLASH and the controller chip, thereby ensuring the localization rate of the application requirement of the command receiving system on one hand and also considering the requirements of the resource utilization, the power consumption and the batch production in the device on the other hand.

Drawings

FIG. 1 is a schematic diagram of the operation of a command receiving system;

FIG. 2 is a block diagram of an application of the SPI FLASH control chip according to the present invention;

fig. 3 is a schematic block diagram of an SPI FLASH control chip.

Detailed Description

The present invention will be further described with reference to the following drawings and examples, which include, but are not limited to, the following examples.

The SPI FLASH control chip is integrated with a frequency division module, a double-port RAM module, a data verification module, a FLASH interface module, a state machine module and a decoding chip interface module. The frequency division module adopts a decoding chip clock to generate a frequency division clock which is provided for each module in the control chip; the state machine module reads the instruction signal and instructs the FLASH interface module to send a read instruction, and three SPI signals (chip selection, clock and data input) are output to read the external SPI FLASH; after the read instruction is sent, the state machine module writes an enable signal to indicate the dual-port RAM module to open a receiving enable to prepare for receiving word data; after the data is received, the state machine module reads an enable signal to indicate the dual-port RAM module to open a sending enable to prepare for sending word data; the state machine module sends an enable signal to indicate the decoding chip interface module to open data sending enable, three SPI signals (chip selection, clock and data input) are prepared to be output, and handshake data writing operation is carried out on the decoding chip. The FLASH interface module outputs three SPI signals (chip selection, clock and data input) to read an external SPI FLASH, and serial data of the SPI FLASH is converted into parallel word data. The data checking module checks the received word data and judges whether the data is correct or not after all the data are received. The dual-port RAM module stores the received word data according to the write enable and write address signals; and outputting the storage data to the decoding chip interface module according to the read enable and read address signals. The decoding chip interface module performs parallel-serial conversion on the received word data, outputs three SPI data signals (chip selection, clock and data input), and performs handshake data writing operation on the decoding chip.

Above-mentioned SPI FLASH control chip has realized that SPI FLASH data reads, decodes chip data write in, has guaranteed that command receiving system handshake data sets up unanimously with the inside handshake data of decoding chip, has overcome because of manufacturing process error, SPIFLASH and the not unanimous between two handshake information that causes of reasons such as decoding chip time sequence requirement unsatisfied, the unable normal work's of command receiving system not enough.

As shown in fig. 3, the chip according to the embodiment of the present invention includes a frequency division module 1, a dual-port RAM module 2, a FLASH interface module 3, a data check module 4, a state machine module 5, and a decoding chip interface module 6. The frequency division module 1 generates a frequency division clock by adopting a clock input provided by a decoding chip and provides the frequency division clock for each module in the control chip; the dual-port RAM module 2 adopts a dual-port RAM form and is used for storing handshake data; the FLASH interface module 3 comprises a read instruction sending module 7, a word receiving module 8 and a shift register 9, wherein the read instruction sending module 7 is used for receiving a read instruction sending signal of the state machine module 5 and sending a read instruction to the SPI FLASH through three SPI signal lines; the shift register 9 realizes serial-parallel conversion of the SPI data, and converts a received serial data input signal into parallel word data; the receiving module 8 transfers the received word data to the dual-port RAM module for data storage. The data check module 4 checks the received word data, and determines whether the data is correct after all the data are received. The state machine module 5 instructs the FLASH interface module 3 to send a read instruction through a read instruction signal, and outputs three SPI signals (chip select, clock, data input) to perform read operation on an external SPI FLASH; after the read instruction is sent, the state machine module 5 writes an enable signal to indicate the dual-port RAM module 2 to open a receiving enable to prepare for receiving word data; after the data reception is finished, the state machine module 5 reads an enable signal to indicate the dual-port RAM module 2 to open a transmission enable to prepare for transmitting word data; the state machine module 5 instructs the decoding chip interface module 6 to open data transmission enable by sending an enable signal, prepares to output three SPI signals (chip select, clock, data input), and performs handshake data write operation on the decoding chip. The decoding chip interface module 6 comprises a read address sending module 10 and a shift register 11, wherein the read address sending module 10 sends a read address signal to the dual-port RAM module and receives word data; the shift register 11 completes the parallel-serial conversion inside the control chip, and outputs three SPI signal (chip select, clock, data input) write timing sequences meeting the requirements of the decoding chip.

The working principle of the whole chip is as follows: after power-on reset, the state machine module 5 instructs the FLASH interface module 3 to send a read instruction by sending a read instruction signal, and the read instruction sending module 7 outputs three SPI signals (chip select, clock, data input) to perform read operation on an external SPI FLASH; the shift register 9 samples and converts the external SPI FLASH data output signal in serial-parallel mode according to the SPI clock and the chip selection signal generated by the read instruction sending module; the shift register 9 receives and completes the transmission of a word datum to the word receiving module 8; the word receiving module 8 transmits the word data to the double-port RAM module 2 through the word receiving completion and the word data signal to receive and store the word data; after the data reception is completed, the state machine module 5 checks the correct/error signal through the data checking module 4 to instruct the state machine module 5 to perform data storage or data discarding operation. And when the error is checked, the state machine module 5 instructs the FLASH interface module to close the write enable signal, resends the SPI FLASH read operation instruction, and resends the read data operation to the external SPI FLASH. The check is correct, the state machine module 5 opens the read enable signal to indicate the decoding chip interface module 6 to prepare for data reading operation on the dual-port RAM module 2, the decoding chip interface module 6 controls the dual-port RAM module 2 to output stored word data by providing a read address in cooperation with a read clock and the read enable signal, the read address sending module 10 receives parallel data output by the dual-port RAM module 2, and transmits the parallel data to the shift register 11 to generate three SPI signals (chip select, clock and data input), so that the requirement of handshake data writing time sequence of the decoding chip is met, and the purpose of internal data configuration is achieved.

The chip integrates the frequency division module, the double-port RAM module, the data check module, the FLASH interface module, the state machine module and the decoding chip interface module, has simple logic and small occupied area, overcomes the defect that the decoding chip and a receiver cannot communicate because the handshake data information of a command receiving system is uncertain and the SPI FLASH and SPI data writing time sequence difference of the decoding chip are caused, enhances the flexibility of the application of a receiver instruction system, and enables the system device to be produced in batch.

Claims

1. a kind of SPI FLASH control chip that is used for order receiving system, comprises frequency division module, dual-port RAM module, data verification module, FLASH interface module, state machine module and decoding chip interface module, it is characterized in that: described The FLASH interface module includes a shift register, a word receiving module and a read instruction sending module; the decoding chip interface module includes a read address sending module and a shift register; the frequency dividing module uses the decoding chip clock to generate a frequency dividing clock, providing To the dual-port RAM module, the data verification module, the FLASH interface module, the state machine module and the decoding chip interface module; the state machine module sends a read command signal to the FLASH interface module, and the read command sending module of the FLASH interface module outputs three The SPI signal, including chip select, clock and data input, reads the external SPIFLASH; the shift register of the FLASH interface module samples the external SPI FLASH data output signal according to the SPI clock and chip select signal generated by the read command sending module. Serial-to-parallel conversion, after receiving a word of data, it is passed to the word receiving module; the word receiving module transmits the word data to the dual-port RAM module through the word receiving completion and word data signals to receive and store the word data; after the data reception is completed, the state machine The module checks whether the signal is correct or wrong through the data verification module. If the verification is wrong, the state machine module instructs the FLASH interface module to turn off the write enable signal, and resends the SPI FLASH read operation command to read data to the external SPI FLASH; If the verification is correct, the state machine module turns on the read enable signal, indicating that the decoding chip interface module is ready to read data to the dual-port RAM module. The decoding chip interface module controls the dual-port RAM by providing the read address, with the read clock and the read enable signal. The module outputs the stored word data, and the read address sending module receives the parallel data output by the dual-port RAM module, and transmits it to the shift register of the interface module of the decoding chip to generate three SPI signals to meet the requirements of the decoding chip handshake data writing sequence, so as to realize Purpose of internal data configuration.