CN106782653B - A kind of optimization method of read operation - Google Patents
A kind of optimization method of read operation Download PDFInfo
- Publication number
- CN106782653B CN106782653B CN201611117961.6A CN201611117961A CN106782653B CN 106782653 B CN106782653 B CN 106782653B CN 201611117961 A CN201611117961 A CN 201611117961A CN 106782653 B CN106782653 B CN 106782653B
- Authority
- CN
- China
- Prior art keywords
- time
- high potential
- memory cell
- cell string
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000005457 optimization Methods 0.000 title claims abstract description 20
- 230000015654 memory Effects 0.000 claims abstract description 58
- 239000003990 capacitor Substances 0.000 claims abstract description 25
- 230000006698 induction Effects 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 210000004027 cell Anatomy 0.000 description 38
- 238000010586 diagram Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 210000000352 storage cell Anatomy 0.000 description 2
- 101150086396 PRE1 gene Proteins 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Landscapes
- Read Only Memory (AREA)
Abstract
The present invention relates to memory area more particularly to a kind of optimization methods of read operation, comprising: the memory cell string that read operation occurs is remained to non-conduction state within the first precharge time；Within the second precharge time, it sets the memory cell string that read operation occurs to the state of conducting, and the second control voltage is maintained at the third high potential lower than the second high potential；When the second precharge time terminating and entering the sensitive time, the first control voltage is reduced and is maintained at one the 4th high potential lower than the first high potential；The first metal-oxide-semiconductor and the second metal-oxide-semiconductor are turned off at the end of the sensitive time；Above-mentioned technical proposal is pre-charged the memory cell string that read operation is chosen and remained non-conduction state by be allowed memory cell string using higher second high potential, and the first metal-oxide-semiconductor and the second metal-oxide-semiconductor are turned off at the end of the sensitive time, so that the voltage held stationary in the time in first capacitor is latched, to ensure that the latch operation of latch cicuit.
Description
Technical Field
The invention relates to the field of memories, in particular to a read operation optimization method.
Background
Flash memory is a long-lived, non-volatile (maintaining stored data information in the event of a power failure) memory that typically includes a plurality of read circuits for reading information from memory cells in an array; each read operation is often required to be completed within a time period, a memory cell string in which the read operation occurs is selected from a bit line of a selected read circuit, and then information of a specific memory cell is read; the read circuit typically further includes a latch circuit and a first capacitor; a first Metal Oxide Semiconductor (MOS) tube and a second MOS tube are sequentially connected in series on the bit line, the latch circuit and the first capacitor are respectively connected to the series nodes of the first MOS tube and the second MOS tube, the first MOS tube is used for pre-charging the first capacitor under the control of a first control voltage at a first high potential, and the second MOS tube is used for supplying power to at least one memory cell string under the control of a second control voltage at a second high potential; each read operation is completed within a time period, and each time period sequentially comprises a pre-charge time, a sensing time, a latch time and a discharge time in time sequence;
in the prior art, the precharging of the bit line is relatively slow because the MOS transistor controlling the conduction of the memory cell string is turned on during the precharging time, and the current of the memory cell string in the reading operation is strong in most of the precharging time, thereby causing the problems of unstable current and increased energy consumption; furthermore, after the latch time is entered, the voltage on the first capacitance may not yet have stabilized, thereby possibly affecting the latching of the latch circuit.
Disclosure of Invention
Aiming at the problems, the invention provides an optimization method of read operation, which is applied to a read circuit of a flash memory; the reading circuit comprises a bit line, a latch circuit and a first capacitor;
a first MOS transistor and a second MOS transistor are connected in series on the bit line in sequence, the latch circuit provides an input point, the input point and the first capacitor are respectively connected to a series node of the first MOS transistor and the second MOS transistor, the first MOS transistor is used for pre-charging the first capacitor under the control of a first control voltage at a first high potential, and the second MOS transistor is used for supplying power to at least one memory cell string under the control of a second control voltage at a second high potential;
each read operation is completed in a time period, and each time period sequentially comprises pre-charge time, induction time, latch time and discharge time according to a time sequence; the memory cell string for reading generates a continuous electricity state or a voltage reduction state on the first capacitor according to the storage condition of the memory cell string; wherein,
dividing the pre-charging time into a first pre-charging time and a second pre-charging time in sequence; the method comprises the following steps:
a step S1 of maintaining the memory cell string in which the read operation occurs in a non-conductive state for the first precharge time, and maintaining the first control voltage at the first high potential and the second control voltage at the second high potential;
step S2, setting the memory cell string where the read operation occurs to be in a conducting state to generate a conducting current on the memory cell string where the read operation occurs, and maintaining the second control voltage at a third high potential lower than the second high potential during the second precharge time;
step S3, when the second precharge time is over and the sensing time is entered, decreasing and maintaining the first control voltage at a fourth high potential lower than the first high potential, so that the voltage on the first capacitor in the step-down state decreases smoothly, but not so low as to affect the saturation operating state of the memory cell string;
step S4, turning off the first MOS transistor and the second MOS transistor at the end of the sensing time, so as to keep the voltage across the first capacitor at a fifth high potential.
In the above optimization method, each of the memory cell strings includes a third MOS transistor;
and controlling the conduction and non-conduction states of the memory cell string by controlling the conduction and the disconnection of the third MOS tube.
The above optimization method, wherein the second precharge time is immediately after the first precharge time;
and when the first pre-charging time is ended and the second pre-charging time is entered, the second control voltage is converted from the second high potential to the third high potential.
In the above optimization method, the memory cell string provides a current input point, the bit line provides a current output point, and the current input point is connected to the current output point to generate a sixth high voltage potential at the current output point when the second MOS transistor is controlled by the second high voltage potential;
when the second MOS tube is controlled by the third high potential, a voltage lower than the sixth high potential is generated on the current output point.
In the above optimization method, the latch circuit includes a pre-amplifier circuit and a latch, an inverting input terminal of the pre-amplifier circuit forms the input point, a non-inverting input terminal of the pre-amplifier circuit receives a reference voltage, and an output terminal of the pre-amplifier circuit is connected to the latch;
the pre-amplifying circuit further comprises an enable end, and when the enable end works and the voltage received by the inverting input end is smaller than the reference voltage, the pre-amplifying circuit performs amplification output through the output end.
In the above-mentioned optimization method, the latch operates under the control of a third control voltage.
The above optimization method, wherein the discharge time is immediately after the latch time.
The above optimization method, wherein the latch time is immediately after the sensing time.
Has the advantages that: the optimization method of the read operation provided by the invention keeps the memory cell string with the read operation in a non-conducting state in the first pre-charging time, pre-charges the memory cell string selected by the read operation by adopting a higher second high potential, and turns off the first MOS tube and the second MOS tube when the induction time is over, so that the voltage on the first capacitor in the latch time is kept stable, thereby ensuring the latch operation of the latch circuit
Drawings
FIG. 1 is a flowchart illustrating steps of a method for optimizing read operations according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a read circuit according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a memory cell string according to an embodiment of the present invention;
FIG. 4 is a timing diagram of transistors and signals during a read operation in accordance with one embodiment of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
In a preferred embodiment, as shown in fig. 1, a method for optimizing a read operation is provided, which is applied to a read circuit of a flash memory; the circuit structure of the read circuit may be the structure shown in fig. 2, and includes a bit line BL, a latch circuit 10 and a first capacitor CSO；
A first MOS tube M is connected in series on the bit line BL in sequencePCHAnd a second MOS transistor MSELThe latch circuit 10 provides an input point (in fig. 2, the inverting input terminal of the pre-amplifying circuit), the input point and the first capacitor CSOAre respectively connected to the first MOS transistor MPCHAnd a second MOS transistor MSELThe first MOS transistor is used for being at a first high potential VTHTo the first capacitor C under the control of a first control voltage PCHSOPre-charging is performed, and the second MOS transistor MSELFor being at a second high potential VPRE1Supplies power to at least one memory cell string 20 under the control of a second control voltage SEL; each read operation is completed within a time period, each time period including in chronological order a precharge time (T)PRE1+TPRE2) Time of induction TEVALatch time TLATAnd discharge time TDIS(ii) a The memory cell string 20 for performing a read operation is stored in the first capacitor C according to the storage condition of the memory cell string 20SOProducing a continuous electrical state (solid line) or a reduced voltage state (dashed line); wherein,
dividing the precharge time into a first precharge time TPRE1And a second precharge time TPRE2(ii) a The method comprises the following steps:
step S1, during the first pre-charging time TPRE1The memory cell string 20 in which the read operation occurs is kept in a non-conductive state, and the first control voltage PCH is kept at the first high potential VTHAnd holding the second control voltage SEL at the second high potential VPRE1；
Step S2, during the second pre-charging time TPRE2In the memory cell string 20, a read operation occurs, and the memory cell string 20 is set to a conducting state to generate a conducting current I on the memory cell string 20 having the read operationCELLAnd the second control voltage SEL is kept lower than the second high potential VPRE1A third high potential VPRE；
Step S3, during the second pre-charging time TPRE2End and enter sensing time TEVAWhile the first control voltage PCH is lowered and kept lower than the first high potential VTHA fourth high potential VSAFESo that the first capacitor C is in the voltage reduction stateSOThe voltage on is steadily decreasing, but not so low as to affect the saturation operating state of the memory cell string 20;
step S4, sensing time TEVAAt the end, the first MOS transistor M is connectedPCHAnd a second MOS transistor MSELIs turned off to turn off the first capacitor CSOThe voltage at the second terminal is maintained at a fifth high potential.
Specifically, the circuit structure of the memory cell string 20 may be as shown in fig. 3, and the timing diagram of each pin and signal may be as shown in fig. 4; the current on the memory cell string 20 reaches a threshold I after settlingREADTH(ii) a MOS transistor MHVMay be protective under the control of the control signal HV; preferably, the first precharge time TPRE1And a second precharge time TPRE2Is less than or equal to the read operation of the prior art read circuitA precharge time in the time period of (a); the pre-charging process also pre-charges the selected memory cell string, and the first MOS tube M is in the pre-charging processPCHSecond MOS transistor MSELAnd MOS transistor M for protectionHVAre all turned on.
In a preferred embodiment, each memory cell string 20 includes a third MOS transistor MSLS；
By controlling the third MOS transistor MSLSTo control the conductive and non-conductive states of the memory cell string 20.
Specifically, the third MOS transistor MSLSThe control signal of (1) is BSG.
In a preferred embodiment, the second precharge time TPRE2Immediately after a first precharge time TPRE1Then;
at a first precharge time TPRE1End of entering the second precharge time TPRE2When the second control voltage SEL is higher than the second high potential VPRE1Is converted into a third high potential VPRE。
Due to VPRE1Down to VPREThe voltage on the bit line BL therefore falls, enabling a first precharge time TPRE1Internal second higher potential VPRE1A second MOS transistor MSELConducting to fully charge the storage capacitor string 20 without generating conducting current to a source line (or a ground line), thereby ensuring that the potential on the whole storage cell string 20 is consistent after the storage cell string 20 is opened in the second charging stage; wherein the memory cell string 20 can be regarded as forming a parasitic second capacitance C on the bit line BLBL。
In a preferred embodiment, the second MOS transistor MSELAt a third high potential VPRECan be operated in the amplification region under the control of (c), but this is only a preferred case and should not be construed as limiting the invention.
In the above-described embodiment, it is preferable that,as shown in FIG. 3, the memory cell string 20 provides a current input point PINThe bit line BL provides a current output point, and the current input point is connected with the current output point;
when the second MOS transistor MSELAt a second high potential VPRE1Generating a sixth high voltage potential at the current output point under the control of (1);
when the second MOS transistor MSELAt a third high potential VPREA voltage lower than the sixth high potential is generated at the current output point.
In particular, MOS transistor MBLSAt discharge time TLATThe high potential can be kept all the time before, and the control signal is TSG; memory cell M without read operationi-1And Mi+1The control signal of the like is VPASSMemory cell M with read operationiControl signal of VREAD。
In a preferred embodiment, the latch circuit 10 includes a pre-amplifier circuit 11 and a latch 12, wherein an inverting input terminal of the pre-amplifier circuit 11 forms an input point, and a non-inverting input terminal of the pre-amplifier circuit 11 receives a reference voltage VTHSAThe output end of the pre-amplifying circuit 11 is connected with the latch 12;
the pre-amplifying circuit 11 further includes an enable terminal, and when the enable terminal operates at a low potential and the voltage received by the inverting input terminal is less than the reference voltage, the pre-amplifying circuit 11 performs amplification output through the output terminal.
Specifically, the signal received by the enable terminal in fig. 2 is ENA _ N.
In the above embodiment, the latch preferably operates under the control of a third control voltage EN.
In a preferred embodiment, the discharge time TDISImmediately following the latch time TLATAnd then.
In a preferred embodiment, the latch time T isLATImmediately following the induction time TEVAAnd then.
In summary, the method for optimizing a read operation provided by the present invention maintains a non-conductive state of a memory cell string having a read operation within a first precharge time, precharges a memory cell string selected by the read operation with a higher second high voltage, and turns off the first MOS transistor and the second MOS transistor at the end of the sensing time, so that the voltage on the first capacitor is maintained stable within the latch time, thereby ensuring the latch operation of the latch circuit.
While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the above invention sets forth presently preferred embodiments, these are not intended as limitations.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (8)
1. A read operation optimization method is applied to a read circuit of a flash memory; the reading circuit comprises a bit line, a latch circuit and a first capacitor;
a first MOS transistor and a second MOS transistor are connected in series on the bit line in sequence, the latch circuit provides an input point, the input point and the first capacitor are respectively connected to a series node of the first MOS transistor and the second MOS transistor, the first MOS transistor is used for pre-charging the first capacitor under the control of a first control voltage at a first high potential, and the second MOS transistor is used for supplying power to at least one memory cell string under the control of a second control voltage at a second high potential;
each read operation is completed in a time period, and each time period sequentially comprises pre-charge time, induction time, latch time and discharge time according to a time sequence; the memory cell string for reading generates a continuous electricity state or a voltage reduction state on the first capacitor according to the storage condition of the memory cell string; it is characterized in that the preparation method is characterized in that,
dividing the pre-charging time into a first pre-charging time and a second pre-charging time in sequence; the method comprises the following steps:
a step S1 of maintaining the memory cell string in which the read operation occurs in a non-conductive state for the first precharge time, and maintaining the first control voltage at the first high potential and the second control voltage at the second high potential;
step S2, setting the memory cell string where the read operation occurs to be in a conducting state to generate a conducting current on the memory cell string where the read operation occurs, and maintaining the second control voltage at a third high potential lower than the second high potential during the second precharge time;
step S3, when the second precharge time is over and the sensing time is entered, decreasing and maintaining the first control voltage at a fourth high potential lower than the first high potential, so that the voltage on the first capacitor in the step-down state decreases smoothly, but not so low as to affect the saturation operating state of the memory cell string;
step S4, turning off the first MOS transistor and the second MOS transistor at the end of the sensing time, so as to keep the voltage across the first capacitor at a fifth high potential;
the latch circuit comprises a pre-amplifying circuit and a latch, wherein the inverting input end of the pre-amplifying circuit forms the input point, the non-inverting input end of the pre-amplifying circuit receives a reference voltage, and the output end of the pre-amplifying circuit is connected with the latch.
2. The optimization method according to claim 1, wherein each of the memory cell strings includes a third MOS transistor;
and controlling the conduction and non-conduction states of the memory cell string by controlling the conduction and the disconnection of the third MOS tube.
3. The optimization method according to claim 1, characterized in that the second pre-charge time is immediately after the first pre-charge time;
and when the first pre-charging time is ended and the second pre-charging time is entered, the second control voltage is converted from the second high potential to the third high potential.
4. The method of claim 1, wherein the memory cell string provides a current input point, the bit line provides a current output point, and the current input point is connected to the current output point;
when the second MOS tube is controlled by the second high potential, a sixth high potential is generated on the current output point;
when the second MOS tube is controlled by the third high potential, a voltage lower than the sixth high potential is generated on the current output point.
5. The optimization method according to claim 1, wherein the pre-amplifying circuit further includes an enable terminal, and the pre-amplifying circuit amplifies the output signal via the output terminal when the enable terminal is operated and the voltage received by the inverting input terminal is less than the reference voltage.
6. The optimization method of claim 5, wherein the latch operates under control of a third control voltage.
7. The optimization method according to claim 1, wherein the discharge time is immediately after the latch time.
8. The optimization method according to claim 1, wherein the latch time is immediately after the sense time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611117961.6A CN106782653B (en) | 2016-12-07 | 2016-12-07 | A kind of optimization method of read operation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611117961.6A CN106782653B (en) | 2016-12-07 | 2016-12-07 | A kind of optimization method of read operation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106782653A CN106782653A (en) | 2017-05-31 |
| CN106782653B true CN106782653B (en) | 2019-02-15 |
Family
ID=58882339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611117961.6A Active CN106782653B (en) | 2016-12-07 | 2016-12-07 | A kind of optimization method of read operation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106782653B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110718256B (en) * | 2018-07-13 | 2021-07-09 | 西安格易安创集成电路有限公司 | Nonvolatile memory processing circuit and method |
| JP7146114B2 (en) | 2019-04-30 | 2022-10-03 | 長江存儲科技有限責任公司 | Memory system that can reduce read time |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101047030A (en) * | 2006-03-27 | 2007-10-03 | 海力士半导体有限公司 | Flash memory device and read operation method thereof |
| CN101154449A (en) * | 2006-09-29 | 2008-04-02 | 海力士半导体有限公司 | Flash memory device and its reading method |
| CN205692571U (en) * | 2016-06-22 | 2016-11-16 | 珠海泓芯科技有限公司 | Memory reading circuitry |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9070422B2 (en) * | 2012-12-28 | 2015-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and method for sense amplifying |
-
2016
- 2016-12-07 CN CN201611117961.6A patent/CN106782653B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101047030A (en) * | 2006-03-27 | 2007-10-03 | 海力士半导体有限公司 | Flash memory device and read operation method thereof |
| CN101154449A (en) * | 2006-09-29 | 2008-04-02 | 海力士半导体有限公司 | Flash memory device and its reading method |
| CN205692571U (en) * | 2016-06-22 | 2016-11-16 | 珠海泓芯科技有限公司 | Memory reading circuitry |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106782653A (en) | 2017-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9985519B2 (en) | Voltage generation circuit | |
| JP2008052810A (en) | Equalizer circuit and its control method | |
| CN105336369B (en) | Bit line regulator for high speed flash memory system | |
| US20150194193A1 (en) | Memory and reading method thereof, and circuit for reading memory | |
| CN105185404A (en) | Charge transfer type sense amplifier | |
| CN106782653B (en) | A kind of optimization method of read operation | |
| US20100045249A1 (en) | Voltage regulator for write/read assist circuit | |
| US9401192B2 (en) | Ferroelectric memory device and timing circuit to control the boost level of a word line | |
| US7619924B2 (en) | Device and method for reading out memory information | |
| CN111312313A (en) | Circuit for quickly switching voltage of charge pump | |
| CN101197192B (en) | Flash memory writing circuit and its writing method | |
| CN112967740A (en) | Super-high speed read circuit and read method for nonvolatile memory | |
| US6879197B2 (en) | Apparatus for generating driving voltage for sense amplifier in a memory device | |
| KR100542709B1 (en) | Boosting Circuit of Semiconductor Memory Device | |
| US8879332B2 (en) | Flash memory with read tracking clock and method thereof | |
| Jiang et al. | A low-voltage sense amplifier for high-performance embedded flash memory | |
| US9099190B2 (en) | Non-volatile memory device with improved reading circuit | |
| CN114974356A (en) | Sense amplifier and circuit and method of reading data from a memory cell | |
| US11942185B2 (en) | Memory device and method | |
| TWI462115B (en) | Memory apparatus and negative bit-line signal generating apparatus | |
| US20140233295A1 (en) | Rom device with keepers | |
| TWI387974B (en) | Bit line precharge circuit | |
| CN103956179A (en) | Sense amplifier and memory system using same | |
| CN110189786B (en) | Booster circuit applied to flash memory | |
| CN203689919U (en) | Reading and buffering circuit of SRAM (Static Random Access Memory) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |