CN106797215B - Synchronous rectification control unit and method - Google Patents

Abstract

The invention provides a synchronous rectification control unit and a synchronous rectification control method. The synchronous rectification control unit comprises a voltage pulse generation circuit (26) and a control algorithm circuit (27). The synchronous rectification control unit can provide high power supply efficiency and low power consumption loss, and also provides inherent current breakdown protection, fast transient response and low power consumption. Furthermore, the synchronous rectification control unit minimizes the need for PWM resources.

Description

Synchronous rectification control unit and method

technical field

Embodiments described herein generally relate to a synchronous rectification control unit and a synchronous rectification control method. In particular, described herein is a mechanism for generating first and second synchronized pulse width modulation (PWM) control signals for controlling switching power switches.

Background technique

Power switches, such as those implemented using Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or other suitable types of transistors, are used in a large number of circuits today. For example, such power switches are used as power converters, and they can be implemented as half-bridge power converters or full-bridge power converters. For example, a full-bridge power converter circuit may include a synchronous side and an asynchronous side. In such a circuit, the non-synchronized side is the side that inputs the original/unconverted signal/power, and the synchronous side is the side that outputs the controlled/transformed signal/power. This can also be expressed as defining the synchronous rectification side as the side of the circuit where the synchronous rectification power switch is located. Accordingly, the asynchronous rectification side is defined as the other side of the circuit where the main power switch is located.

Thus, for a bidirectional circuit, the asynchronous side of the circuit may correspond to a different physical side of the circuit, depending on which direction the signal/power should be steered/translated, since the original signal/power is input to the asynchronous side. Correspondingly, the synchronous side of the circuit may correspond to different physical sides of the circuit, depending on which direction the signal/power should be steered/converted, since the steered/converted signal/power is output from the synchronous side.

Circuits containing these power switches, such as power conversion circuits, etc., can be used in a variety of units such as User Equipment (UE), which is also known to be capable of communicating wirelessly in a wireless communication network A wireless communication network is also sometimes referred to as a cellular radio system for mobile stations, wireless terminals and/or mobile terminals. Such circuits may also be used in radio network nodes or base stations such as Radio Base Stations (RBSs), which in some networks may be referred to as "eNB", "eNodeB", "NodeB" or "B node" ”, depending on the technology and/or terminology used.

The purpose of switching power converters in such circuits is to save as much energy as possible. The resistance of MOSFETs and other transistors used to implement power switches is generally lower when the switch is closed/conducting than when the switch is open/non-conducting. As a non-limiting example, it may be mentioned that when the switch is open, the MOSFET switch has a voltage drop across the switch corresponding to the body diode voltage of the MOSFET, which may be 0.7 volts. When the MOSFET switch is off, according to a non-limiting example, the voltage drop across the switch is much lower, such as 0.01 volts. Therefore, to achieve the highest possible power efficiency, as much power as possible should flow through the closed switch, which results in a lower voltage drop.

Conventional synchronous rectification has been proposed for improving the power efficiency of a circuit by controlling the switching of power switches contained in the circuit. Today, many conventional synchronous rectification control schemes have been proposed recently. One such solution utilizes current transformers, which are placed on the synchronous rectification side of the circuit. Measure the voltage drop across the current transformer. Based on the measured voltage drop signal, the control circuit generates appropriate pulses to turn on and off the power switch on the synchronous rectification side of the circuit.

However, conventional solutions are generally less efficient because a significant portion of the power flows through the body diode of the power switch when the switch is turned on. In addition, the implementation complexity of the conventional solution is high, which increases the production cost of the circuit.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to address at least some of the disadvantages described above, to improve power supply efficiency, and to reduce the complexity of implementation of a circuit including a synchronous side and an asynchronous side.

According to a first aspect, the object is achieved by a synchronous rectification control unit, the synchronous rectification control unit comprising:

Voltage pulse generation unit for

measure the current I in a circuit including a power switch;

If the positive rate of change of the current I is close to the value 0 of the current I, outputting a logic high value of the first voltage V1; and

If the negative change rate of the current I is close to the value 0 of the current I, a logic high value of the second voltage V2 is output;

a control algorithm circuit for: generating first and second voltages based on first and second asynchronous pulse width modulation (PWM) control signals Q1 and Q2, and based on said first voltage V1 and said second voltage V2 Second synchronous PWM control signals SQ1 and SQ2, the first and second synchronous PWM control signals SQ1 and SQ2 may be used to control the switching of the power switch.

The synchronous rectification control unit can provide high power efficiency and low power loss. The synchronous rectification control unit may generate the first and second synchronous PWM control signals SQ1 and SQ2 based on a continuous or discontinuous AC current waveform, or based on a rectified continuous or discontinuous AC current waveform, which makes the current measurement more efficient. flexible. The synchronous rectification control unit can be implemented with little increase in circuit complexity.

The synchronous rectification control unit also provides inherent current breakdown protection, fast transient response and low power consumption. Furthermore, the synchronous rectification control unit minimizes the need for PWM resources.

According to the first aspect, in a first possible implementation form of the synchronous rectification control unit, the current I is the rectified alternating current I _{AC_rect} , and the control algorithm circuit is configured to: if the first voltage V1 has A logic high value and the first asynchronous PWM control signal Q1 has a logic high value, a logic high value of the first synchronous PWM control signal SQ1 is generated.

The logic high value of the first voltage V1 indicates that the body diode of the synchronous rectification side power switch starts to conduct. Therefore, a logic high value of the first voltage V1 is an indicator to turn on the synchronous rectification side power switch to avoid diode conduction and improve efficiency. Additionally, the first asynchronous PWM control signal Q1 is taken into account to ensure that the first synchronous PWM control signal SQ1 (and not the second synchronous PWM control signal SQ2) is selected.

According to the first aspect as described above or according to any preceding implementation form of the first aspect, in a second possible implementation form of the synchronous rectification control unit, the current I is the rectified alternating current I _{AC_rect} , and the A control algorithm circuit for: if at least one of the first voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and if the second voltage V2 has a logic high value or if the first The two asynchronous PWM control signals Q2 have a logic high value, and then generate a logic low value of the first synchronous PWM control signal SQ1.

The logic high value of the second voltage V2 indicates that the body diode of the synchronous rectification side power switch stops conducting. Therefore, the logic high value of the second voltage V2 is an indicator to turn off the power switch of the synchronous rectification side to avoid current breakdown. Furthermore, the second asynchronous PWM control signal Q2 is taken into account to ensure that current breakdown will not occur. Therefore, the use of the second asynchronous PWM control signal Q2 produces current breakdown protection, which ensures proper circuit operation.

According to the first aspect as described above or according to any preceding implementation form of the first aspect, in a third possible implementation form of the synchronous rectification control unit, the current I is a rectified alternating current I _{AC_rect} , and the a control algorithm circuit for: if at least one of the first voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and if the second voltage V2 and the second asynchronous PWM control Signals Q2 all have a logic low value, then the previous value of the first synchronous PWM control signal SQ1 is generated.

Thereby, the first synchronous PWM control signal SQ1 is set to the correct previous value, ie a logic high value or a logic low value, which makes the system robust and insensitive to circuit disturbances. In addition, the values of the signals in the circuit, ie the values of Q1, V1, Q2 and V2, may be logic low during the time period in which this embodiment is implemented, which means that the energy consumed is minimized.

According to the first aspect as described above or according to any preceding implementation form of the first aspect, in a fourth possible implementation form of the synchronous rectification control unit, the current I is a rectified alternating current I _{AC_rect} , and the The control algorithm circuit is configured to generate a logic high value of the second synchronous PWM control signal SQ2 if the first voltage V1 has a logic high value and the second asynchronous PWM control signal Q2 has a logic high value.

The logic high value of the first voltage V1 indicates that the body diode of the synchronous rectification side power switch starts to conduct. Therefore, a logic high value of the first voltage V1 is an indicator to turn on the synchronous rectification side power switch to avoid diode conduction and improve efficiency. In addition, the second asynchronous PWM control signal Q2 is taken into account to ensure that the second synchronous PWM control signal SQ2 (and not the first synchronous PWM control signal SQ1) is selected.

According to the first aspect as described above or according to any preceding implementation form of the first aspect, in a fifth possible implementation form of the synchronous rectification control unit, the current I is a rectified alternating current I _{AC_rect} , and the A control algorithm circuit for: if at least one of the first voltage V1 and the second asynchronous PWM control signal Q2 has a logic low value, and if the second voltage V2 has a logic high value or if the first When an asynchronous PWM control signal Q1 has a logic high value, a logic low value of the second synchronous PWM control signal SQ2 is generated.

The logic high value of the second voltage V2 indicates that the body diode of the synchronous rectification side power switch stops conducting. Therefore, the logic high value of the second voltage V2 is an indicator to turn off the power switch of the synchronous rectification side to avoid current breakdown. Additionally, the first asynchronous PWM control signal Q1 is taken into account to ensure that current breakdown will not occur. Therefore, the use of the first asynchronous PWM control signal Q1 creates protection, which ensures proper circuit operation.

According to the first aspect as described above or according to any preceding implementation form of the first aspect, in a sixth possible implementation form of the synchronous rectification control unit, the current I is a rectified alternating current I _{AC_rect} , and the a control algorithm circuit for: if at least one of the first voltage V1 and the second asynchronous PWM control signal Q2 has a logic low value, and if the second voltage V2 and the first asynchronous PWM control Signals Q1 both have a logic low value, generating the previous value of the second synchronous PWM control signal SQ2.

Thereby, it is ensured that the second synchronous PWM control signal SQ2 is set to the correct value, eg a logic high value or a logic low value, which makes the system robust and insensitive to circuit disturbances. In addition, the logic values of the signals in the circuit, ie the values of Q1, V1, Q2 and V2, may be low during the time period in which this embodiment is implemented, which means that the energy consumed is minimized.

According to the first aspect as described above, in a seventh possible implementation form of the synchronous rectification control unit, the current I is an alternating current I _AC , and the control algorithm circuit is configured to: if the first voltage V1 has a logic A high value and the first asynchronous PWM control signal Q1 has a logic high value, then a logic high value of the first synchronous PWM control signal SQ1 is generated.

Here, the first asynchronous PWM control signal Q1 is taken into account to ensure that the first synchronous PWM control signal SQ1 is selected instead of the second synchronous PWM control signal SQ2. Then the logic high value of the first voltage V1 indicates that the body diode of the power switch on the synchronous rectification side starts to conduct. Therefore, the logic high value of the first voltage V1 is an indicator that the synchronous rectification side power switch SQ1 is turned on to avoid diode conduction and improve power efficiency.

According to the first aspect as described above or according to a seventh possible implementation form of the first aspect, in an eighth possible implementation form of the synchronous rectification control unit, the current I is an alternating current I _AC , and the control algorithm The circuit is configured to: if at least one of the first voltage V1 and the first non-synchronous PWM control signal Q1 has a logic low value, and if the second voltage V2 has a logic high value or if the second non-synchronous PWM control signal Q1 has a logic low value When the synchronous PWM control signal Q2 has a logic high value, a logic low value of the first synchronous PWM control signal SQ1 is generated.

The logic high value of the second voltage V2 indicates that the body diode of the synchronous rectification side power switch stops conducting. Therefore, the logic high value of the second voltage V2 is an indicator to turn off the synchronous rectification side power switch SQ1 to avoid current breakdown. Therefore, the use of the second asynchronous PWM control signal Q2 creates circuit protection and ensures that current breakdown will not occur. Thereby, proper circuit operation is ensured.

According to the first aspect as described above or according to any one of the seventh or eighth possible implementation forms of the first aspect, in a ninth possible implementation form of the synchronous rectification control unit, the current I is an alternating current I _AC , and the control algorithm circuit for: if at least one of the first voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and if the second voltage V2 and the Both the second asynchronous PWM control signals Q2 have a logic low value, and the previous value of the first synchronous PWM control signal SQ1 is generated.

Thereby, it is ensured that the first synchronous PWM control signal SQ1 is set to the correct previous value, ie a logic high value or a logic low value, which makes the system robust and insensitive to circuit disturbances. Furthermore, the values of the signals in the circuit, eg, the values of Q1, V1, Q2, and V2, may be low during the time period in which this embodiment is implemented, which means that the energy consumed is minimized.

According to the first aspect as described above or according to any one of the seventh, eighth or ninth possible implementation forms of the first aspect, in a tenth possible implementation form of the synchronous rectification control unit, the current I is the alternating current I _AC , and the control algorithm circuit is configured to generate the second synchronous PWM if the second voltage V2 has a logic high value and the second asynchronous PWM control signal Q2 has a logic high value Logic high value of control signal SQ2.

Here, the second asynchronous PWM control signal Q2 is taken into account to ensure that the first synchronous PWM control signal SQ1 is selected, and that the second synchronous PWM control signal SQ2 is not selected. The logic high value of the second voltage V2 indicates that the body diode of the synchronous rectification side power switch SQ2 starts to conduct. Therefore, the logic high value of the second voltage V2 is an indicator that the synchronous rectification side power switch SQ2 is turned on to avoid diode conduction and improve the power efficiency.

According to the first aspect as described above or according to any one of the seventh, eighth, ninth or tenth possible implementation forms of the first aspect, in an eleventh possible implementation form of the synchronous rectification control unit , the current I is an alternating current I _AC , and the control algorithm circuit is adapted to: if at least one of the second voltage V2 and the second asynchronous PWM control signal Q2 has a logic low value, and if the The first voltage V1 has a logic high value or a logic low value of the second synchronous PWM control signal SQ2 is generated if the first asynchronous PWM control signal Q1 has a logic high value.

The logic high value of the first voltage V1 indicates that the body diode of the synchronous rectification side power switch SQ2 stops conducting. Therefore, the logic high value of the first voltage V1 is an indicator to turn off the synchronous rectification side power switch SQ2 to avoid current breakdown. Furthermore, the first asynchronous PWM control signal Q1 is taken into account to ensure that current breakdown will not occur. Therefore, the use of the second asynchronous PWM control signal Q2 acts here as a protection, which ensures proper circuit operation.

According to the first aspect as described above or according to any one of the seventh, eighth, ninth, tenth or eleventh possible implementation forms of the first aspect, in the first aspect of the synchronous rectification control unit In twelve possible implementation forms, the current I is an alternating current I _AC , and the control algorithm circuit is configured to: if at least one of the second voltage V2 and the second asynchronous PWM control signal Q2 has a logic low value, and if both the first voltage V1 and the first asynchronous PWM control signal Q1 have a logic low value, the previous value of the second synchronous PWM control signal SQ2 is generated.

Thereby, it is ensured that the second synchronous PWM control signal SQ2 is set to the correct previous value, ie a logic high value or a logic low value, which makes the system robust and insensitive to circuit disturbances. Furthermore, the values Q1 , V1 , Q2 and V2 of the signals in the circuit may be low values during the time period in which this embodiment is implemented, which means that as little energy as possible is consumed.

According to a second aspect, the object is achieved by a synchronous rectification control method, the method comprising:

measure the current I in a circuit including a power switch;

If the positive rate of change of the current I is close to the value 0 of the current I, a logic high value of the first voltage V1 is output, or

If the negative rate of change of the current I is close to the value 0 of the current I, outputting a logic high value of the second voltage V2; and

Based on first and second asynchronous pulse width modulation (PWM) control signals Q1 and Q2, and based on said first voltage V1 and said second voltage V2, first and second synchronous PWM control signals are generated Signals SQ1 and SQ2, the first and second synchronous PWM control signals SQ1 and SQ2 may be used to control the switching of the power switch.

The synchronous rectification control method can provide high power efficiency and low power loss. The synchronous rectification control method may generate the first and second synchronous PWM control signals SQ1 and SQ2 based on a continuous or discontinuous AC current waveform, or based on a rectified continuous or discontinuous AC current waveform, which makes current measurement more flexible. The synchronous rectification control method can be implemented with little increase in circuit complexity.

The synchronous rectification control method also provides current breakdown protection, fast transient response and low power consumption. Additionally, the synchronous rectification control method minimizes the need for PWM resources.

According to the second aspect, in a first possible implementation form of the synchronous rectification control method, the current I is the rectified alternating current I _{AC_rect} , and if the first voltage V1 has a logic high value and the first If the asynchronous PWM control signal Q1 has a logic high value, the control algorithm circuit generates a logic high value of the first synchronous PWM control signal SQ1.

The logic high value of the first voltage V1 indicates that the body diode of the synchronous rectification side power switch starts to conduct. Therefore, a logic high value of the first voltage V1 is an indicator to turn on the synchronous rectification side power switch to avoid diode conduction and improve efficiency. Additionally, the first asynchronous PWM control signal Q1 is taken into account to ensure that the first synchronous PWM control signal SQ1 (and not the second synchronous PWM control signal SQ2) is selected.

According to the second aspect as described above or according to any preceding implementation form of the second aspect, in a second possible implementation form of the synchronous rectification control method, the current I is the rectified alternating current I _{AC_rect} , and if all at least one of the first voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and if the second voltage V2 has a logic high value or if the second asynchronous PWM control signal Q2 has a logic high value A logic high value, the control algorithm circuit generates a logic low value of the first synchronous PWM control signal SQ1.

The logic high value of the second voltage V2 indicates that the body diode of the synchronous rectification side power switch stops conducting. Therefore, the logic high value of the second voltage V2 is an indicator to turn off the power switch of the synchronous rectification side to avoid current breakdown. Additionally, the second asynchronous PWM control signal Q2 is taken into account to ensure that current breakdown will not occur. Therefore, the use of the second asynchronous PWM control signal Q2 creates a current breakdown protection, which ensures proper circuit operation.

According to the second aspect as described above or according to any preceding implementation form of the first aspect, in a third possible implementation form of the synchronous rectification control method, the current I is the rectified alternating current I _{AC_rect} , and if all at least one of the first voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and if both the second voltage V2 and the second asynchronous PWM control signal Q2 have a logic low value, The control algorithm circuit then generates the previous value of the first synchronous PWM control signal SQ1.

Thereby, the first synchronous PWM control signal SQ1 is set to the correct previous value, ie a logic high value or a logic low value, which makes the system robust and insensitive to circuit disturbances. In addition, the values of the signals in the circuit, ie the values of Q1, V1, Q2 and V2, may be logic low during the time period in which this embodiment is implemented, which means that the energy consumed is minimized.

According to the second aspect as described above or according to any preceding implementation form of the first aspect, in a fourth possible implementation form of the synchronous rectification control method, the current I is the rectified alternating current I _{AC_rect} , and if all If the first voltage V1 has a logic high value and the second asynchronous PWM control signal Q2 has a logic high value, the control algorithm circuit generates a logic high value of the second synchronous PWM control signal SQ2.

The logic high value of the first voltage V1 indicates that the body diode of the synchronous rectification side power switch starts to conduct. Therefore, a logic high value of the first voltage V1 is an indicator to turn on the synchronous rectification side power switch to avoid diode conduction and improve efficiency. In addition, the second asynchronous PWM control signal Q2 is taken into account to ensure that the second synchronous PWM control signal SQ2 (and not the first synchronous PWM control signal SQ1) is selected.

According to the second aspect as described above or according to any preceding implementation form of the first aspect, in a fifth possible implementation form of the synchronous rectification control method, the current I is the rectified alternating current I _{AC_rect} , and if all at least one of the first voltage V1 and the second asynchronous PWM control signal Q2 has a logic low value, and if the second voltage V2 has a logic high value or if the first asynchronous PWM control signal Q1 has a logic high value A logic high value, the control algorithm circuit generates a logic low value of the second synchronous PWM control signal SQ2.

The logic high value of the second voltage V2 indicates that the body diode of the synchronous rectification side power switch stops conducting. Therefore, the logic high value of the second voltage V2 is an indicator to turn off the power switch of the synchronous rectification side to avoid current breakdown. Additionally, the first asynchronous PWM control signal Q1 is taken into account to ensure that current breakdown will not occur. Therefore, the use of the first asynchronous PWM control signal Q1 creates protection, which ensures proper circuit operation.

According to the second aspect as described above or according to any preceding implementation form of the first aspect, in a sixth possible implementation form of the synchronous rectification control method, the current I is the rectified alternating current I _{AC_rect} , and if all at least one of the first voltage V1 and the second asynchronous PWM control signal Q2 has a logic low value, and if both the second voltage V2 and the first asynchronous PWM control signal Q1 have a logic low value, The control algorithm circuit then generates the previous value of the second synchronous PWM control signal SQ2.

Thereby, it is ensured that the second synchronous PWM control signal SQ2 is set to the correct previous value, eg a logic high value or a logic low value, which makes the system robust and insensitive to circuit disturbances. In addition, the logic values of the signals in the circuit, ie the values of Q1, V1, Q2 and V2, may be low during the time period in which this embodiment is implemented, which means that the energy consumed is minimized.

According to the second aspect as described above, in a seventh possible implementation form of the synchronous rectification control method, the current I is an alternating current I _AC , and if the first voltage V1 has a logic high value and the first non- If the synchronous PWM control signal Q1 has a logic high value, the control algorithm circuit generates a logic high value of the first synchronous PWM control signal SQ1.

Here, the first asynchronous PWM control signal Q1 is taken into account to ensure that the first synchronous PWM control signal SQ1 is selected instead of the second synchronous PWM control signal SQ2. Then the logic high value of the first voltage V1 indicates that the body diode of the power switch on the synchronous rectification side starts to conduct. Therefore, the logic high value of the first voltage V1 is an indicator that the synchronous rectification side power switch SQ1 is turned on to avoid diode conduction and improve power efficiency.

According to the second aspect as described above or according to the seventh possible implementation form of the first aspect, in the eighth possible implementation form of the synchronous rectification control method, the current I is an alternating current I _AC , and if the first At least one of a voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and if the second voltage V2 has a logic high value or if the second asynchronous PWM control signal Q2 has a logic high value, the control algorithm circuit generates a logic low value of the first synchronous PWM control signal SQ1.

The logic high value of the second voltage V2 indicates that the body diode of the synchronous rectification side power switch stops conducting. Therefore, the logic high value of the second voltage V2 is an indicator to turn off the synchronous rectification side power switch SQ1 to avoid current breakdown. Therefore, the use of the second asynchronous PWM control signal Q2 creates circuit protection and ensures that current breakdown will not occur. Thereby, proper circuit operation is ensured.

According to the second aspect as described above or according to any one of the seventh or eighth possible implementation forms of the first aspect, in a ninth possible implementation form of the synchronous rectification control method, the current I is an alternating current I _AC , and if at least one of the first voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and if the second voltage V2 and the second asynchronous PWM control signal Q2 both have a logic low value, the control algorithm circuit generates the previous value of the first synchronous PWM control signal SQ1.

Thereby, it is ensured that the first synchronous PWM control signal SQ1 is set to the correct previous value, ie a logic high value or a logic low value, which makes the system robust and insensitive to circuit disturbances. Furthermore, the values of the signals in the circuit, eg, the values of Q1, V1, Q2 and V2, may be low during the time period in which this embodiment is implemented, which means that the energy consumed is minimized.

According to the first aspect as described above or according to any one of the seventh, eighth or ninth possible implementation forms of the first aspect, in the tenth possible implementation form of the synchronous rectification control method, the current I is the alternating current I _AC , and if the second voltage V2 has a logic high value and the second asynchronous PWM control signal Q2 has a logic high value, the control algorithm circuit generates the second synchronous PWM control signal SQ2 logical high value.

Here, the second asynchronous PWM control signal Q2 is taken into account to ensure that the first synchronous PWM control signal SQ1 is selected, and that the second synchronous PWM control signal SQ2 is not selected. The logic high value of the second voltage V2 indicates that the body diode of the synchronous rectification side power switch starts to conduct. Therefore, the logic high value of the second voltage V2 is an indicator that the synchronous rectification side power switch SQ2 is turned on to avoid diode conduction and improve the power efficiency.

According to the second aspect as described above or according to any one of the seventh, eighth, ninth or tenth possible implementation forms of the first aspect, in an eleventh possible implementation form of the synchronous rectification control method , the current I is the alternating current I _AC , and if at least one of the second voltage V2 and the second asynchronous PWM control signal Q2 has a logic low value, and if the first voltage V1 has a logic high value Alternatively, the control algorithm circuit generates a logic low value of the second synchronous PWM control signal SQ2 if the first asynchronous PWM control signal Q1 has a logic high value.

The logic high value of the first voltage V1 indicates that the body diode of the synchronous rectification side power switch SQ2 stops conducting. Therefore, the logic high value of the first voltage V1 is an indicator to turn off the synchronous rectification side power switch SQ2 to avoid current breakdown. Furthermore, the first asynchronous PWM control signal Q1 is taken into account to ensure that current breakdown will not occur. Therefore, the use of the second asynchronous PWM control signal Q2 acts here as a protection, which ensures proper circuit operation.

According to the second aspect as described above or according to any one of the seventh, eighth, ninth, tenth or eleventh possible implementation forms of the first aspect, in the tenth aspect of the method for controlling synchronous rectification In two possible implementations, the current I is an alternating current I _AC , and if at least one of the second voltage V2 and the second asynchronous PWM control signal Q2 has a logic low value, and if the first voltage Both V1 and the first asynchronous PWM control signal Q1 have a logic low value, and the control algorithm circuit generates the previous value of the second synchronous PWM control signal SQ2.

Thereby, it is ensured that the second synchronous PWM control signal SQ2 is set to the correct previous value, ie a logic high value or a logic low value, which makes the system robust and insensitive to circuit disturbances. Additionally, the values of the signals in the circuit, ie the values of Q1, V1, Q2 and V2, may be low during the time period in which this embodiment is implemented, which means that the energy consumed is minimized.

According to a third aspect, the object is achieved by a computer program having program code for carrying out a method according to the second aspect when the computer program is run on a computer.

The advantages of the computer program according to the third aspect correspond to the advantages of the second aspect described above. Furthermore, a computer program with program code makes environmental conditions more flexible, accurate and robust. In addition, the program code is easy to modify and update.

According to a fourth aspect, this object is achieved by an integrated circuit comprising at least one synchronous rectification control unit according to the first aspect as described above or according to any preceding implementation form of the first aspect.

The advantages of the integrated circuit according to the fourth aspect correspond to the advantages of the first aspect described above.

According to a fifth aspect, this object is achieved by a power electronic device having a power converter comprising a synchronous rectification control unit according to the first aspect as described above or according to any preceding implementation form of the first aspect .

The advantages of the power converter according to the fifth aspect correspond to the advantages of the first aspect described above.

The embodiments described above enable high power efficiency for circuits that include one or more power switches. These circuits may include power converters, such as resonant switching power converters.

The synchronous rectification control unit may be connected to a circuit including one or more power switches by using rectified AC current or AC current.

The synchronous rectification control algorithm can be implemented by an analog control circuit or a digital control circuit.

In addition, the proposed synchronous rectification control method can be applied to bidirectional resonant switching power converters, etc.

Other objects, advantages and novel features of embodiments of the present invention will become apparent from the following detailed description.

Description of drawings

Examples of embodiments of the invention are illustrated in the accompanying drawings, which are described in greater detail in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic block diagram of a synchronous rectification control unit according to some embodiments.

Figure 2 is a flow diagram illustrating some embodiments.

3a-3b are block diagrams illustrating some embodiments.

4 is a flow diagram illustrating some embodiments.

5a-5b are block diagrams illustrating some embodiments.

Figure 6 shows examples of input and output signal values in accordance with some embodiments.

Figure 7 shows examples of input and output signal values in accordance with some embodiments.

Figure 8 shows examples of input and output signal values in accordance with some embodiments.

FIG. 9 shows examples of input and output signal values in accordance with some embodiments.

10 is a schematic block diagram of a power converter including a synchronous rectification control unit according to some embodiments.

FIG. 11 is a flowchart of a synchronous rectification control method according to some embodiments.

12 is a schematic block diagram illustrating a processing circuit implementing a synchronous rectification control method according to some embodiments.

Detailed ways

The embodiments described in the present invention are defined as a synchronous rectification control unit and a method for controlling synchronous rectification, which will be implemented in the embodiments described below. These embodiments may, however, be exemplary and may take many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete .

Other objects and features will also become apparent from the following detailed description considered in conjunction with the accompanying drawings. It should be understood, however, that the drawings are for illustration only, and not as limitations on the embodiments; for embodiments, reference should be made to the appended claims. Further, the drawings are not necessarily to scale, and unless otherwise indicated, they are merely conceptual illustrations of structures and flows.

FIG. 1 schematically shows the internal structure of a synchronous rectification control unit 100 implementing an embodiment of the present invention.

The synchronous rectification control unit 100 includes a voltage pulse generation circuit 26 and a control algorithm circuit 27 . The synchronous rectification control unit 100 has a current I in the circuit 200 including the power switch 50 and has first and second asynchronous PWM control signals Q1 30 and Q2 31 as inputs. The synchronous rectification control unit 100 outputs first and second synchronous PWM control signals SQ1 32 and SQ2 33 , which can be used to control the switching of the power switch 50 .

The voltage pulse generation circuit 26 is used to measure/detect the current I. The voltage pulse generation circuit 26 is also used to output two voltage pulses.

If the measured/detected current I has a positive rate of change, dI/dt>0, near/close to the value 0 of the current I, a logic high value of the first voltage V1 28 is output. In this document, dI/dt corresponds to the time derivative of the current I, which obviously represents the rate of change of the current, i.e. whether the current I is increasing (positive value) or decreasing (negative value).

If the current I has a negative rate of change, dI/dt<0, and is close to/close to the value 0 of the current I, a logic high value of the second voltage V229 is output.

The first and second voltage pulses V1 28 and V2 29 , and the first and second asynchronous PWM control signals Q1 30 and Q2 31 are inputs to the control algorithm circuit 27 . The control algorithm circuit 27 is used to generate the first and second synchronous PWM control signals SQ1 32 and SQ2 33 . These first and second synchronous PWM control signals SQ1 32 and SQ2 33 may be used to control switching of the power switch 50 in the circuit 200 .

The control algorithm circuit 27 is configured to generate first and second voltages based on the first and second asynchronous PWM control signals Q1 30 and Q2 31 and based on the first voltage V1 28 and the second voltage V229 output by the voltage pulse generating circuit 26 The PWM control signals SQ1 32 and SQ2 33 are synchronized. Accordingly, the control logic/algorithm implemented in the control algorithm circuit 27 generates the first and second voltage pulses V1 28 and V2 29 based on the first and second voltage pulses V1 28 and V2 29 and based on the first and second asynchronous PWM control signals Q1 30 and Q2 31 The PWM control signals SQ1 32 and SQ2 33 are synchronized and their values are determined. The control logic/algorithm for generating the first and second synchronous PWM control signals SQ1 32 and SQ2 33 is explained in detail below.

The switching of the power switch 50 in the circuit 200 is then performed by using these generated first and second synchronous PWM control signals SQ1 32 and SQ233.

The synchronous rectification control unit 100 according to the embodiment of the present invention has several advantages. The synchronous rectification control unit provides high power efficiency. The synchronous rectification control unit 100 may also provide the first and second synchronous PWM control signals SQ132 and SQ2 33 based on any one of the AC current waveform and the rectified AC current waveform, whereas conventional solutions are limited to AC current waveforms. Since the synchronous rectification control unit 100 can use both AC and rectified AC, greater flexibility in current measurement is obtained.

In addition, the synchronous rectification control unit 100 according to the embodiment of the present invention provides a simple, low-complexity and robust solution to the above problem.

The synchronous rectification control unit 100 thus utilizes a simple control algorithm for synchronous rectification, which utilizes narrow pulses indicative of the power switch on and off time points. The synchronous rectification control unit 100 also provides inherent current breakdown protection, fast transient response, and low power consumption.

The present invention utilizes a saturable current transformer that generates voltage pulses in the voltage pulse generation circuit 26 , such as a current sensing circuit including a saturable comparator, combined with an intelligence for synchronous rectification control implemented in the control algorithm circuit 27 Control method/algorithm/logic. The use of saturated current transformers has the effect of reducing power loss.

The first and second synchronous PWM control signals SQ1 and SQ2 are here generated based on the first and second non-synchronous control signals Q1 and Q2. Thereby, the PWM resources in the synchronous rectification control unit 100 are minimized.

FIG. 2 is a flow chart illustrating two embodiments of a method/algorithm/logic for controlling the algorithmic circuit 27 .

According to the embodiment shown in the left branch of FIG. 2 , the current I input to the synchronous rectification control unit 100 is the rectified alternating current I _{AC_rect} . The method/algorithm/logic corresponding to the control algorithm circuit 27 of the left branch of FIG. 2 is also shown in the flip-flop circuit of FIG.

As described above, the voltage pulse generating unit 26 is used to measure the rectified alternating current I _{AC_rect} and output the first and second voltages V1 28 and V2 29 .

According to an embodiment, if both the first voltage V1 28 and the first asynchronous PWM control signal Q1 30 have a logic high value, the control algorithm circuit 27, based on the inputted first and second asynchronous PWM control signals Q1 30 and 31 and a logic high value for generating the first synchronous PWM control signal SQ1 32 based on the first and second voltages V1 28 and V2 29 . The generated and output logic high value of the first synchronous PWM control signal SQ1 32 is then latched to the logic high value.

According to an embodiment, if at least one of the first voltage V1 28 and the first asynchronous PWM control signal Q1 30 has a logic low value, and if the second voltage V2 29 has a logic high value or if the second asynchronous PWM control signal Q2 31 has a logic high value, then the control algorithm circuit 27, based on the inputted first and second asynchronous PWM control signals Q130 and Q2 31 and based on the first and second voltages V1 28 and V2 29, is used to generate and output The logic low value of the first synchronous PWM control signal SQ1 32 . The output logic low value of the first synchronous PWM control signal SQ1 32 is then latched to the logic low value.

According to an embodiment, if at least one of the first voltage V1 28 and the first asynchronous PWM control signal Q1 30 has a logic low value, and if both the second voltage V2 29 and the second asynchronous PWM control signal Q2 31 have logic low value, the control algorithm circuit 27, based on the input of the first and second asynchronous PWM control signals Q1 30 and Q2 31 and based on the first and second voltages V1 28 and V2 29, is used to output the first synchronous PWM control The previous value of signal SQ1 32. The outputted previous values of the first synchronous PWM control signal SQ1 32 are then locked to these previous values.

According to the embodiment shown in the right branch of FIG. 2 , the current I input to the synchronous rectification control unit 100 is the rectified alternating current I _{AC_rect} . The method/algorithm/logic corresponding to the control algorithm circuit 27 of the right branch of FIG. 2 is also shown in the flip-flop circuit of FIG.

According to an embodiment, if the first voltage V1 28 has a logic high value and the second asynchronous PWM control signal Q231 has a logic high value, the control algorithm circuit 27, based on the inputted first and second asynchronous PWM control signals Q1 30 and Q2 31 and based on the first and second voltages V1 28 and V2 29 for generating and outputting a logic high value of the second synchronous PWM control signal SQ2 33 . The output logic high value of the second synchronous PWM control signal SQ2 33 is then latched to the logic high value.

According to an embodiment, if at least one of the first voltage V1 28 and the second asynchronous PWM control signal Q2 31 has a logic low value, and if the second voltage V2 29 has a logic high value or if the first asynchronous PWM control signal Q1 30 has a logic high value, then the control algorithm circuit 27, based on the inputted first and second asynchronous PWM control signals Q130 and Q2 31 and based on the first and second voltages V1 28 and V2 29, is used to generate and output The logic low value of the second synchronous PWM control signal SQ2 33. The output logic low value of the second synchronous PWM control signal SQ2 33 is then latched to the logic low value.

According to an embodiment, if at least one of the first voltage V1 28 and the second asynchronous PWM control signal Q2 31 has a logic low value, and if both the second voltage V2 29 and the first asynchronous PWM control signal Q1 30 have logic low value, the algorithm circuit 27 is controlled for generating and outputting a second synchronous PWM based on the inputted first and second asynchronous PWM control signals Q1 30 and Q2 31 and on the basis of the first and second voltages V1 28 and V2 29 The previous value of the PWM control signal SQ2 33. The previous values of the second synchronous PWM control signal SQ2 33 are then locked to these previous values accordingly.

FIG. 4 is a flowchart illustrating two embodiments of a method/algorithm/logic for controlling the algorithmic circuit 27 .

According to the embodiment shown in the left branch of FIG. 4 , the current I input to the synchronous rectification control unit 100 is an alternating current I _{AC_rect} , that is, a non-rectified current. The method/algorithm/logic corresponding to the control algorithm circuit 27 of the left branch of FIG. 4 is also shown in the flip-flop circuit of FIG.

If the alternating current I _AC is here the measured synchronous rectification side current I _{AC_sec} 35 , then the synchronous rectification control unit is the synchronous rectification side unit 2 connected to the AC part of the synchronous rectification side 220 , as illustrated in FIG. 10 below.

Correspondingly, if the alternating current I _AC is here the measured asynchronous whole alternating current AC I _AC,prim 36, then the synchronous rectification control unit 100 is the asynchronous rectification side unit 3 connected to the AC part of the asynchronous rectification side 210, as follows As shown in Figure 10.

According to an embodiment, if the first voltage V1 28 has a logic high value and the first asynchronous PWM control signal Q130 has a logic high value, the control algorithm circuit 27, based on the inputted first and second asynchronous PWM control signals Q1 30 and Q2 31 and based on the first and second voltages V1 28 and V2 29 for generating and outputting a logic high value of the first synchronous PWM control signal SQ1 32. The output logic high value of the first synchronous PWM control signal SQ1 32 is then latched to the logic high value.

According to an embodiment, if at least one of the first voltage V1 28 and the first asynchronous PWM control signal Q1 30 has a logic low value, and if the second voltage V2 29 has a logic high value or if the second asynchronous PWM control signal Q2 31 has a logic high value, then the control algorithm circuit 27, based on the inputted first and second asynchronous PWM control signals Q130 and Q2 31 and based on the first and second voltages V1 28 and V2 29, is used to generate and output The logic low value of the first synchronous PWM control signal SQ1 32 . The output logic low value of the first synchronous PWM control signal SQ1 32 is then latched to the logic low value.

According to an embodiment, if at least one of the first voltage V1 28 and the first asynchronous PWM control signal Q1 30 has a logic low value, and if both the second voltage V2 29 and the second asynchronous PWM control signal Q2 31 have logic low value, the control algorithm circuit 27, based on the inputted first and second asynchronous PWM control signals Q1 30 and Q2 31 and based on the first and second voltages V1 28 and V2 29, is used to generate and output the first synchronous The previous value of the PWM control signal SQ1 32. The previous values of the first synchronous PWM control signal SQ1 32 are then locked to these previous values accordingly.

According to the embodiment shown in the right branch of FIG. 4 , the current I input to the synchronous rectification control unit 100 is an alternating current I _AC , that is, a non-rectified current. The method/algorithm/logic corresponding to the control algorithm circuit 27 of the right branch of FIG. 4 is also shown in the flip-flop circuit of FIG.

If the alternating current I _AC is here the measured synchronous rectification side circuit I _AC,sec 35 , then the synchronous rectification control unit is the synchronous rectification side unit 2 connected to the AC part of the synchronous rectification side 220 , as illustrated in FIG. 10 below.

Correspondingly, if the alternating current I _AC is here the measured asynchronous whole alternating current AC I _AC,prim 36, then the synchronous rectification control unit 100 is the asynchronous rectification side unit 3 connected to the AC part of the asynchronous rectification side 210, as follows As shown in Figure 10.

According to an embodiment, if the second voltage V2 29 has a logic high value and the second asynchronous PWM control signal Q231 has a logic high value, the control algorithm circuit 27, based on the inputted first and second asynchronous PWM control signals Q1 30 and Q2 31 and based on the first and second voltages V1 28 and V2 29 for generating and outputting a logic high value of the second synchronous PWM control signal SQ2 33 . The output logic high value of the second synchronous PWM control signal SQ2 33 is then latched to the logic high value.

According to an embodiment, if at least one of the second voltage V2 29 and the second asynchronous PWM control signal Q2 31 has a logic low value, and if the first voltage V1 28 has a logic high value or if the first asynchronous PWM control signal Q1 30 has a logic high value, then the control algorithm circuit 27, based on the inputted first and second asynchronous PWM control signals Q130 and Q2 31 and based on the first and second voltages V1 28 and V2 29, is used to generate and output The logic low value of the second synchronous PWM control signal SQ2 33. The output logic low value of the second synchronous PWM control signal SQ2 33 is then latched to the logic low value.

According to an embodiment, if at least one of the second voltage V2 29 and the second asynchronous PWM control signal Q2 31 has a logic low value, and if both the first voltage V1 28 and the first asynchronous PWM control signal Q1 30 have logic low value, the algorithm circuit 27 is controlled for generating and outputting a second synchronous PWM based on the inputted first and second asynchronous PWM control signals Q1 30 and Q2 31 and on the basis of the first and second voltages V1 28 and V2 29 The previous value of the PWM control signal SQ2 33. The previous values of the second synchronous PWM control signal SQ2 33 are then locked to these previous values accordingly.

6 is a graph containing curves showing example values and waveforms of the first and second asynchronous PWM control signals Q1 30 and Q2 31, the current for the alternating current I _{AC_rect} , the first and second non-synchronous PWM control signals Q1 30 and Q2 31 Two voltage pulses V1 28 and V229 and generated first and second synchronous PWM control signals SQ1 32 and SQ233 that can be used to control the switches of the power switches. The first and second synchronous PWM control signals SQ1 32 and SQ2 33 are generated here in accordance with the flowchart of FIG. 2 above.

FIG. 6 shows the operating conditions when the rectified alternating current I _{AC_rect} is continuous. According to the operating conditions shown in FIG. 6 , if the rectified continuous alternating current I _{AC_rect is} close to/close to zero and has a positive rate of change, the voltage pulse generation circuit 26 generates a first voltage pulse V1 28 . Alternatively, the voltage pulse generation circuit 26 generates a second voltage pulse V2 29 if the rectified continuous alternating current I _{AC_rect is} close to/close to zero and has a negative rate of change. As described above in connection with the flowchart in FIG. 2, a synchronous rectification control algorithm is used to generate the first and second synchronous PWM control signals SQ1 32 and SQ2 33 to turn the power switch on or off.

FIG. 7 is a graph containing curves showing example values and waveforms of first and second asynchronous PWM control signals Q1 30 and Q2 31 , the current that is the rectified alternating current I _{AC_rect} , the first and second voltage pulses V128 and V2 29 and generated first and second synchronous PWM control signals SQ132 and SQ2 33 that can be used to control the switches of the power switches. The first and second synchronous PWM control signals SQ1 32 and SQ2 33 are generated here in accordance with the flowchart of FIG. 2 above.

FIG. 7 shows the operating conditions when the rectified alternating current I _{AC_rect} is discontinuous. According to the operating conditions shown in FIG. 7 , if the rectified discontinuous alternating current I _{AC_rect is} close to/close to zero and has a positive rate of change, the voltage pulse generation circuit 26 generates a first voltage pulse V1 28 . Alternatively, if the rectified discontinuous alternating current IAC_rect is near/close to zero and has a negative rate of change, the voltage pulse generation circuit 26 generates a second voltage pulse V2 29 . As described above in connection with the flowchart in FIG. 2, a synchronous rectification control algorithm is used to generate the first and second synchronous PWM control signals SQ1 32 and SQ2 33 to turn the power switch on or off.

FIG. 8 is a graph containing curves showing example values and waveforms of first and second asynchronous PWM control signals Q1 30 and Q2 31 , current for alternating current IAC_rect, first and second The voltage pulses V1 28 and V2 29 and the generated first and second synchronous PWM control signals SQ1 32 and SQ2 33 that can be used to control the switches of the power switches. The first and second synchronous PWM control signals SQ1 32 and SQ2 33 are generated here according to the flow chart in FIG. 4 above.

Figure 8 shows the operating conditions when the alternating current IAC is continuous. According to the operating conditions presented in FIG. 8 , if the continuous alternating current IAC_rect is close to/close to zero and has a positive rate of change, the voltage pulse generation circuit 26 generates a first voltage pulse V1 28 . Alternatively, the voltage pulse generation circuit 26 generates a second voltage pulse V2 29 if the continuous alternating current IAC is near/close to zero and has a negative rate of change. As described above in connection with the flowchart in FIG. 4, a synchronous rectification control algorithm is used to generate the first and second synchronous PWM control signals SQ1 32 and SQ2 33 to turn the power switch on or off.

9 is a graph containing curves showing example values and waveforms of first and second asynchronous PWM control signals Q1 30 and Q2 31 , current for alternating current I _AC , first and second non-synchronous PWM control signals Q1 30 and Q2 31 Two voltage pulses V1 28 and V2 29 and generated first and second synchronous PWM control signals SQ1 32 and SQ2 33 that can be used to control the switches of the power switches. The first and second synchronous PWM control signals SQ1 32 and SQ2 33 are generated here according to the flowchart of FIG. 4 above.

Figure 9 shows the operating conditions when the alternating current I _AC is discontinuous. According to the operating conditions shown in FIG. 9, if the discontinuous alternating current I _AC is close to/close to zero and has a positive rate of change, the voltage pulse generation circuit 26 generates a first voltage pulse V128. Optionally, the voltage pulse generation circuit 26 generates a second voltage pulse V2 29 if the discontinuous alternating current I _AC is near/close to zero and has a negative rate of change. As described above in connection with the flowchart in FIG. 4, a synchronous rectification control algorithm is used to generate the first and second synchronous PWM control signals SQ1 32 and SQ2 33 to turn the power switch on or off.

As mentioned above, the synchronous rectification control unit 100 may be used to control power switches in substantially any circuit 200 that includes the power switch 50 . These circuits 200 include, for example, half-bridge power converters and full-bridge power converters.

FIG. 10 schematically illustrates one non-limiting example of a circuit diagram of a full-bridge power converter circuit 200 in which embodiments of the present invention may be implemented. It should be noted, however, that embodiments of the present invention may also be implemented in a number of other circuits including one or more power switches.

The circuit 200 in Figure 10 is thus a schematic illustration of a resonant switching power converter 200 including a synchronous rectification circuit. The resonant switching power converter 200 is divided into a primary side 210 and a secondary side 220 by the isolation transformer 18 . The primary side 210 may correspond to the asynchronous side 210 of the circuit in this example. The secondary side 220 may here correspond to the synchronous side 220 of the circuit.

The transformer 18 has a primary winding 181 of Np turns and a secondary winding 182 of Ns turns. The secondary side 220 of the resonant switching power converter here includes four asynchronous side power switches 13, 14, 15 and 16, which may be implemented using MOSFETs or other suitable transistors or the like. The primary 210 also includes a resonant circuit 17, which may include capacitors and inductors arranged in a well-known manner, and a capacitor 12 connected between the two primary terminals 10 and 11. The rectified AC voltage is input to the capacitor 12 . Therefore, the rectified AC voltage, ie the negative voltage value of the substitute voltage AC has been converted into a voltage corresponding to the positive voltage, connected to the terminals 10 and 11 .

The secondary side 220 of the converter includes four asynchronous side power switches 19, 20, 21 and 22, which may be implemented using MOSFETs or other suitable transistors or the like. The secondary side 220 is also included in a capacitor 25 which is connected between the two secondary side terminals 23 and 24 and is powered by the rectified AC voltage. Therefore, the rectified AC voltage is connected to terminals 23 and 24 .

The first asynchronous control signal Q1 30 drives the two asynchronous side power switches 13 and 16 during the first half of the switching cycle, so that the first asynchronous control signal Q1 30 has a logic high value, which means that the first asynchronous control The two asynchronous side power switches driven by signal Q130 are turned on. During the second half of the switching cycle, the first asynchronous control signal Q1 30 has a logic low value, which means that the two asynchronous side power switches driven by the first asynchronous control signal Q1 30 are turned off.

The second asynchronous control signal Q2 31 drives the two asynchronous side power switches 14 and 15 during the first half of the switching period/cycle, so that the second asynchronous control signal Q2 31 has a logic low value, which means that the second asynchronous control signal Q2 31 has a logic low value. The two power switches driven by the synchronization control signal Q2 31 are turned off. During the second half of the switching cycle, the second asynchronous control signal Q231 has a logic high value, which means that the two power switches driven by the second asynchronous control signal Q231 are turned on.

Dead time is introduced between the first and second asynchronous control signals Q1 and Q2 to prevent current breakdown in the circuit, ie a short circuit due to turning on multiple power switches simultaneously. In this document, dead time may be defined as the time period when both the first and second asynchronous control signals Q1 and Q2 have logic low values. Accordingly, the dead time may be defined as a time period when both the first and second synchronization control signals SQ1 and SQ2 have logic low values.

On the secondary/sync side 220, the first sync control signal SQ1 32 drives the two sync side power switches 19 and 22, while the second sync control signal SQ2 33 drives the power switches 20 and 21 in a corresponding manner, likewise the first non- The synchronous control signal Q1 30 and the second asynchronous control signal Q2 31 drive four asynchronous power switches.

Therefore, the first synchronization control signal SQ1 32 drives the two synchronization side power switches 19 and 22 in the first half of the switching cycle, so that the first synchronization control signal SQ1 32 has a logic high value, which means that the first synchronization control signal SQ132 The two asynchronous side power switches of the drive are turned on. During the second half of the switching cycle, the first synchronization control signal SQ132 has a logic low value, which means that the two synchronization side power switches driven by the first synchronization control signal SQ132 are turned off.

The second synchronization control signal SQ2 33 drives the two synchronization side power switches 20 and 21 during the first half of the switching cycle, so that the second synchronization control signal SQ2 33 has a logic low value, which means that the second synchronization control signal SQ2 33 is driven by the second synchronization control signal SQ2 33 The two power switches are turned off. During the second half of the switching cycle, the second synchronization control signal SQ2 33 has a logic high value, which means that the two power switches driven by the second synchronization control signal SQ2 33 are turned on.

Dead time is introduced between the first and second synchronization control signals SQ1 and SQ2 to prevent current breakdown.

The synchronous rectification control unit 100 can be implemented in different locations/places in the full-bridge power converter circuit 200 shown in FIG. 10 according to the different embodiments described above.

According to an embodiment, the synchronous rectification control unit 100 is connected to the rectified AC bus of the synchronous rectification side 220 between the power switches 19 , 20 , 21 , 22 and the capacitor 25 , also referred to as the DC bus, that is, on the rectified AC part . The synchronous rectification control unit 100 is thus subsequently denoted 1 in FIG. 10 and placed between points 37 and 38 of FIG. 1 . Here, the current I input to the synchronous rectification control unit 1 is the rectified AC current I _{AC_rect} 34 , which may be continuous or discontinuous, as described above for the rectified alternating current I _{AC_rect} .

According to another embodiment, the synchronous rectification control unit 100 is connected to the AC part of the synchronous rectification side 220 between the transformer 18 and the two power switches 21 and 22 . The synchronous rectification control unit 100 is thus subsequently denoted 2 in FIG. 10 . Here, the current I input to the synchronous rectification control unit 2 is the synchronous alternating current AC I _AC,sec 35 , which may be continuous or discontinuous, as described above for the alternating current I _AC . Therefore, if the alternating current I _AC as the input of the synchronous rectification control unit 100 is the measured synchronous rectification side current, then the synchronous rectification control unit is the synchronous rectification side unit 2 .

According to another embodiment, the synchronous rectification control unit 100 is connected to the AC part of the asynchronous rectification side 210 between the resonant circuit 17 and the transformer 18 . The synchronous rectification control unit 100 is thus subsequently designated 3 in FIG. 10 . Here, the current I measured by the synchronous rectification control unit 3 is the asynchronous alternating current AC I _AC,prim 36 , which may be continuous or discontinuous, as described above for the alternating current I _AC . In the full bridge converter circuit 200, the non-synchronous alternating current AC I _AC,prim 36 may be the mirror waveform of the synchronous alternating current AC I _AC,sec 35 .

The synchronous rectification control units 1, 2, 3 according to these embodiments of the present invention may correspond to any of the embodiments disclosed in this document, provided they have suitable input currents. Therefore, the operation of the internal structure of the synchronous rectification control unit 100 described above is also valid for each of the synchronous _{rectification} control units 1, 2, 3 disclosed in FIG. rectification control unit 1, when the synchronous side alternating current I _AC,sec 35 is input to the synchronous rectification control unit 2, or when the asynchronous side alternating current I _AC,prim 36 is input to the synchronous rectification control unit 3.

FIG. 11 is a flowchart illustrating a synchronous rectification control method 300 .

It should be noted, however, that any, some or all of the described actions 301-303 may be performed in a slightly different chronological order than indicated by the enumeration, concurrently, or even in the reverse order. Additionally, note that some actions may be performed in a number of alternative ways, according to different embodiments. Method 300 may include the following actions:

Action 301

In a first action 301, the current I in the circuit 100 including the power switch 50 is measured.

Action 302

In the second action 302, if the positive rate of change of the current I is close to the value 0 of the current I, a logic high value of the first voltage V128 is output.

Alternatively, if the negative rate of change of the current I is close to the value 0 of the current I, a logic high value of the second voltage V2 29 is output.

Action 303

In a third act 303, based on the first and second asynchronous pulse width modulation (PWM) control signals Q1 30 and Q2 31, and based on the first voltage V1 28 and the second voltage V2 29, a first and The second synchronous PWM control signals SQ1 32 and SQ2 33. The generated first and second synchronous PWM control signals SQ132 and SQ2 33 may then be used to control the switching of power switch 50 in circuit 200 .

Additionally, the synchronous rectification control method may be implemented in the circuit 400 schematically illustrated in FIG. 12 . Processing circuit 400 may be used to:

measuring 301 the current I in the circuit 100 including the power switch 50;

If the positive rate of change of the current I is close to the value 0 of the current I, then output 302 a logic high value of the first voltage V1 28, or

outputting 302 a logic high value of the second voltage V2 29 if the negative rate of change of the current I is close to the value 0 of the current I; and

Based on the first and second asynchronous pulse width modulation (PWM) control signals Q1 30 and Q2 31, and based on the first voltage V1 28 and the second voltage V2 29, generating 303 the first and second synchronous PWM control signals Signals SQ1 32 and SQ2 33. These first and second synchronous PWM control signals SQ1 32 and SQ2 33 may be used to control the switching of the power switch 50 .

The processing circuit 400 may include, for example, a central processing unit (CPU), a processing unit, a processing circuit, a processor, an application specific integrated circuit (ASIC), a microprocessor, or other devices capable of parsing and executing instructions. One or more instances of processing logic. Therefore, the expression "processing circuit" as used herein may mean a processing circuit comprising a plurality of processing circuits, such as any, some or all of the items enumerated above.

Processing circuitry 400 also performs data processing functions for data input, output, and processing including data buffering, as well as device control functions.

According to some embodiments, the processing circuit 400 may be connected to at least one memory 401 . Memory 401 may include physical devices for temporarily or permanently storing data or programs, ie, sequences of instructions. According to some embodiments, memory 401 may include an integrated circuit containing silicon-based transistors. Additionally, memory 401 may be volatile or non-volatile.

Actions 301-303 previously described may be performed by one or more processing circuits 400 together with computer program code that performs the functions of actions 301-303. Therefore, a computer program product comprising instructions to perform actions 301 to 303, when loaded into the processing circuit 400, can perform the synchronous rectification control method 300.

For example, the computer program product described above may be provided in the form of a data carrier carrying computer program code for performing the steps of actions 301 to 303 according to some embodiments when it is loaded into the processing circuit 400 . Any, at least some, or all actions. The data carrier may be, for example, a hard disk, a CD-ROM disc, a memory stick, an optical storage device, a magnetic storage device or any other suitable medium, such as a magnetic disk or magnetic tape which can hold machine-readable data in a non-transitory manner. Additionally, the computer program product may be provided as computer program code on a server and may be downloaded remotely via the Internet or an intranet connection or the like.

The terminology used in the detailed description of the embodiments as illustrated in the drawings is not intended to limit the described method 300 and/or synchronous rectification control unit 100, which is instead limited by the appended claims.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. In addition, the singular forms "a" and "the" are construed as "at least one" and thus may also include a plurality of entities of a certain class, unless expressly stated otherwise. It will be further understood that the terms "comprising", "comprising", "containing" and/or "consisting of" are used to describe the presence of stated features, acts, integers, steps, operations, elements and/or components, but not The presence or addition of one or more other features, acts, integers, steps, operations, elements, components and/or combinations thereof is excluded.

Claims (4)

1. a synchronous rectification control unit, is characterized in that, comprises: Voltage pulse generation circuit for: measuring the current I in the circuit including the power switch, the current I being the rectified alternating current I _{AC_rect} or the alternating current I _AC ; If the positive rate of change of the current I is close to the value 0 of the current I, outputting a logic high value of the first voltage V1; and If the positive rate of change of the current I is away from the value 0 of the current I, outputting a logic low value of the first voltage V1; and If the negative rate of change of the current I is close to the value 0 of the current I, outputting a logic high value of the second voltage V2; and If the negative change rate of the current I is far from the value 0 of the current I, a logic low value of the second voltage V2 is output; a control algorithm circuit for: generating first synchronous PWM control signals SQ1 and A second synchronous PWM control signal SQ2, the first and second synchronous PWM control signals SQ1 and SQ2 may be used to control the switching of the power switch, wherein when the first synchronous PWM control signal SQ1 or the second synchronous PWM control signal SQ1 When the PWM control signal SQ2 has a logic high value, it is turned on by the power switch; when the first synchronous PWM control signal SQ1 or the second synchronous PWM control signal SQ2 has a logic low value, it is turned on by the power switch is closed; The control algorithm circuit is specifically used for: if at least one of the first voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and if the second voltage V2 has a logic high value or if the second asynchronous PWM control signal Q2 has a logic high value, then a logic low value of the first synchronous PWM control signal SQ1 is generated; or If at least one of the first voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and both the second voltage V2 and the second asynchronous PWM control signal Q2 have a logic low value , the previous value of the first synchronous PWM control signal SQ1 is generated, and the previous value of the first synchronous PWM control signal SQ1 is the value of the first synchronous PWM control signal SQ1 generated last time; or if the first voltage V1 and the second asynchronous PWM control signal Q2 have a logic high value, generating a logic high value of the second synchronous PWM control signal SQ2; or if at least one of the first voltage V1 and the second asynchronous PWM control signal Q2 has a logic low value, and if the second voltage V2 has a logic high value or if the first asynchronous PWM control signal Q1 has a logic high value, then a logic low value of the second synchronous PWM control signal SQ2 is generated; or If at least one of the first voltage V1 and the second asynchronous PWM control signal Q2 has a logic low value, and both the second voltage V2 and the first asynchronous PWM control signal Q1 have a logic low value , then the previous value of the second synchronous PWM control signal SQ2 is generated, and the previous value of the second synchronous PWM control signal SQ2 is the old value of the second synchronous PWM control signal SQ2; or if at least one of the second voltage V2 and the second asynchronous PWM control signal Q2 has a logic low value, and if the first voltage V1 has a logic high value or if the first asynchronous PWM control signal Q1 has a logic high value, then a logic low value of the second synchronous PWM control signal SQ2 is generated; or If at least one of the second voltage V2 and the second asynchronous PWM control signal Q2 has a logic low value, and both the first voltage V1 and the first asynchronous PWM control signal Q1 have a logic low value , the previous value of the second synchronous PWM control signal SQ2 is generated, and the previous value of the second synchronous PWM control signal SQ2 is the old value of the second synchronous PWM control signal SQ2. 2. An integrated circuit, comprising at least one synchronous rectification control unit according to claim 1. 3 . A power electronic device with a power converter, wherein the power converter comprises the synchronous rectification control unit according to claim 1 . 4 . 4. a synchronous rectification control method, is characterized in that, comprises: measuring the current I in the circuit including the power switch, the current I being the rectified alternating current I _{AC_rect} or the alternating current I _AC ; If the positive rate of change of the current I is close to the value 0 of the current I, a logic high value of the first voltage V1 is output, or A logic low value of the first voltage V1 is output if the positive rate of change of the current I is away from the value 0 of the current I, or If the negative rate of change of the current I is close to the value 0 of the current I, output (302) a logic high value of the second voltage V2, or If the negative change rate of the current I is far from the value 0 of the current I, a logic low value of the second voltage V2 is output; as well as A first synchronous PWM control signal SQ1 and a second synchronous PWM control signal SQ2 are generated based on the first and second asynchronous pulse width modulated PWM control signals Q1 and Q2, and based on the first voltage V1 and the second voltage V2 , the first and second synchronous PWM control signals SQ1 and SQ2 can be used to control the switching of the power switch, wherein when the first synchronous PWM control signal SQ1 or the second synchronous PWM control signal SQ2 has a logic high value, the power switch is turned on; when the first synchronous PWM control signal SQ1 or the second synchronous PWM control signal SQ2 has a logic low value, the power switch is turned off; The method also includes: if at least one of the first voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and if the second voltage V2 has a logic high value or if the second asynchronous PWM control signal Q2 has a logic high value, then a logic low value of the first synchronous PWM control signal SQ1 is generated; or If at least one of the first voltage V1 and the first asynchronous PWM control signal Q1 has a logic low value, and both the second voltage V2 and the second asynchronous PWM control signal Q2 have a logic low value , the previous value of the first synchronous PWM control signal SQ1 is generated, and the previous value of the first synchronous PWM control signal SQ1 is the value of the first synchronous PWM control signal SQ1 generated last time; or if the first voltage V1 and the second asynchronous PWM control signal Q2 have a logic high value, generating a logic high value of the second synchronous PWM control signal SQ2; or if at least one of the first voltage V1 and the second asynchronous PWM control signal Q2 has a logic low value, and if the second voltage V2 has a logic high value or if the first asynchronous PWM control signal Q1 has a logic high value, then a logic low value of the second synchronous PWM control signal SQ2 is generated; or If at least one of the first voltage V1 and the second asynchronous PWM control signal Q2 has a logic low value, and both the second voltage V2 and the first asynchronous PWM control signal Q1 have a logic low value , then the previous value of the second synchronous PWM control signal SQ2 is generated, and the previous value of the second synchronous PWM control signal SQ2 is the old value of the second synchronous PWM control signal SQ2; or if at least one of the second voltage V2 and the second asynchronous PWM control signal Q2 has a logic low value, and if the first voltage V1 has a logic high value or if the first asynchronous PWM control signal Q1 has a logic high value, then a logic low value of the second synchronous PWM control signal SQ2 is generated; or If at least one of the second voltage V2 and the second asynchronous PWM control signal Q2 has a logic low value, and both the first voltage V1 and the first asynchronous PWM control signal Q1 have a logic low value , the previous value of the second synchronous PWM control signal SQ2 is generated, and the previous value of the second synchronous PWM control signal SQ2 is the old value of the second synchronous PWM control signal SQ2.

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