CN106847325A - Primary particle inversion resistant memory cell - Google Patents

Abstract

The invention relates to a single-event flip-resistant storage unit, which relates to the field of anti-radiation hardening of integrated circuits. Solved the problem that radiation particles flipped the information stored in the memory, thereby reducing the reliability of the memory. The present invention consists of 10 MOS transistors, which are respectively PMOS transistors P1 and P2 and NMOS transistors N1, N2, N3, N4, N5, N6, N7 and N8. The present invention can strengthen the flipping of any single node in the storage unit, and can also implement anti-multi-node flipping and fault tolerance for two fixed nodes without depending on the stored value at the same time. The invention is mainly used for strengthening and protecting the memory against single event reversal.

Description

Memory cell resistant to single event upset

technical field

The invention relates to the field of anti-radiation hardening of integrated circuits.

Background technique

With the continuous development of semiconductor technology, radiation particles in the natural and cosmic environment will more easily flip the information stored in the memory, resulting in the occurrence of single event flipping, thereby reducing the reliability of the memory. Therefore, in the design of modern integrated circuit memory, it needs to be protected against single event upset.

Contents of the invention

The purpose of the present invention is to solve the problem that the information stored in the memory is reversed by radiation particles, thus reducing the reliability of the memory. The invention provides a storage unit resistant to single event reversal.

A storage unit resistant to single event upset, which includes 2 PMOS transistors and 8 NMOS transistors, the 2 PMOS transistors are respectively transistors P1 and P2, and the 8 NMOS transistors are respectively transistors N1 to N8;

The source of the transistor P2, the source of the transistor P1, the drain of the transistor N5 and the drain of the transistor N6 are all connected to the power supply,

The drain of the transistor P2 is connected to the gate of the transistor P1, the gate of the transistor N6, and the drain of the transistor N2 at the same time, and the intersection of the drain of the transistor P2 and the gate of the transistor P1 is a node C,

The gate of the transistor P2 is connected to the drain of the transistor P1, the drain of the transistor N4 and the gate of the transistor N5 at the same time, and the intersection of the drain of the transistor P1 and the gate of the transistor N5 is a node D,

The source of the transistor N6 is connected to the source of the transistor N8, the gate of the transistor N4, the drain of the transistor N3 and the gate of the transistor N1, and the intersection of the gate of the transistor N4 and the drain of the transistor N3 is the storage unit output node A ,

The source of the transistor N4 is grounded simultaneously with the source of the transistor N3, the source of the transistor N1 and the source of the transistor N2,

The source of the transistor N5 is connected to the source of the transistor N7, the gate of the transistor N3, the drain of the transistor N1 and the gate of the transistor N2, and the intersection of the gate of the transistor N2 and the drain of the transistor N1 is the storage unit output node B ,

Both the gates of the transistor N7 and the gates of the transistor N8 receive a signal for controlling the switching operation through the word line WL,

The drain of transistor N7 is connected to bit line BLN, and the drain of transistor N8 is connected to bit line BL.

When the level of node A is "1", the level of node B is "0", the level of node C is "1", and the level of node D is "0", the storage unit is in the storage operation state The specific process is: when the word line WL is at a low level "0", the transistors N4, N6, N1 and P2 are in the on state, and the remaining transistors are in the off state. In this case, the storage of the memory cell is completed. operate.

When the level of node A is "1", the level of node B is "0", the level of node C is "1", and the level of node D is "0", the storage unit performs a read operation The specific process is:

First, the bit lines BL and BLN are precharged to VDD. When the word line WL is at a high level "1", node A maintains a high level "1" state, and node B maintains a low level "0" state. Line BLN is discharged through transistors N1 and N7;

Then, the amplifier in the peripheral circuit will output the state of the memory cell according to the voltage difference between the two bit lines BL and BLN, thereby completing the read operation of the memory cell.

When the level of node A is "1", the level of node B is "0", the level of node C is "1", and the level of node D is "0", the storage unit performs a write operation The specific process is:

Pull down the bit line BL to a low level "0", and pull up the bit line BLN to a high level "1". When the word line WL is at a high level "1", the transistors N7 and N8 are in a conducting state , node A is pulled down to low level "0", node B is pulled up to high level "1", at this time, transistors P1, N2, N3 and N5 are in the conduction state, transistors N4, N6, N1 and P2 , in an off state, when the word line WL returns to a low level "0", all nodes are in a stable state, thereby completing the write operation of the memory cell.

The beneficial effect brought by the present invention is that, in the present invention, an anti-single event inversion storage unit is mainly designed by using 10 transistors to strengthen the anti-single event inversion. Aiming at the single event upset effect, the present invention utilizes the physical mechanism of the single event upset to design a novel anti-single event upset storage unit, which has the advantages of small area, low power consumption and less impact on memory performance. Since the storage unit belongs to a latch, this hardened design is also a latch hardened design against single event flipping.

Description of drawings

FIG. 1 is a memory cell resistant to single event turnover according to the present invention.

detailed description

Specific Embodiment 1: Referring to FIG. 1 to illustrate this embodiment, the anti-single event reversal memory unit described in this embodiment includes 2 PMOS transistors and 8 NMOS transistors, and the 2 PMOS transistors are respectively transistor P1 and P2, the 8 NMOS transistors are respectively transistors N1 to N8;

The source of the transistor P2, the source of the transistor P1, the drain of the transistor N5 and the drain of the transistor N6 are all connected to the power supply,

The drain of the transistor P2 is connected to the gate of the transistor P1, the gate of the transistor N6, and the drain of the transistor N2 at the same time, and the intersection of the drain of the transistor P2 and the gate of the transistor P1 is a node C,

The gate of the transistor P2 is connected to the drain of the transistor P1, the drain of the transistor N4 and the gate of the transistor N5 at the same time, and the intersection of the drain of the transistor P1 and the gate of the transistor N5 is a node D,

The source of the transistor N6 is connected to the source of the transistor N8, the gate of the transistor N4, the drain of the transistor N3 and the gate of the transistor N1, and the intersection of the gate of the transistor N4 and the drain of the transistor N3 is the storage unit output node A ,

The source of the transistor N4 is grounded simultaneously with the source of the transistor N3, the source of the transistor N1 and the source of the transistor N2,

The source of the transistor N5 is connected to the source of the transistor N7, the gate of the transistor N3, the drain of the transistor N1 and the gate of the transistor N2, and the intersection of the gate of the transistor N2 and the drain of the transistor N1 is the storage unit output node B ,

Both the gates of the transistor N7 and the gates of the transistor N8 receive a signal for controlling the switching operation through the word line WL,

The drain of transistor N7 is connected to bit line BLN, and the drain of transistor N8 is connected to bit line BL.

In this implementation manner, in order to improve the reliability of the SRAM in spaceflight and natural radiation environments, a reinforced design for anti-single event upset of the storage unit is carried out. The invention can carry out fault-tolerant recovery for the single-node flip and multi-node flip of the storage unit. The present invention consists of 10 MOS transistors, which are respectively PMOS transistors P1 and P2 and NMOS transistors N1, N2, N3, N4, N5, N6, N7 and N8. The present invention can strengthen the flipping of any single node in the storage unit, and can also implement anti-multi-node flipping and fault tolerance for two fixed nodes without depending on the stored value at the same time.

Specific embodiment 2: Refer to FIG. 1 to illustrate this embodiment. The difference between this embodiment and the anti-single event upset memory cell described in Embodiment 1 is that when the level of node A is "1" and the voltage of node B is When level is "0", the level of node C is "1", and the level of node D is "0", the specific process that the memory cell is in the storage operation state is: when the word line WL is low level "0" ", the transistors N4, N6, N1 and P2 are in the on state, and the rest of the transistors are in the off state. In this case, the storage operation of the memory cell is completed.

Specific embodiment 3: Refer to FIG. 1 to illustrate this embodiment. The difference between this embodiment and the anti-single event upset memory cell described in Embodiment 1 is that when the level of node A is "1" and the voltage of node B When the level is "0", the level of the node C is "1", and the level of the node D is "0", the specific process for the memory unit to perform the read operation is as follows:

First, the bit lines BL and BLN are precharged to VDD. When the word line WL is at a high level "1", node A maintains a high level "1" state, and node B maintains a low level "0" state. Line BLN is discharged through transistors N1 and N7;

Then, the amplifier in the peripheral circuit will output the state of the memory cell according to the voltage difference between the two bit lines BL and BLN, thereby completing the read operation of the memory cell.

Embodiment 4: Refer to FIG. 1 to illustrate this embodiment. The difference between this embodiment and the anti-single event upset memory cell described in Embodiment 1 is that when the level of node A is "1" and the voltage of node B When the level is "0", the level of the node C is "1", and the level of the node D is "0", the specific process of the write operation of the storage unit is as follows:

Pull down the bit line BL to a low level "0", and pull up the bit line BLN to a high level "1". When the word line WL is at a high level "1", the transistors N7 and N8 are in a conducting state , node A is pulled down to low level "0", node B is pulled up to high level "1", at this time, transistors P1, N2, N3 and N5 are in the conduction state, transistors N4, N6, N1 and P2 , in an off state, when the word line WL returns to a low level "0", all nodes are in a stable state, thereby completing the write operation of the memory cell.

The state of the anti-single event flip memory unit of the present invention includes two states, one is: the level of node A is "1", the level of node B is "0", and the level of node C is "1". ", the level of node D is "0"; the other is: the level of node A is "0", the level of node B is "1", the level of node C is "0", the level of node D is The level is "1". Among them, when the level of node A is "0", the level of node B is "1", the level of node C is "0", and the level of node D is "1", the storage unit performs storage operation, read The specific process of operation and write operation is the same as when the level of node A is "0", the level of node B is "1", the level of node C is "0", and the level of node D is "1". The process of storage operation, read operation and write operation of the storage unit is reversed.

Based on the physical mechanism of single event inversion, when a radiation particle bombards a PMOS transistor, only a positive transient voltage pulse can be generated; when it bombards an NMOS transistor, only a negative transient voltage pulse can be generated. Therefore, node B is not a sensitive node for this state since it is not connected to the gate/drain of the PMOS transistor. Considering the given state A=1, B=0, C=1, D=0 in Fig. 1, the sensitive nodes are nodes A, C and D. In another storage state, that is, A=0, B=1, C=0 and D=1 states, sensitive nodes are nodes B, C and D.

In the multi-node flipping phenomenon caused by charge sharing, the charge sharing of two redundant nodes will not cause effective changes in the state of the memory. Therefore, the present invention mainly considers the anti Single-node overturn reinforcement and two sensitive nodes C and D are anti-multi-node overturn reinforcement.

Taking A=1, B=0, C=1, and D=0 as examples, the anti-radiation performance analysis of the anti-single event flipping storage unit according to the present invention is as follows:

1. Assuming that node A is flipped to "0" state, it will turn off transistors N1 and N4, and nodes B, C and D will maintain their original states, so the remaining transistors still maintain their original on or off states. For example, transistor N6 will remain on. Therefore, node A will revert to the original "1" state.

2. When the node C flips to "0", the transistors P1 and N6 will be turned on and off respectively. Node D will be affected, its value will be "1", and transistor P2 will be temporarily turned off. However, since the width-to-length ratio of transistor N4 is greater than that of transistor P1, the affected node D will quickly be pulled back to the original low level; therefore, transistor N5 will always be turned off, and node B will not will not be affected. At the same time, the transistor N4 remains on because the node A has not changed, and then the transistor P2 will turn back on, and the node C is restored to its original "1" state.

3. When the node D is flipped, the transistor P2 is turned off, and the transistor N5 is temporarily turned on. However, since the width-to-length ratio of transistor N4 is greater than that of transistor P1, and transistor N4 remains on since node A has not changed, the affected node D will quickly be pulled back to its original low level.

4. Nodes C and D may be affected due to the charge sharing effect. At this time, its state is the same as that of node C being flipped, so through similar analysis, it can be found that both node C and node D will return to their original state.

Correspondingly, if the designed storage unit is in another state, that is, A=0, B=1, C=0 and D=1, the multi-node forwarding at nodes C and D will also be restored. Therefore, nodes C and D are two fixed nodes recoverable from multi-node rollover, and these two nodes are independent of the value stored in the memory.

5. When node A-C or A-D has multi-node inversion, transistor N4 will be turned off, so node C or node D will not return to the original state. At this point, the stored state is flipped.

Therefore, in order to minimize the possibility of node A-C (B-C) or A-D (B-D) multi-node flipping, it is necessary to reasonably consider the layout topology in the layout design. Therefore, when drawing the layout, nodes A, B, and C-D can be drawn relatively far apart in terms of the physical distance of the layout.

Claims (4)

1. primary particle inversion resistant memory cell, it is characterised in that it includes 2 PMOS transistors and 8 nmos pass transistors, institute The 2 PMOS transistors respectively transistor P1 and P2 for stating, 8 nmos pass transistors are respectively transistor N1 to N8；

The source electrode of transistor P2, the source electrode of transistor P1, the drain electrode of transistor N5 and the drain electrode of transistor N6 connect power supply,

The grid of the drain electrode of transistor P2 and transistor P1, the grid of transistor N6, the drain electrode of transistor N2 are connected simultaneously, crystal The drain electrode of pipe P2 is node C with the intersection point of the grid of transistor P1,

The grid of transistor P2 is connected simultaneously with the grid of the drain electrode, the drain electrode of transistor N4 and transistor N5 of transistor P1, brilliant The drain electrode of body pipe P1 is node D with the intersection point of the grid of transistor N5,

The source electrode of transistor N6 and the grid of transistor N8 source electrodes, the grid of transistor N4, the drain electrode of transistor N3 and transistor N1 Pole connects simultaneously, and the grid of transistor N4 is memory cell output node A with the intersection point of the drain electrode of transistor N3,

The source electrode of transistor N4 is grounded simultaneously with the source electrode of the source electrode, the source electrode of transistor N1 and transistor N2 of transistor N3,

The source electrode of transistor N5 and the grid of transistor N7 source electrodes, the grid of transistor N3, the drain electrode of transistor N1 and transistor N2 Pole connects simultaneously, and the grid of transistor N2 is memory cell output node B with the intersection point of the drain electrode of transistor N1,

The grid of transistor N7 and the grid of transistor N8 receive the signal of controlling switch operation by wordline WL,

The drain electrode of transistor N7 is connected with bit line BLN, and the drain electrode of transistor N8 is connected with bit line BL.

2. primary particle inversion resistant memory cell according to claim 1, it is characterised in that when the level of node A is When the level that the level of " 1 ", node B is " 0 ", the level of node C is " 1 ", node D is for " 0 ", the memory cell is in and deposits behaviour The detailed process for making state is：When wordline WL is low level " 0 ", transistor N4, N6, N1 and P2 are in ON state, are left Transistor all in OFF state, in the case of this kind, complete memory cell and deposit operation.

3. primary particle inversion resistant memory cell according to claim 1, it is characterised in that when the level of node A is When the level that the level of " 1 ", node B is " 0 ", the level of node C is " 1 ", node D is for " 0 ", the memory cell carries out reading behaviour The detailed process of work is：

First, bit line BL and BLN are precharged to VDD, and when wordline WL is high level " 1 ", node A keeps high level One state, node B keeps low level " 0 " state, and bit line BLN is discharged by transistor N1 and N7；

Then, the amplifier in peripheral circuit is by according to the voltage difference between two bit lines BL and BLN, by the state of memory cell Output, so as to complete the read operation of memory cell.

4. primary particle inversion resistant memory cell according to claim 1, it is characterised in that when the level of node A is When the level that the level of " 1 ", node B is " 0 ", the level of node C is " 1 ", node D is for " 0 ", the memory cell enters row write behaviour The detailed process of work is：

Bit line BL is pulled down into low level " 0 ", while bit line BLN is pulled upward to high level " 1 ", when wordline WL is high level " 1 " When, the state that transistor N7 and N8 are on, node A pulled down to low level " 0 ", and node B is essentially pulled up to high level " 1 ", Now, transistor P1, N2, N3 and N5 is on state, and transistor N4, N6, N1 and P2 are closed, when wordline WL is returned During to low level " 0 ", all nodes are in stable state, so as to complete the write operation of memory cell.