CN106887434B - Three-dimensional memory element - Google Patents

Abstract

The present invention discloses a three-dimensional memory element, including a multi-layer stack structure, the multi-layer stack structure including a plurality of conductive strips and a plurality of channels to define a first, a second, a third and a fourth ridge stack; a first serial selection line switch located on the first ridge stack; a first ground selection line switch located on the second ridge stack; a first U-shaped memory cell series, the first serial selection line switch and the first ground selection line switch connected in series; a second serial selection line switch located on the third ridge stack; a second ground selection line switch located on the fourth ridge stack; a second U-shaped memory cell series, the second serial selection line switch and the second ground selection line switch connected in series. A first word line contact structure contacts the conductive strip of the first ridge stack. A second word line contact structure contacts the conductive strip of the second ridge stack; and a third word line contact structure contacts the conductive strips of the third and fourth ridge stacks.

Description

3D memory element

technical field

The present invention relates to a high density memory element. In particular, a three-dimensional (Three Dimemsional, 3D) memory element.

Background technique

Non-volatile memory elements, such as flash memory, have the property of not losing information stored in memory cells when power is removed. It has been widely used in solid-state mass storage applications for portable music players, mobile phones, digital cameras, etc. In order to meet the demand for higher density storage capacity, there are various three-dimensional memory devices with different structures, such as single-gate memory cells, double gate memory cells, and wrap-around gates. A three-dimensional flash memory device with surrounding gate memory cells is proposed.

A typical three-dimensional non-volatile memory device includes a plurality of three-dimensional arrays of memory cells with vertical channels built into multi-layer stacks. Taking a single-gate vertical channel (SGVC) NAND memory device with a U-shaped memory cell serial structure as an example, a stacked conductive strip made of polysilicon is generally used as the gate of the memory cell. Due to the high resistance of polysilicon, when constructing a memory cell array, it is necessary to separate the conductive strips into multiple sections, and pass the stepped word line contact structure word line contact structure to connect the conductive strips located at the same level. It is electrically connected to the metal word lines located above the memory cell array.

Because the word line contact structure occupies a relatively large area of the memory element, and the wiring space for accommodating the metal word lines above the memory cell array is limited. With the expansion of the memory capacity of the memory element, the number of conductive strip layers in the multi-layered layer structure is relatively increased, and more word lines and word line contact structures need to be provided. At present, it can only be dealt with by reducing the line diameter and pitch of the word lines, or increasing the area size of the memory block.

However, shrinking the wire diameter and spacing of the word lines will reduce the process window and yield, thereby greatly increasing the process cost, and even causing oxide breakdown. Increasing the area size of the memory block does not conform to the current trend of device scaling.

Therefore, there is a need to provide an advanced memory device that solves the problems faced by the above-mentioned technologies.

SUMMARY OF THE INVENTION

An embodiment of the present specification provides a three-dimensional memory device. The three-dimensional memory element includes: multi-layer stacks, a first String Select Line (SSL) switch, a first Ground Selection Line (GSL) switch, and a second String Select Line (SSL) switch. A select line switch, a second ground select line switch, a first U-shaped memory cell string, a second U-shaped memory cell string, a first word line contact structure, a second word line contact structure, and a third word line contact structure. The multilayer stack structure includes a plurality of conductive strips and a plurality of trenches isolated from each other to define at least a first ridge stack, a second ridge stack, and a third ridge stack layer and a fourth ridged stack. A first serial select line switch is located over the first ridged stack. The first ground select line switch is located over the second ridged stack. The first U-shaped memory unit is serially connected to the first serial selection line switch and the first ground selection line switch. The second serial select line switch is located over the third ridged stack. The second ground select line switch is located over the fourth ridged stack. The second U-shaped memory unit is serially connected to the second serial selection line switch and the second ground selection line switch. The first word line contact structure is in contact with the conductive strip on the first ridge stack. The second wordline contact structure is in contact with the conductive strips on the second ridge stack; the third wordline contact structure is in contact with the conductive strips on the third and fourth ridge stacks.

In accordance with the above-described embodiments, the present specification provides a three-dimensional memory element having a plurality of ridge stacks, wherein each ridge stack includes, respectively, a serial select line switch or a ground select line switch on top, and A plurality of memory cells located below the serial select line switch or the ground select line switch. The first string select line switch and the first ground select line switch are connected in series on the two ridge stacks, and the memory cells are located under the first string select line switch and the first ground select line switch. a U-shaped memory cell string; simultaneously by connecting in series a second string select line switch and a second ground select line switch on two other different ridge stacks, and a second string select line switch and a second The memory cells below the select line switch are grounded to form a second U-shaped string of memory cells.

Wherein, the memory cells located under the first serial selection line switch of the first U-shaped memory cell series are connected to the first word line contact structure; they are located under the second serial selection line switch of the second U-shaped memory cell series. The memory cells are connected to the second word line contact structure; and the memory cells located under the first ground select line switches of the first U-shaped memory cell series and the second ground select line switches of the second U-shaped memory cell series The lower memory cells are then connected to the same third word line contact structure. In other words, in the three-dimensional memory element, the number of word line contact structures used to connect memory cells located under the ground select switch is smaller than the number of word line contact structures used to connect memory cells located under the serial select switch. Compared with the three-dimensional memory element in the prior art, the arrangement of the word line contact structure can be reduced without changing the memory capacity.

By reducing the arrangement of the word line contact structure, the area size of the memory element can be reduced; moreover, the memory capacity of the memory element can be expanded without affecting the process margin, the process cost can be greatly reduced, and the oxide layer breakdown can be prevented. Increase the process yield of vertical channel memory devices.

Description of drawings

Other objects, features and advantages of the present invention can be seen in the following embodiments and the scope of claims, and in conjunction with the accompanying drawings, are described in detail as follows:

1A to 1D are partial structural perspective views of a single-gate vertical channel NAND memory device according to the prior art;

2 is a partial structural top view of the single-gate vertical channel NAND memory device depicted in FIG. 1D;

3 is a top view of a partial structure of a single-gate vertical channel NAND memory device according to another embodiment of the present invention;

4 is an equivalent circuit diagram illustrating a program operation with the single-gate vertical channel NAND memory device of FIG. 1C;

5 is an equivalent circuit diagram illustrating a read operation with the single-gate vertical channel NAND memory device of FIG. 1C; and

FIG. 6 is an equivalent circuit diagram illustrating an erase operation performed with the single-gate vertical channel NAND memory device of FIG. 1C .

【Symbol Description】

100, 300: memory element

101: Substrate

102: Conductive layer

103: Insulation layer

104: Multilayer Laminated Structure

104A, 104B, 104C, 104D: Ridge Laminate

104A1-104A6, 104B1-104B6, 104C1-104C6, 104D1-104D6: Conductive strips

105: Channel

106: Memory material layer

107: Semiconductor channel layer

108, 108P, 108R: storage unit

109A, 109B: U-shaped memory cell serial

110A, 110B: Ground selection line switch

111A, 111B: Serial selection switch

112: Dielectric Material Layer

113: Air Gap

114: Contact plug

115: bit line

116: Contact plug

117: Metal Wire

118: Common source line

119A, 119B, 119C, 319C: word line contact structure

120: word line

121, 122: Contact pads

IG 1A, IG 1B control switch

IG 0A, IG 0B: Auxiliary switch

Vpgm: write voltage

Vpass: Gate pass voltage

Vref: gate read voltage floating: floating

GIDL: Gate Induced Drain Leakage Current

Detailed ways

The present invention provides a memory element, which can solve the problem of insufficient process margin of the known memory element, and at the same time save the manufacturing cost and improve the process yield. In order to make the above-mentioned and other objects, features and advantages of the present invention more obvious and easy to understand, several preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings.

However, it must be noted that these specific implementation cases are not intended to limit the present invention. The present invention may still be practiced with other features, elements, methods and parameters. The preferred embodiments are provided only to illustrate the technical features of the present invention, and not to limit the scope of the claims of the present invention. Those with ordinary knowledge in the technical field will be able to make equivalent modifications and changes based on the description of the following specification without departing from the spirit and scope of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

Please refer to FIGS. 1A to 1C . FIGS. 1A to 1C are perspective views illustrating a process structure for fabricating a single-gate vertical channel NAND memory device 100 according to an embodiment of the present invention. The method for fabricating the single-gate vertical channel NAND memory device 100 includes the following steps: firstly, a multi-layer stack structure 104 (as shown in FIG. 1A ) is formed on the surface of the substrate 101 . In this embodiment, the multi-layer structure 104 includes a plurality of conductive layers 102 and a plurality of insulating layers 103 that are alternately stacked on the substrate 101 along the Z-axis direction shown in FIG. 1A .

In some embodiments of the present invention, the material of the conductive layer 102 may include n-type polysilicon (or n-type epitaxial monocrystalline silicon) doped with phosphorus or arsenic, p-type polysilicon (or p-type epitaxial monocrystalline silicon) doped with boron crystalline silicon), undoped polycrystalline silicon, metal silicides such as titanium silicide (TiSi), cobalt silicide (CoSi) or silicon germanium (SiGe), oxide semiconductors such as indium zinc oxide ( InZnO) or indium gallium zinc oxide (InGaZnO), metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), titanium nitride (TiN) , tantalum nitride (TaN) or tantalum aluminum nitride (TaAlN), or a combination of two or more of the above materials. The insulating layer 103 may be formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicate, or other materials.

Next, a patterning process is performed on the multilayer stack structure 104 to form a plurality of ridge stack layers 104A, 104B, 104C and 104D. In some embodiments of the present invention, an anisotropic etching process, such as a reactive ion etching (Reactive Ion Etching, RIE) process, is used to etch the multilayer structure 104 . The multi-layer stack structure 104 is divided into a plurality of ridge-like stacks 104A, 104B, 104C, and 104D, whereby a channel 105 extending laterally along the X axis and longitudinally along the Z axis is formed in the multilayer stack structure 104, and the Part of the substrate 101 is exposed through the channel 105 (as shown in FIG. 1B ).

Each of the ridge stacks 104A, 104B, 104C, and 104D includes a plurality of strip-shaped conductive strips. For example, in this embodiment, the ridge stack 104A has conductive strips 104A1, 104A2, 104A3, 104A4, 104A5, and 104A6 stacked up in the Z-axis direction; Layers of conductive strips 104B1, 104B2, 104B3, 104B4, 104B5, and 104B6; ridge stack 104C having conductive strips 104C1, 104C2, 104B3, 104C4, 104C5, and 104C6 stacked up in the Z-axis direction; and ridges The stack 104D has conductive strips 104D1, 104D2, 104D3, 104D4, 104D5, and 104D6 stacked up in the Z-axis direction. Among them, conductive strips 104A6, 104B6, 104C6, and 104D6 on the top plane of ridge stacks 104A, 104B, 104C, and 104D have more conductive strips than conductive strips on other planes of the same ridge stacks 104A, 104B, 104C, and 104D 104A1-104A5, 104B1-104B5, 104C1-104C5 and 104D1-104D5 are also thicker.

Afterwards, a memory material layer 106 having a charge trapping structure is formed on the sidewalls of the ridge stacks 104A, 104B, 104C and 104D and at the bottom of the channel 105 . And a patterned semiconductor channel layer 107 is formed on the memory material layer 106 . Further, at the crosspoints where the conductive strips 104A1-A6, 104B1-B6, 104C1-C6 and 104D1-D6 of the ridge stacks 104A, 104B, 104C and 104D overlap with the memory material layer 106 and the channel layer 107, A plurality of memory cells 108 are respectively defined (as shown in FIG. 1C ).

In some embodiments of the present invention, the charge trapping structure of the memory material layer 106 may be a composite multilayer, which is selected from the group consisting of oxide-nitride-oxide (oxide-nitride-oxide, ONO) structure, a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide-nitride-oxide, ONONO) structure, a silicon-silicon oxide-silicon nitride- Silicon-oxide-nitride-oxide-silicon (SONOS) structure, an energy gap engineered silicon-silicon oxide-silicon nitride-silicon oxide-silicon (bandgap engineered silicon-oxide-nitride-oxide-silicon) , BE-SONOS) structure, a tantalum nitride-aluminum oxide-silicon nitride-silicon oxide-silicon (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS) structure and a metal high dielectric constant energy A group of gap-engineered silicon-silicon oxide-silicon nitride-silicon oxide-silicon (metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon, MA BE-SONOS) structures. The semiconductor channel layer 107 may be composed of n-type polysilicon doped with phosphorus or arsenic, or n-type epitaxial single crystal silicon. In addition, the semiconductor channel layer 107 can also be composed of p-type polysilicon doped with boron, or p-type epitaxial single crystal silicon.

In this embodiment, the patterned semiconductor channel layer 107 is made of n-type polysilicon, and the patterned semiconductor channel layer 107 includes at least two parts separated from each other. A portion of the semiconductor channel layer 107 covers the adjacent ridge stacks 104A and 104B and the bottoms of the trenches 105 used to isolate the ridge stacks 104A and 104B. Thereby, a U-shaped channel film is formed between the ridge-shaped stacks 104A and 104B respectively, which is used to connect the plurality of memory cells 108 formed on the ridge-shaped stacks 104A and 104B in series, thereby forming a first U-shaped memory cell series 109A. Another portion of the semiconductor channel layer 107 covers the adjacent ridge stacks 104C and 104C and the bottom of the channel 105 used to isolate the ridge stacks 104C and 104D. And another U-shaped channel film is formed between the ridge-shaped stacks 104C and 104D for connecting the plurality of memory cells 108 formed on the ridge-shaped stacks 104C and 104D in series, thereby forming a second U-shaped memory cell series 109B.

The memory cells located at the top of the ridge stack 104A can be used as the first ground select line switch 110A of the first U-shaped memory cell series 109A; the memory cells located on the top of the ridge stack 104B can be used as the first ground select line switch 110A. The first string selection switch 111A of the U-shaped memory cell string 109A. The memory cells at the top of the ridge stack 104C may act as the second ground select line switch 110B of the second U-shaped memory cell string 109B; the memory cells at the top of the ridge stack 104D may act as a second U-shaped memory cell The second string selection switch 111B of the memory cell string 109B.

It is also worth noting that although FIG. 1C only shows two U-shaped memory cell strings (the first U-shaped memory cell string) formed by four ridge stacks (ridge stacks 104A, 104B, 104C and 104D) row 109A and second U-shaped memory cell series 109B). However, it is only shown for the purpose of clear description, and is not intended to limit the present invention. In some embodiments of the present invention, the single-gate vertical channel NAND memory device 100 may include more ridge stacks and more U-shaped memory cell strings, thereby forming a three-dimensional memory cell array.

After that, a dielectric material layer 112 is filled in the trenches 105 . In some embodiments of the present invention, the material for forming the dielectric material layer 112 may include silicon dioxide, silicon nitride, silicon oxynitride, high-k materials, or any combination of the above materials. In this embodiment, an air gap 113 is preferably formed in the channel 105 to reduce the distance between the memory cells 108 on the sidewalls of the different ridge stacks 104A, 104B, 104C and 104D. interference.

Subsequently, as shown in FIG. 1D , contact plugs 114 are formed on the tops of the ridge stacks 104A, 104B, 104C and 104D to enable the first serial selection line switch 111A and the second serial selection line switch 111B, respectively. It is connected to a bit line 115 ; and a contact plug 116 is formed so that the first ground selection line switch 110A and the second ground selection line switch 110B are respectively connected to a common source line 118 through metal wires 117 . A plurality of word line contact structures (eg, 119B shown in FIG. 1D ) are formed in the peripheral region of the three-dimensional memory cell array, so that they are located in the same level of the ridge stacks 104A, 104B, 104C and 104D for use Conductive strips 104A1-D1, 104A2-D2, 104A3-D3, 104A4-D4, 104A5-D5, and 104A6-D6, which form layer memory cells 108, are connected to different word lines 120, respectively.

The detailed configuration of the word line contact structures, such as the word line contact structures 119A, 119B and 119C, please refer to FIG. 2 , which is a top view of a partial structure of the single-gate vertical channel NAND memory device 100 according to FIG. 2 . The word line contact structures 119A, 119B and 119C are disposed on both sides of the long axis of the ridge stacks 104A, 104B, 104C and 104D, respectively. In this embodiment, the word line contact structure 119A includes a plurality of contact layers of the stepped stack, which are respectively used to contact conductive strips located at different levels in the ridge stack 104B; the word line contact structure 119B includes the stepped stack The multiple contact layers of the layers are respectively used to make contact with the conductive strips located at different levels in the ridge stack 104D. The word line contact structure 119C includes a plurality of contact layers of the stepped stack for making contact with conductive strips at the same level in the ridge stacks 104A and 104C, respectively.

In other words, the conductive strips in the ridge stacks 104A and 104C at the same plane layer share a word line contact structure 119C. Specifically, the conductive strips 104A1 and 104C1 in the first plane layer of the ridge stacks 104A and 104C are in contact with the first contact layer (not shown) of the stepped word line contact structure 119C; they are located in the second plane layer The conductive strips 104A2 and 104C2 are in contact with the second contact layer (not shown) of the stepped word line contact structure 119C; the conductive strips 104A3 and 104C3 on the third plane layer are in contact with the stepped word line contact structure 119C. The third contact layer (not shown) contacts; the conductive strips 104A4 and 104C4 on the fourth plane layer are in contact with the fourth contact (not shown) layer of the stepped word line contact structure 119C; the conductive strips on the fifth plane layer Conductive strips 104A5 and 104C5, in contact with the fifth contact layer (not shown) of the stepped wordline contact structure 119C; and conductive strips 104A6 and 104C6 in the sixth plane layer, in contact with the fifth contact layer (not shown) of the stepped wordline contact structure 119C The sixth contact layer (not shown) contacts. Since the word line contact structure is already known, its detailed structure and fabrication method will not be repeated here.

However, the configuration of the word line contact structure is not limited to this. In some embodiments of the present invention, the conductive strips located under the serial selection line switches in more than two or more different U-shaped memory cell strings, The conductive strips located under the ground select line switches in the more than two different U-shaped memory cell strings share a word line contact structure, respectively.

In some embodiments of the present invention, the single-gate vertical channel NAND memory device 100 further includes a plurality of serial select line contact pads 121 and a shared ground select line contact pad 122 for connecting the serial select line switches ( For example, the first serial selection line switch 111A and the second serial selection line switch 111B) and the ground selection switches (eg, the first ground selection line switch 110A and the second ground selection line switch 110B) are connected to the decoder (not shown). For example, in this embodiment, each TSL contact pad 121 is located at one end of the ridge stacks 104B and 104D having the first TSL switch 111A and the second TSL switch 111B, respectively, adjacent to the word line Contact structures 119A and 119B, and make contact with conductive strips 104B6 and 104D6 used to form first string select line switch 111A and second string select line switch 111B. The shared ground select line contact pad 122 is located at one end of the ridge stacks 104A and 104C with the first ground select line switch 110A and the second ground select line switch 110B, adjacent to the word line contact structure 119C, and is used to form the first ground select line contact structure 119C. A ground select line switch 110A contacts the conductive strips 104A6 and 104C6 of a second ground select line switch 110B.

The shape of the shared word line contact structure 119C may vary with the design of the single gate vertical channel NAND memory element. For example, please refer to FIG. 3 , which is a top view of a partial structure of a single-gate vertical channel NAND memory device 300 according to another embodiment of the present invention. The structure of the single gate vertical channel NAND memory element 300 is substantially the same as the single gate vertical channel NAND memory element 100, the only difference being that the shape of the word line contact structure 319C adjacent to the ground select line contact pad 122 is different. In the present embodiment, the word line contact structure 319C shared by the conductive strips 104A6 and 104C6 located under the first ground select line switch 110A and the second ground select line switch 110B of the ridge stacks 104A and 104C may be Configured in a vertical ladder structure. The lateral width of the single gate vertical channel NAND memory element 300 is further saved.

In order to prevent the different U-shaped memory cell strings 109A and 109B with the shared word line contact structure 119C from generating signal interference during write operations, read operations, and erase operations, in some embodiments of the present invention, the single-gate Vertical channel NAND memory element 100 may include a first control switch IG_1A between first string select line switch 111A and first ground select line switch 110A of U-shaped memory cell string 109A, and a U-shaped memory cell A second control switch IG_1B between the second string select line switch 111B of the string 109B and the second ground select line switch 110B.

For example, please refer to FIG. 4 . FIG. 4 is an equivalent circuit diagram of the single-gate vertical channel NAND memory device 100 of FIG. 1C during a write operation. In this embodiment, the first control switch IG_1A may include a complementary switch circuit 123 connected to the bottom conductive strip 104B1 of the spine-mounted stack 104B for controlling the bottom of the spine-mounted stack 104B. Opening and closing of the storage unit 108 . The second control switch IG_1B is connected to the bottom conductive strip 104D1 of the spine-mounted stack 104D for controlling the opening and closing of the memory cells 108 at the bottom of the spine-mounted stack 104D. Since the structure of the second control switch IG_1B can be the same as that of the first control switch IG_1A, the structure of the second control switch IG_1B is not shown in FIG. 4 . However, in other embodiments, the structure of the second control switch IG_1B may still be different from that of the first control switch 1G_1A.

In addition, in some preferred embodiments, the single-gate vertical channel NAND memory device 100 may further include a first auxiliary switch IG_0A located between the first ground selection line switch 110A and the first control switch IG_1A, and a first auxiliary switch IG_0A located between the first ground selection line switch 110A and the first control switch IG_1A The second auxiliary switch IG_0B between the two ground selection line switch 110B and the second control switch IG_1B. Likewise, the structures of the first auxiliary switch IG_0A and the second auxiliary switch IG_0B may be the same as or different from those of the first control switch IG_1A.

In this embodiment, the first auxiliary switch IG_0A is connected to the bottom conductive strip 104A1 of the spine-mounted stack 104A to control the opening and closing of the memory cells 108 located at the bottom of the spine-mounted stack 104A; the second auxiliary switch IG_0B is The conductive strip 104C1 at the bottom of the spine-mounted stack 104C is connected to control the opening and closing of the memory cells 108 at the bottom of the spine-mounted stack 104C.

When the memory cell 108P in the first U-shaped memory cell string 109A is selected by the first serial selection switch 111A for writing operation, the first serial selection line switch 111A, the first control switch IG_1A and the first auxiliary switch are turned on. switch IG_0A; and turn off the first ground selection line switch 110A. A voltage of 0 volts (0V) is simultaneously applied to the first serial selection line switch 111A and the first ground selection line switch 110A by the bit line 115 and the common source line 118 ; and then a gate is applied to the selected memory cell 108P through the word line 120 write voltage Vpgm; and apply a gate pass voltage Vpass to other memory cells 108 located on the first U-shaped memory cell series 109A. The gate write voltage Vpgm is greater than the gate pass voltage Vpass, so as to induce electron e- to generate Fowler-Nordheim tunneling effect and write data into the memory cell 108P.

The unselected second U-shaped memory cell string 109B keeps the gates of the second string select line switch 111B on the ridge stack 104D and the memory cells below it floating ( floating). Since the conductive strips in the ridge stacks 104A and 104C share a wordline contact structure 119C; Therefore, the gate voltage applied to the second ground select line switch 110B on the ridge stack 104C and the memory cell 108 below it (including the memory cell 108P') will be the same as the gate voltage applied to the first ridge stack 104A. The gate voltages of ground select line switch 110A and the memory cells 108 (including memory cell 108P) below it are identical. Closing the second control switch IG_1B enables the local self-boosting of the second U-shaped memory cell string 109B to form local self-boosting to maintain a sufficient potential to prevent the memory cells 108P located on the ridge stack 104C ' is written under the influence of the write voltage Vpgm.

Please refer to FIG. 5 . FIG. 5 is an equivalent circuit diagram illustrating a read operation using the single-gate vertical channel NAND memory device 100 of FIG. 1C . In this embodiment, when the memory cell 108R located on the first U-shaped memory cell serial 109A is selected by the first serial selection line switch 111A to perform the read operation, the first serial selection line switch 111A, the first serial selection line switch 111A, the A ground selection line switch 110A, a first control switch IG_1A and a first auxiliary switch IG_0A. The bit line 115 and the common source line 118 simultaneously apply 1 volt (1V) and 0 volt (0V) to the first serial selection line switch 111A and the first ground selection line switch 110A; A gate read voltage Vref is applied to the selected memory cell 108R; and a gate pass voltage Vpass is applied to other memory cells 108 on the first U-shaped memory cell series 109A. That is, data can be read from the selected storage unit 108R.

During the read operation of the unselected second U-shaped memory cell string 109B, the gates of the second string select line switch 111B on the ridge stack 104D and the memory cells 108 below it remain floating. Since the conductive strips in the ridge stacks 104A and 104C share a wordline contact structure 119C; Therefore, the gate voltage applied to the second ground select line switch 110B on the ridge stack 104C and the memory cell 108 below it (including the memory cell 108R') will be the same as the gate voltage applied to the first ridge stack 104A. The gate voltages of ground select line switch 110A and the memory cell 108 (including memory cell 108R) below it are identical. Turning off the second control switch IG_1B and keeping the gates of the second string select line switch 111B in the second U-shaped memory cell string 109B and the memory cells 108 below it floating can prevent unselected second Memory cells 108R' in U-shaped memory cell string 109B are read by gate read voltage Vref.

Please refer to FIG. 6 . FIG. 6 is an equivalent circuit diagram of the single-gate vertical channel NAND memory device 100 of FIG. 1C during an erase operation. In this embodiment, when the first U-shaped memory cell string 109A is selected for the erasing operation, 7 is applied to the gates of the first string selection line switch 111A, the first control switch IG_1A and the first auxiliary switch IG_0A voltage (7V) to turn it on; 0 volts (0V) is applied to the first ground selection line switch 110A through the common source line 118 to keep the gate of the first ground selection line switch 110A floating; A voltage of 0 volts (0V) is applied to the gates of all the memory cells 108 on the first U-shaped memory cell string 109A; then an erase voltage of 20 volts (20V) is applied to the first string selection line switch 111A through the bit line 115 . Thereby, the memory cells 108 located on the first U-shaped memory cell series 109A generate a gate-induced drain leakage (GIDL) GIDL.

When the unselected second U-shaped memory cell string 109B is performing an erase operation, the second string selection line switch 111B on the ridge stack 104D and the memory cells 108 below it, and the second control switches IG_1B and IG_1B and The gates of the second ground selection switch 110B are kept floating. Since the conductive strips in the ridge stacks 104A and 104C share a wordline contact structure 119C; Therefore, the gate voltage of the second ground select line switch 110B applied on the ridge stack 104C and the memory cell 108 below it will be the same as that of the first ground select line switch 110A and its underlying memory cell 108 applied on the ridge stack 104A. The gate voltages of the underlying memory cells 108 are identical. Keeping the gates of the second serial select line switch 111B on the ridge stack 104D and the memory cell 108 below it and the second control switch IG_1B floating can delay the erase time and prevent the second U-shaped memory The memory cells 108 in the cell string 109B are erased within the nanosecond erase time.

In accordance with the above-described embodiments, the present specification provides a three-dimensional memory element having a plurality of ridge stacks, wherein each ridge stack includes, respectively, a serial select line switch or a ground select line switch on top, and Multiple memory cells located below the serial select line switch or the ground select line switch. The first string select line switch and the first ground select line switch are connected in series on the two ridge stacks, and the memory cells are located under the first string select line switch and the first ground select line switch. a U-shaped memory cell string; simultaneously by connecting in series a second string select line switch and a second ground select line switch on two other different ridge stacks, and a second string select line switch and a second The memory cells below the select line switch are grounded to form a second U-shaped string of memory cells.

Wherein, the memory cells located under the first serial selection line switch of the first U-shaped memory cell series are connected to the first word line contact structure; they are located under the second serial selection line switch of the second U-shaped memory cell series. The memory cells are connected to the second word line contact structure; and the memory cells located under the first ground select line switches of the first U-shaped memory cell series and the second ground select line switches of the second U-shaped memory cell series The lower memory cells are then connected to the same third word line contact structure. In other words, in the three-dimensional memory element, the number of word line contact structures used to connect memory cells located under the ground select switch is smaller than the number of word line contact structures used to connect memory cells located under the serial select switch. Compared with the three-dimensional memory element in the prior art, the arrangement of the word line contact structure can be reduced without changing the memory capacity.

By reducing the arrangement of the word line contact structure, the area size of the memory element can be reduced; moreover, the memory capacity of the memory element can be expanded without affecting the process margin, the process cost can be greatly reduced, and the oxide layer breakdown can be prevented. Increase the process yield of vertical channel memory devices.

Claims (10)

1. A three-dimensional memory element, comprising: A multi-layer stack structure including a plurality of conductive strips and a plurality of channels isolated from each other, for defining at least a first ridge stack, a second ridge stack, a third ridge stack, and a fourth ridged stack; a first serial selection line switch on the first ridge stack; a first ground selection line switch located on the second ridge stack; a first U-shaped memory cell serial, connected in series with the first serial selection line switch and the first grounding selection line switch; a second serial selection line switch on the third ridged stack; a second ground selection line switch located on the fourth ridge stack; a second U-shaped memory cell serial, connected in series with the second serial selection line switch and the second grounding selection line switch; a first word line contact structure in contact with the conductive strips on the first ridge stack; a second wordline contact structure in contact with the conductive strips on the third ridge stack; and A third wordline contact structure contacts the conductive strips on the second ridge stack and the fourth ridge stack. 2. The three-dimensional memory element of claim 1, further comprising a first serial select line contact pad in contact with a top conductive strip on the first ridge stack; a second serial select line contact pad in contact with a top conductive strip on the third ridge stack; and A ground select line contact pad is in contact with the two top conductive strips on the second ridge stack and the fourth ridge stack. 3. The three-dimensional memory element according to claim 1, further comprising: a layer of memory material on the sidewalls of the channels; a patterned channel film covering the memory material layer and the bottoms of the channels; and A plurality of memory cells are formed at a plurality of positions where the memory material layer, the patterned channel film and the conductive strips overlap. 4. The three-dimensional memory element of claim 3, wherein: The first U-shaped memory cell string is connected in series with the first string select line switch, the memory cells on the first ridge stack and the second ridge stack through a portion of the patterned channel film, and formed by the first ground select line switch; and The second U-shaped memory cell string is connected in series with the second string select line switch, the memory cells on the third ridge stack and the fourth ridge stack through another part of the patterned channel film and the second ground selection line switch is formed. 5. The three-dimensional memory element according to claim 3, further comprising: a first control switch located between the first serial selection line switch and the first ground selection line switch; and A second control switch is located between the second serial selection line switch and the second ground selection line switch. 6. The three-dimensional memory element of claim 5, wherein: the first control switch is connected to a bottom conductive strip of the first ridge stack; and The second control switch is connected to a bottom conductive strip of the third ridge stack. 7. The three-dimensional memory element according to claim 6, further comprising: a first auxiliary switch located between the first control switch and the first ground selection line switch; and A second auxiliary switch is located between the second control switch and the second ground selection line switch. 8. The three-dimensional memory element of claim 7, wherein: the first auxiliary switch is in contact with a bottom conductive strip of the second ridge stack; and The second auxiliary switch is in contact with a bottom conductive strip of the fourth ridge stack. 9. The three-dimensional memory element of claim 5, wherein when selecting the first U-shaped memory cells to perform a write operation in series, the write operation comprises: turning on the first serial selection line switch and the first control switch; turning off the first ground selection line switch, the second ground selection line switch, and the second control switch; and applying a write voltage to one of the memory cells on the first U-shaped memory cell string; and A pass voltage is applied to the other memory cells on the first U-shaped memory cell string, wherein the write voltage is greater than the pass voltage. 10. The three-dimensional memory device of claim 9, wherein a gate of the second serial select line switch is kept floating during the write operation.