CN106888004A - A kind of ring oscillator - Google Patents
A kind of ring oscillator Download PDFInfo
- Publication number
- CN106888004A CN106888004A CN201710018343.4A CN201710018343A CN106888004A CN 106888004 A CN106888004 A CN 106888004A CN 201710018343 A CN201710018343 A CN 201710018343A CN 106888004 A CN106888004 A CN 106888004A
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- China
- Prior art keywords
- delay cell
- pipe
- ring oscillator
- source
- output
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
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- Pulse Circuits (AREA)
Abstract
The present invention is a kind of ring oscillator, and the oscillator includes Current Voltage converting unit, oscillating unit and frequency dividing circuit, and Current Voltage converting unit is connected with oscillating unit, and oscillating unit is connected with frequency dividing circuit.The present invention can greatly weaken influence of the supply voltage to inverter delay elements, so as to improve oscillator precision.
Description
Technical field
The present invention is a kind of ring oscillator, especially a kind of ring oscillator insensitive to supply voltage.
Background technology
In current fairly large IC system, numerical portion circuit is required for one to compare accurately clock letter
Number, as synchronizing signal and timing signal.Traditional clock signal is obtained using the outer quartz oscillator of piece, and quartz crystal shakes
Swinging utensil has stability very high, it can be difficult to be integrated into piece, and it is relatively costly.Therefore increasing circuit is in
The integrated clock oscillator in portion, common are ring oscillator, relaxor and LC oscillators.Its ring oscillator because
Simple structure, power consumption is smaller by many widely used, but because stability is not high, is served only for less demanding to clock signal
In system.
Referring to Fig. 1, in order to improve the stability of ring oscillator, a kind of ring oscillator structure by current control is sent out
It is bright out.By controlling phase inverter pull-up current and pull-down current, make the rising edge trailing edge time delay of phase inverter controllable, to obtain
Relatively stable frequency of oscillation.But the drawbacks of structure still has one substantially, it has obvious frequency with mains voltage variations
Rate is shaken.
The content of the invention
In order to solve above-mentioned technical problem present in background technology, the present invention provides a kind of insensitive to supply voltage
Ring oscillator, can greatly weaken influence of the supply voltage to inverter delay elements, so as to improve oscillator precision.
Technical solution of the invention is：The present invention is a kind of ring oscillator, and it is characterized in that：The oscillator
Including Current Voltage converting unit, oscillating unit and frequency dividing circuit, Current Voltage converting unit is connected with oscillating unit, and vibration is single
Unit is connected with frequency dividing circuit.
Above-mentioned Current Voltage converting unit is in series by the n type field effect transistor that two diodes are connected.
Above-mentioned oscillating unit includes delay cell, and delay cell includes upper trombone slide P2 and lower trombone slide N16, upper trombone slide P2 sources
Power supply is connect, grid connects the input of delay cell, and drain terminal connects output；Lower trombone slide N16 sources connect mirror current source output, and grid connects and prolongs
Slow unit input, drain terminal connects output；Delay cell includes the mirror current source being made up of mirror image pipe N6 and cascade pipe N5, mirror
The source of the drain terminal of image tube N6 bank tube N5 common with common source is connected, and the source ground connection of mirror image pipe N6, cascade pipe N5 drain terminals connect down
The source of trombone slide N16, the grid of mirror image pipe N6 meets bias voltage Vb, and the grid of cascade pipe N5 meets cascade voltage Vc；
Gate voltage Vc is produced bias voltage Vb by Current Voltage converting unit altogether with common source.
The feedback pipe also constituted comprising NMOS tube in above-mentioned delay cell, feeding back the grid of pipe, to connect delay cell defeated
Go out, drain terminal connects delay cell input, source ground connection.
The load capacitance also constituted comprising a NMOS tube in above-mentioned delay cell, the grid connection delay unit of electric capacity is defeated
Go out, source drain terminal ground connection.
Above-mentioned frequency dividing circuit is frequency-halving circuit, is made up of with phase inverter d type flip flop, and phase inverter is defeated by the Q ends of d type flip flop
Go out the anti-phase input for being followed by d type flip flop, the CK of d type flip flop terminates the output of oscillating unit.
Above-mentioned oscillating unit includes N grades of identical delay cell, and output end and the next stage of delay cells at different levels postpone list
The input connection of unit, the output end of most final stage is connected with the input of the first order.
Above-mentioned N is greater than the odd number equal to 3.
The present invention has advantages below：
1st, Current Voltage converting unit of the present invention, using cascode structure, can be greatly improved current mirror
Precision.
2nd, delay cell of the invention, is postponed using current control trailing edge, and removes supply voltage (VDD) to trailing edge
The influence of delay, is substituted using the threshold voltage (VTHP) of p type field effect transistor (PMOS)；Accelerate to rise using feedback simultaneously
Along postponing, further weaken influences of the VDD to oscillator frequency.
Brief description of the drawings
Fig. 1 is the structural representation of the ring oscillator of existing current control；
Fig. 2 is the structural representation of delay cell in the present invention
Fig. 3 is the structural representation of the specific embodiment of the invention.
Specific embodiment
Referring to Fig. 2,3, instantiation example of the invention is by Current Voltage converting unit, oscillating unit and frequency unit group
Into.
Current Voltage converting unit includes mirror image pipe and the common bank tube of common source, the N-type effect for being connected by two diodes respectively
Answer transistor (NMOS) N1 and N2 in series, control electric current (IREF) is converted into control voltage Vb and Vc.Vb and Vc is controlled
Pull-down current mirror image pipe (N3, N4, N5, N6, N7, N8) in delay cell, the pull-down current of stabilization is provided for delay cell.
Oscillating unit includes three delay cells, is described by taking delay cell 2 as an example.
Comprising upper trombone slide P2 and lower trombone slide N16, upper trombone slide P2 sources termination power, grid connects the input of delay cell, drain terminal
Connect output；Lower trombone slide N16 sources connect mirror current source output, and grid connects delay cell input, and drain terminal connects output；Delay cell bag
Containing the mirror current source being made up of mirror image pipe N6 and cascade pipe N5, the source of the drain terminal bank tube N5 common with common source of mirror image pipe N6
It is connected, the source ground connection of mirror image pipe N6, cascade pipe N5 drain terminals connect the source of lower trombone slide N16, and the grid of mirror image pipe N6 connects partially
Voltage Vb is put, the grid of cascade pipe N5 meets cascade voltage Vc；Bias voltage Vb gate voltage Vcs common with common source is by electric current
Voltage conversion unit is produced.
Mirror image pipe N6 and cascade pipe N5 use cascode structure, cascade pipe N5 sizes to be changed with Current Voltage
N1 in unit is identical and grid is connected, and mirror image pipe N6 sizes are identical with N2 and grid is connected.Cascode structure can be improved
The precision of current mirror, makes pull-down current (ID2) be reduced with the difference of control electric current (IREF).
PMOS P2 and NMOS tube N16 is respectively the upper trombone slide and lower trombone slide of delay cell, and pull-up PMOS is directly connected to
Supply voltage (VDD), pull-down NMOS pipe connection current source.
The design can be controlled at (VDD-VTHP) turnover voltage of delay cell；Pull-down current by current source control,
Therefore, delay cell trailing edge postpone be
Wherein Cout is delay cell output node electric capacity, and ID2 is delay cell pull-down current, and IREF is the control of oscillator
Electric current processed.The relation of the fall time and VDD that can be seen that delay cell by the formula is eliminated.
Delay cell turnover voltage is set as that (VDD-VTHP) also has two extra advantages.First, in output voltage
In the range of from VDD to (VDD-VTHP), pull-down current mirror image pipe will not be pressed into linear zone, improve the stability of electric current；
Second, in the range of output voltage is from VDD to (VDD-VTHP), the capacitance of output load capacitance N13 keeps stabilization, it is ensured that
The stabilization of electric capacity in Tdf.
The rise time of delay cell is determined by upper trombone slide P2, because P2 pulls up drop-down energy of the ability much larger than delay cell
Power, so rising delay
Tdr<<Tdf；
The presence of feedback pipe N10, can further reduce the rise time of delay cell.Detailed process is as follows：
It is that PH1 begins to decline when PH3 rises above (VDD-VTHP)；When PH1 drops to (VDD-VTHP), P2 pipes
Open, now PH2 maintains power supply ground, but because P2 sizes are much larger than N11, PH2 begins to ramp up, when PH2 rises to NMOS thresholds
During threshold voltage (VTHN), N10 pipes are opened, and rapidly drag down PH1.
The electric capacity N13 also constituted comprising a NMOS tube in delay cell, its grid connection delay unit output, source
Drain terminal is grounded.The presence of electric capacity can further widen the gap that rise edge delay postpones with trailing edge, reduce rise edge delay
Influence in this design, the frequency of stabilized oscillator.
In sum, the output frequency of oscillator is：
Wherein, N is the series of delay cell, and N is greater than the odd number equal to 3, N=3 in this example.
Claims (8)
1. a kind of ring oscillator, it is characterised in that：The oscillator includes Current Voltage converting unit, oscillating unit and frequency dividing electricity
Road, the Current Voltage converting unit is connected with oscillating unit, and the oscillating unit is connected with frequency dividing circuit.
2. ring oscillator according to claim 1, it is characterised in that：The Current Voltage converting unit is by two two poles
The n type field effect transistor of pipe connection is in series.
3. ring oscillator according to claim 2, it is characterised in that：The oscillating unit includes delay cell, described
Delay cell includes upper trombone slide P2 and lower trombone slide N16, and the upper trombone slide P2 sources termination power, grid connects the input of delay cell,
Drain terminal connects output；The lower trombone slide N16 sources connect mirror current source output, and grid connects delay cell input, and drain terminal connects output；Institute
State delay cell and include the mirror current source being made up of mirror image pipe N6 and cascade pipe N5, the drain terminal of the mirror image pipe N6 is together
The source of the common bank tube N5 in source is connected, and the source ground connection of the mirror image pipe N6, the cascade pipe N5 drain terminals connect lower trombone slide N16's
Source, the grid of the mirror image pipe N6 meets bias voltage Vb, and the grid of the cascade pipe N5 meets cascade voltage Vc；Institute
Gate voltage Vc is produced by Current Voltage converting unit altogether with common source to state bias voltage Vb.
4. ring oscillator according to claim 3, it is characterised in that：A NMOS tube is also included in the delay cell
The feedback pipe of composition, the grid of the feedback pipe connects delay cell output, and drain terminal connects delay cell input, source ground connection.
5. ring oscillator according to claim 4, it is characterised in that：A NMOS tube is also included in the delay cell
The load capacitance of composition, the grid connection delay unit output of the electric capacity, source drain terminal ground connection.
6. ring oscillator according to claim 5, it is characterised in that：The frequency dividing circuit is frequency-halving circuit, is touched by D
Hair device is constituted with phase inverter, and the Q ends of d type flip flop are exported the anti-phase input for being followed by d type flip flop, d type flip flop by the phase inverter
CK terminate oscillating unit output.
7. the ring oscillator according to claim 1 or 2 or 3 or 4 or 5 or 6, it is characterised in that：The oscillating unit bag
N grades of identical delay cell is included, the output end of delay cells at different levels is connected with the input of next stage delay cell, most final stage
Output end is connected with the input of the first order.
8. ring oscillator according to claim 7, it is characterised in that：The N is greater than the odd number equal to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710018343.4A CN106888004A (en) | 2017-01-10 | 2017-01-10 | A kind of ring oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710018343.4A CN106888004A (en) | 2017-01-10 | 2017-01-10 | A kind of ring oscillator |
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| CN106888004A true CN106888004A (en) | 2017-06-23 |
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| CN201710018343.4A Pending CN106888004A (en) | 2017-01-10 | 2017-01-10 | A kind of ring oscillator |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109167571A (en) * | 2018-08-13 | 2019-01-08 | 中科芯集成电路股份有限公司 | A kind of low-power consumption ring oscillator and its implementation |
| CN109491438A (en) * | 2018-12-05 | 2019-03-19 | 北京矽成半导体有限公司 | The fixed delay circuit and its control method not influenced by temperature voltage |
| CN109547018A (en) * | 2018-11-28 | 2019-03-29 | 中国人民解放军国防科技大学 | A Multi-Bias Voltage Controlled Oscillator with Radiation Resistance |
| CN112858767A (en) * | 2020-12-22 | 2021-05-28 | 国网宁夏电力有限公司检修公司 | High-precision synchronous acquisition device for monitoring extra-high voltage converter station sleeve |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109167571A (en) * | 2018-08-13 | 2019-01-08 | 中科芯集成电路股份有限公司 | A kind of low-power consumption ring oscillator and its implementation |
| CN109547018A (en) * | 2018-11-28 | 2019-03-29 | 中国人民解放军国防科技大学 | A Multi-Bias Voltage Controlled Oscillator with Radiation Resistance |
| CN109547018B (en) * | 2018-11-28 | 2022-08-09 | 中国人民解放军国防科技大学 | Multi-bias voltage-controlled oscillator with anti-irradiation function |
| CN109491438A (en) * | 2018-12-05 | 2019-03-19 | 北京矽成半导体有限公司 | The fixed delay circuit and its control method not influenced by temperature voltage |
| CN112858767A (en) * | 2020-12-22 | 2021-05-28 | 国网宁夏电力有限公司检修公司 | High-precision synchronous acquisition device for monitoring extra-high voltage converter station sleeve |
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Application publication date: 20170623 |
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