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CN106935543A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN106935543A
CN106935543A CN201610720168.9A CN201610720168A CN106935543A CN 106935543 A CN106935543 A CN 106935543A CN 201610720168 A CN201610720168 A CN 201610720168A CN 106935543 A CN106935543 A CN 106935543A
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CN
China
Prior art keywords
semiconductor workpiece
semiconductor
workpiece
hole
conductive
Prior art date
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Pending
Application number
CN201610720168.9A
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English (en)
Inventor
余振华
陈明发
叶松峯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN106935543A publication Critical patent/CN106935543A/zh
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Abstract

本发明提供了半导体结构及其形成方法。该方法包括：提供第一半导体工件；将第二半导体工件接合至第一半导体工件的第一表面；形成穿过第二半导体工件至第一半导体工件的第一导电通孔；将第三半导体工件接合至第一半导体工件的第二表面，第二表面与第一表面相对；并且形成穿过第一半导体工件和第三半导体工件至第二半导体工件的第二导电通孔，从而使得第一导电通孔和第二导电通孔是电连接的。

Description

半导体结构及其形成方法
技术领域
本发明的实施例涉及半导体结构及其形成方法。
背景技术
自集成电路的发明以来，由于各个电子组件和半导体封装件的集成密度的持续改进，半导体工业已经经历了连续的快速增长。对于大部分而言，这些集成密度的改进来自于最小部件尺寸的反复减小，允许更多的组件集成至半导体芯片或封装件。
一种用于允许更多组件集成至半导体结构的方法是三维集成电路(3DIC)堆叠技术的采用，其中，硅晶圆和/或管芯彼此堆叠并且使用通孔垂直互连，从而使得它们充当为单个器件以获得比传统二维工艺改进的性能。然而，用于3DIC堆叠的传统技术允许在基衬底/晶圆的一侧上堆叠晶圆和/或管芯。相应地，需要在基衬底/晶圆的两侧上堆叠晶圆和/或管芯的半导体结构。
发明内容
本发明的实施例提供了一种用于形成半导体结构的方法，包括：提供第一半导体工件；将第二半导体工件接合至所述第一半导体工件的第一表面；形成穿过所述第二半导体工件至所述第一半导体工件的第一导电通孔；将第三半导体工件接合至所述第一半导体工件的第二表面，所述第二表面与所述第一表面相对；以及形成穿过所述第一半导体工件和所述第三半导体工件至所述第二半导体工件的第二导电通孔，从而使得所述第一导电通孔和所述第二导电通孔是电连接的。
本发明的另一实施例提供了一种用于形成半导体结构的方法，包括：提供包括第一衬底和第一有源层的第一半导体工件；将第二半导体工件接合至所述第一有源层，其中，所述第二半导体工件包括第二衬底和第二有源层；将第三半导体工件接合至所述第一衬底，其中，所述第三半导体工件包括第三衬底和第三有源层；以及形成连接所述第一有源层、所述第二有源层和所述第三有源层的导电通孔。
本发明的又一实施例提供了一种半导体结构，包括：第一半导体工件；第二半导体工件，接合至所述第一半导体工件的第一表面；第三半导体工件，接合至所述第一半导体工件的第二表面；以及多个导电通孔，电连接所述第一半导体工件、所述第二半导体工件和所述第三半导体工件，其中，第一导电通孔在朝向所述第二半导体工件的方向上是锥形的。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A至图1R示意性地示出了根据本发明的一个实施例的制造半导体结构的方法。
图2A至图2P示意性地示出了根据本发明的一个实施例的制造半导体结构的方法。
图3A至图3O示意性地示出了根据本发明的一个实施例的制造半导体结构的方法。
图4是根据本发明的一个实施例的示出半导体结构的示意图。
图5是根据本发明的一个实施例的示出半导体结构的示意图。
图6是根据本发明的一个实施例的示出半导体结构的示意图。
图7A和图7B是根据本发明的一个实施例的示出半导体InFO结构的示意图。
图8是根据本发明的一个实施例的示出半导体CoWoS结构的示意图。
具体实施方式
以下将详细的讨论本发明的实施例的制造和使用。然而，应该理解，本发明提供的许多适用的创造性概念，该概念可以在各种特定的上下文中体现。应该明白，以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。
以下使用特定的语言讨论图中示出的实施例或实例。然而，应该明白，该实施例或实例不旨在限制本发明。公开的实施例中的任何改变和修改以及在这个文件中公开的原则的任何进一步应用可以考虑为将通常发生在相关领域中的一种普通技术。
此外，应该明白，可以仅简单的描述多个工艺步骤(操作)和/或器件的特性。同样，当仍实现要求时，可以添加额外的工艺步骤和/或部件，可以去除或改变某些随后的工艺步骤和/或部件。因此，应该明白，随后的描述仅代表实例，并且不旨在显示需要的一个或多个步骤或部件。
此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
参照附图，图1A至图1R示意性地示出了根据本发明的第一实施例的用于制造半导体结构的操作。
在图1A中，提供了第一半导体工件101。第一半导体工件101可以包括第一衬底101a和第一有源层101b。第一衬底101a可以包括多层衬底、梯度衬底、混合取向衬底、任何他们的组合等。用于第一衬底101a的材料包括块状硅、半导体晶圆、绝缘体上硅(SOI)衬底或硅锗衬底。也可以使用包括III族、IV族和V族元素的其它半导体材料。第一有源层101b可以包括诸如靠近有源侧的浅沟槽隔离(STI)部件或硅的局部氧化(LOCOS)部件的多个隔离部件(未示出)。隔离部件可以限定或隔离各个微电子元件。微电子元件可以包括晶体管(例如，MOSFET、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高压晶体管、高频晶体管、p-沟道和/或n-沟道场效应晶体管(PFET/NFET))、二极管、电阻器、电容器、电感器或其它合适的元件。用于这些微电子元件101c的制造工艺包括沉积、蚀刻、注入、光刻、退火或其它合适的工艺。互连这些微电子元件以形成逻辑器件、存储器器件(例如，静态随机存取存储器或SRAM)、射频(RF)器件、输入/输出(I/O)器件，芯片上系统(SoC)器件、嵌入式闪存器件、微电子机械(MEMS)器件、模拟器件、CMOS器件、这些的组合等。在一个实施例中，第一半导体工件101可以是具有已知功能电路单元的已知良好晶圆("KGW")或已知良好管芯("KGD")，其中，微电子元件101c以网格形式定位。
第一有源层101b由钝化材料形成(例如，氧化物或电介质)并且可以包括钝化材料中的金属互连件。在一些实施例中，微电子元件包括用于接收另一金属互连件(未示出)的电信号并且向另一金属互连件(未示出)提供电信号的的金属焊盘。
在图1B中，包括第二衬底102a和第二有源层102b第二半导体工件102接合至第一半导体工件101。第二有源层102b包括多个微电子元件102c。可以通过使用熔融接合、混合接合、共晶接合、附着接合、热压接合、等离子体活化接合或反应接合来完成接合。
图1B中采用熔融接合。该接合工艺描述如下。首先，为了避免非接合区的出现(即，界面气泡)，处理第一半导体工件101和第二半导体工件102的将要接合的表面以变得足够的干净和平滑。在一个实施例中，处理第一半导体工件101和第二半导体工件102(例如，通过抛光)的将要接合的表面以变得平滑，其表面粗糙度小于10埃或甚至小于5埃。之后，第一半导体工件101和第二半导体工件102在室温和预定量的压力下对准并且物理接触地放置以开始接合工艺。在升高的温度下的退火用于形成第一半导体工件101和第二半导体工件102的将要接合的表面之间的化学接合。在一个实施例中，退火温度小于约400摄氏度。
图1B也示出了布置为“面对面”接合布置(即，它们的有源层接合在一起的半导体工件)的第一半导体工件101的第一有源层101b和第二半导体工件102的第二有源层102b。本实施例仅应于说明的目的并且因此不用于限制。“面对面”、“背对背”、“面对背”或“背对面”组合的任何布置均可以用于本发明的接合界面中。
在图1C中，减薄第二半导体工件102以减小总厚度。具体地，通过减薄第二半导体工件102的第二衬底102a实施减薄。可以通过机械研磨、化学机械抛光(CMP)、湿蚀刻、大气压下游等离子体(ADP)干化学蚀刻(DCE)、上述工艺的组合或任何另一适当的减薄方法来完成减薄。在一个实施例中，第二半导体工件102减薄至小于约50微米厚。在一个实施例中，第二半导体工件102减薄至小于约10微米厚。
在一个实施例中，第二半导体工件102包括多个半导体管芯(图1C的实施例所示，第二半导体工件102包括两个半导体管芯)。在图1D中，用介电材料105填充位于第二半导体工件102的邻近的半导体管芯之间的间隙。在一个实施例中，介电材料105是诸如环氧树脂或聚酰亚胺化合物的模塑料。
在图1E中，形成穿过第二半导体工件102的开口106和107，其中，开口107形成为穿过介电材料105。实际上，开口106和107穿透第二半导体工件102并且延伸至到达第一半导体工件101。在第二半导体工件102上形成用于限定开口106和107的硬掩模层和图案化的光刻胶层(未示出)。硬掩模层可以是氮化硅层、氮氧化硅层等。通过曝光、烘烤、显影和/或其它光刻工艺图案化光刻胶层以提供暴露硬掩模层的开口。之后，使用图案化的光刻胶层作为掩模元件，通过湿蚀刻或干蚀刻工艺蚀刻暴露的硬掩模层以提供开口。使用硬掩模层和图案化的光刻胶层作为掩模元件，实施回蚀刻工艺以蚀刻暴露的第二半导体工件102，形成开口106和107。在开口106和107的形成之后，去除硬掩模层和光刻胶层。例如，可以使用包括等离子体蚀刻、化学湿蚀刻、激光钻孔和/或本领域中已知的其它工艺的任何合适的蚀刻方法蚀刻开口106和107。该蚀刻工艺可以产生具有垂直侧壁轮廓或锥形侧壁轮廓的开口。在一个实施例中，开口106和107具有介于约5和约10之间的高高宽比。在一些实施例中，开口106和107的高宽比大于10。
在图1F中，导电材料沉积为填充开口106和107以形成导电通孔108和109，其中，导电通孔109邻近于介电材料105’。导电通孔108和109用于电连接第一半导体工件101的第一有源层101b和第二半导体工件102的第二有源层102b(例如，通过电连接且电子元件101c和微电子元件102c)。导电材料可以由通过LPCVD、PECVD、MOCVD、ALD或其它先进的沉积技术(例如，铜填充工艺包括金属晶种层沉积和铜电化学镀)形成的钨、钨基合金、铜或铜基合金、铝、金、银、钼(Mo)、氮化钛(TiN)等形成。
在一些实施例中，在导电通孔108和109的形成之前，选择性地沉积阻挡层(氧化物衬垫)。该阻挡层起扩散阻挡的作用以防止金属扩散并且作为金属和电介质之间的粘合层。难熔金属、难熔金属氮化物、难熔金属硅氮化物以及它们的组合通常用于阻挡层。在一个实施例中，导电通孔108是硅通孔("TSV")并且导电通孔109是介电通孔("TDV")。
在图1G中，形成金属焊盘110以覆盖并且电连接导电通孔108和109。利用金属焊盘110将外部电接触件电连接至微电子元件101c/102c的I/O的一个。金属焊盘110可以包括铝、铜或它们的合金。
在图1H中，在第二半导体工件102和金属焊盘110的顶面上形成用于结构支撑和物理隔离的钝化层111。钝化层111可以保护第二半导体工件102免受机械损坏(粒子/划痕/污染)和其它化学腐蚀的影响。钝化层111可以用氮化硅(SiN)、二氧化硅(SiO2)、氮氧化硅(SiON)、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或其它绝缘材料制成。
在图1I中，使用胶材料(未示出)将衬底104接合至钝化层111。衬底104用以对第一半导体工件101和第二半导体工件102提供机械支撑以促进进一步处理。
在图1J中，减薄第一半导体工件101以减小总厚度。具体地，通过减薄第一半导体工件101的第一衬底101a实施减薄。在一个实施例中，第一半导体工件101减薄至小于约50微米厚。在一个实施例中，第一半导体工件101减薄至小于约10微米厚。
在图1K中，在第一半导体工件101的减薄的第一衬底101a上形成接合氧化物层112以促进进一步接合工艺。在一个实施例中，通过加热第一衬底101a的表面形成接合氧化物层112。
在图1L中，使用熔融接合技术将包括第三衬底103a和第三有源层103b的第三半导体工件103接合至接合氧化物层112。第三有源层103b包括多个微电子元件103c。在一个实施例中，第三半导体工件103包括多个半导体管芯(如图1L所示的两个半导体管芯)。在图1M中，用介电材料105填充位于第三半导体工件103的邻近的半导体管芯之间的间隙。
在图1N中，形成穿过第三半导体工件103和第一半导体工件101的开口113和114(其中，开口114形成为穿过介电材料105)。例如，可以使用包括等离子体蚀刻、化学湿蚀刻、激光钻孔和/或本领域中已知的其它工艺的任何合适的蚀刻方法形成开口113和114。该蚀刻工艺可以产生具有垂直侧壁轮廓或锥形侧壁轮廓的开口。在一个实施例中，开口113和114具有介于约5和约10之间的高高宽比。在一些实施例中，开口113和114的高宽比大于10。
在图1O中，沉积导电材料以填充开口113和114以形成导电通孔115和116，其中，导电通孔116邻近介电材料105’。导电通孔115和116用以电连接第一半导体工件101的第一有源层101b和第三半导体工件103的第三有源层103b(通过电连接微电子元件101c和微电子元件103c)。导电材料可以由通过LPCVD、PECVD、MOCVD、ALD或其它先进的沉积技术形成的钨、钨基合金、铜或铜基合金、铝、金、银、钼(Mo)、氮化钛(TiN)等形成。在一些实施例中，在导电通孔115和116的形成之前，选择性地沉积阻挡层(氧化物衬垫)。在一个实施例中，导电通孔115是硅通孔("TSV")并且导电通孔116是介电通孔("TDV")。
在图1P中，形成金属焊盘117以覆盖并且电连接导电通孔115和116。利用金属焊盘117将外部电接触件电连接至微电子元件101c/102c/103c的I/O的一个。金属焊盘117可以包括铝、铜或它们的合金。
在图1Q中，在第三半导体工件103和金属焊盘117的顶面上形成用于结构支撑和物理隔离的钝化层118。钝化层118可以保护第三半导体工件103免受机械损坏(粒子/划痕/污染)和其它化学腐蚀的影响。
在图1R中，图案化钝化层118以包括暴露金属焊盘117的开口。在金属焊盘117的暴露的部分上形成导电凸块119。在图1R中，衬底114从钝化层111剥离。图1R示出了根据本发明的第一方法的实施例制造的半导体结构，其中，导电通孔108和109以及导电通孔115和116形成为朝向相反方向的锥形。在一个实施例中，第一半导体工件101是已知良好晶圆("KGW")并且对图1R的半导体结构进行进一步切割以产生多个子结构(未示出)。在一个实施例中，使用任何合适的蚀刻方法使金属焊盘110从钝化层111下方进一步暴露，从而使得金属焊盘110可以连接至外部电接触件(未示出)。
参照附图，图2A至图2P示意性地示出了根据本发明的第二实施例的用于制造半导体结构的操作。
在图2A中，提供第一半导体衬底工件201。第一半导体工件210可以包括第一衬底201a和第一有源层201b。第一有源层201b可以由与第一衬底101a相同的材料形成。可选地，第一有源层201b可以由钝化材料(例如，氧化物或电介质)形成。第一有源层201b可以包括多个微电子元件(未示出)。
如图2A所示，第一半导体工件201包括嵌入在其内的导电通孔205。此外，第一有源层201b包括金属焊盘201c。在一个实施例中，第一半导体工件201是已知良好晶圆("KGW")。
在图2B中，包括第二衬底202a和第二有源层202b的第二半导体工件202接合至第一半导体工件201。第二有源层202b包括多个微电子元件(未示出)和金属焊盘202c。如图2B所示，通过混合接合将第二半导体工件202接合至第一半导体工件201。在混合接合中，以类似于熔融接合的方式接合介电材料，并且使用退火工艺接合金属焊盘。在一个实施例中，氧化金属焊盘201c和金属焊盘202c以形成金属氧化物，从金属焊盘蚀刻金属氧化物，形成具有良好控制的表面轮廓的金属焊盘，并且首先用接触接合来接合半导体工件，并且之后经受相对低温退火以形成金属焊盘至金属焊盘接合。在混合接合工艺中接合介电表面和金属焊盘。
在图2C中，第二半导体工件202包括多个半导体管芯并且用介电材料206填充第二半导体工件202的邻近的半导体管芯之间的间隙。
在图2D中，衬底204接合至第二半导体工件202。该衬底用以对第一半导体工件201和第二半导体工件202提供机械支撑以促进进一步处理。
在图2E中，减薄第一半导体工件201以减小总厚度并且揭露(暴露)导电通孔205。具体地，通过减薄第一半导体工件201的第一衬底201a实施减薄。
在图2F中，形成金属焊盘207以覆盖并且电连接导电通孔205。金属焊盘207可以包括铝、铜或它们的合金。
在图2G中，在第一半导体工件201和金属焊盘207的顶面上形成用于结构支撑和物理隔离的钝化层208。钝化层208可以保护第一半导体工件201免受机械损坏(粒子/划痕/污染)和其它化学腐蚀的影响。
在图2H中，使用混合接合技术将包括第三衬底203a和第三有源层203b的第三半导体工件203接合至第一半导体工件201。第三有源层103b包括多个微电子元件(未示出)和金属焊盘203c。在混合接合中，以类似于熔融接合的方式接合介电材料，并且使用退火工艺接合金属焊盘。在一个实施例中，金属焊盘201c和金属焊盘203c经受相对低温退火以形成金属焊盘至金属焊盘接合。
在图2I中，减薄第三半导体工件203以减小总厚度(通过减薄第三衬底203a)。在一个实施例中，第三半导体工件203减薄至小于约50微米厚。在一个实施例中，第三半导体工件203减薄至小于约10微米厚。
在一个实施例中，第三半导体工件203包括多个半导体管芯(图2J中所示的两个半导体管芯)。在图2J中，用介电材料209填充位于第三半导体工件203的邻近的半导体管芯之间的间隙。
在图2K中，形成穿过第三半导体工件203的开口210。实际上，开口210穿透第三半导体工件203并且延伸至到达第一半导体工件201。该蚀刻工艺可以产生具有垂直侧壁轮廓或锥形侧壁轮廓的开口。在一个实施例中，开口210具有介于约5和约10之间的高高宽比。在一些实施例中，开口210的高宽比大于10。
在图2L中，导电材料沉积为填充开口210以形成导电通孔211。在一个实施例中，导电通孔211是硅通孔("TSV")。
在图2M中，形成金属焊盘212以覆盖和电连接导电通孔211。金属焊盘212可以包括铝、铜或它们的合金。
在图2N中，在第三半导体工件203上方和金属焊盘212的顶面上形成用于结构支撑和物理隔离的钝化层213。
在图2O中，图案化钝化层213以包括暴露金属焊盘212的开口。在金属焊盘212的暴露的部分上形成导电凸块214。
在图2P中，衬底204从第二半导体工件202剥离。图2P示出了根据本发明的第二方法的实施例制造的半导体结构，其中，导电通孔205和211形成为朝向相反方向的锥形。
参照附图，图3A至图3O示意性地示出了根据本发明的第三实施例的用于制造半导体结构的操作。
在图3A中，提供第一半导体衬底工件301。第一半导体工件301可以包括第一衬底301a和第一有源层301b。第一有源层301b包括多个微电子元件(未示出)和金属焊盘301c。在一个实施例中，第一半导体工件301是已知良好晶圆("KGW")。
在图3B中，包括第二衬底302a和第二有源层302b的第二半导体工件302接合至第一半导体工件301。第二有源层302b包括多个微电子元件(未示出)和金属焊盘302c。如图3B所示，通过混合接合将第二半导体工件302接合至第一半导体工件301。
在图3C中，减薄第二半导体工件302以减小总厚度(通过减薄第二半导体工件302的第二衬底302a)。
在图3D中，第二半导体工件302包括多个半导体管芯并且用介电材料305填充位于第二半导体工件302的邻近的半导体管芯之间的间隙。
在图3E中，衬底304接合至第二半导体工件302。该衬底用以对第一半导体工件301和第二半导体工件302提供机械支撑以促进进一步处理。
在图3F中，在第一半导体工件301上形成接合氧化物层306以促进进一步接合工艺。
在图3G中，使用熔融接合技术将包括第三衬底303a和第三有源层303b的第三半导体工件303接合至接合氧化物层306。第三有源层303b包括多个微电子元件303c。
在图3H中，减薄第三半导体工件303以减小总厚度。在一个实施例中，第三半导体工件303减薄至小于约50微米厚。在一个实施例中，第三半导体工件303减薄至小于约10微米厚。
在一个实施例中，第三半导体工件303包括多个半导体管芯(图3I中所示的两个半导体管芯)。在图3I中，用介电材料307填充位于第三半导体工件303的邻近的半导体管芯之间的间隙。
在图3J中，形成穿过第三半导体工件303和第一半导体工件301的开口308。实际上，开口308穿透第三半导体工件303和第一半导体工件301并且延伸至到达第二半导体工件302。例如，可以使用包括等离子体蚀刻、化学湿蚀刻、激光钻孔和/或本领域中已知的其它工艺的任何合适的蚀刻方法蚀刻开口308。该蚀刻工艺可以产生具有垂直侧壁轮廓或锥形侧壁轮廓的开口。
在图3K中，导电材料沉积为填充开口308以形成电连接第一半导体工件301、第二半导体工件302和第三半导体工件303的微电子元件的导电通孔309。在一个实施例中，导电通孔309是硅通孔("TSV")。
在图3L中，形成金属焊盘310以覆盖和电连接导电通孔309。金属焊盘310可以包括铝、铜或它们的合金。
在图3M中，在第三半导体工件303上方和金属焊盘310的顶面上形成用于结构支撑和物理隔离的钝化层311。
在图3N中，图案化钝化层311以包括暴露金属焊盘310的开口。在金属焊盘310的暴露的部分上形成导电凸块312。
在图3O中，衬底304从第二半导体工件302剥离。图3O示出了根据本发明的第三方法的实施例制造的半导体结构。
图4是根据本发明的一个实施例的示出半导体结构400的截面图。半导体400包含包括第一衬底401a和第一有源层401b的第一半导体工件401、包括第二衬底402a和第二有源层402b的第二半导体工件402(接合至第一半导体工件401)以及包括第三衬底403a和第三有源层403b的第三半导体工件403(接合至第一半导体工件401)。第一有源层401b、第二有源层402b和第三有源层403b全部包括多个微电子元件404和金属焊盘(未示出)。第二半导体工件402和第三半导体工件403可以包括多个半导体管芯(KGD)，并且用介电材料414填充邻近的半导体管芯之间的间隙。半导体结构400包括：将金属焊盘410和412电连接至一些微电子元件404的TSV 406和408；以及将金属焊盘410和412电连接至一些微电子元件404的TSV 407和409。在第三半导体工件303上方和金属焊盘410的顶面上形成钝化层411，并且在第三半导体工件303上方和金属焊盘412的顶面上形成钝化层413。在金属焊盘412的暴露的部分上形成导电凸块415。TSV 406和TSV 408形成为朝向相反方向的锥形并且TSV 407和TSV 409形成为朝向相反方向的锥形。此外，可以提供堆叠在半导体结构400的两侧上的半导体工件。
图5是根据本发明的一个实施例的示出半导体结构500的截面图。半导体结构500包含包括第一衬底和第一有源层的第一半导体工件501、包括第二衬底和第二有源层的第二半导体工件502(接合至第一半导体工件501的一侧)以及包括第三衬底和第三有源层的第三半导体工件503(接合至第一半导体工件501的另一侧)。该半导体结构500还包含包括第一彻底和第一有源层的第四半导体工件504(接合至第三半导体工件503)。在一个实施例中，可以通过将预定数量的半导体工件彼此接合/堆叠(未示出)形成半导体结构500。在一个实施例中，可以利用如图1A至图3O中所示的方法在基半导体工件(未示出)的两侧上接合/堆叠预定数量的半导体工件形成半导体结构500。
图6是根据本发明的一个实施例的示出半导体结构600的截面图。半导体600包括第一半导体工件601、第二半导体工件602(接合至第一半导体工件601的一侧)、第三半导体工件603(接合至第一半导体工件601的另一侧)和第四半导体工件604(接合至第三半导体工件603)。该半导体结构600的特征在于TSV 605和TSV 606布置为堆叠配置("堆叠的TSV")，其中，TSV 605的底端位于TSV 606的顶端之上或邻近于TSV 606的顶端(即，TSV 605和TSV 606是线性对准的)，而TSV 607和TSV 608布置为交错配置("交错的TSV")，其中，TSV607和TSV 608不是线性对准的。在一个实施例中，半导体结构600也可以包括布置为堆叠配置或交错配置或两者的TDV(未示出)。
在一个实施例中，图4的半导体结构400可以作为“集成芯片上系统(SoIC)单元集成并且之后实现为集成扇出(InFo)或衬底上晶圆上芯片(CoWoS)结构。图7A是根据本发明的一个实施例的示出半导体InFo结构700A的示意图。在图7A中，SoIC结构单元701A(可以是图4的半导体结构400)嵌入在电介质/插入器702A内，其中，SoIC结构单元701A的I/O通过金属焊盘704A和导电凸块703A连接至外部电接触件(未示出)。半导体InFo结构700A允许信号扇出区域大于SoIC结构单元701A的硅管芯覆盖区。图7B是根据本发明的一个实施例的示出半导体InFo结构700B的示意图。在图7B中，SoIC结构单元701B(可以是图4的半导体结构400)嵌入在电介质/插入器702B内，其中，SoIC结构单元701B的I/O通过金属焊盘704B和导电凸块703B连接至外部电接触件(未示出)，其中，金属焊盘704B和导电凸块703B的一些连接至通孔结构705B。
图8是根据本发明的一个实施例的示出半导体CoWoS结构800的示意图。在图8中，SoIC结构单元801(可以是图4的半导体结构400)嵌入在电介质802内并且设置在晶圆层803上方。在一个实施例中，晶圆层803是插入器。半导体芯片805也提供在晶圆层803上方，其中，半导体芯片805和SoIC结构单元801通过晶圆层803内的互连件804(例如，TSV)电连接至在衬底807上方提供的导电凸块806(模塑料809内)，并且导电凸块806通过导电凸块808电连接至外部电接触件(未示出)。半导体CoWoS结构800使用互连件808以将多个芯片(例如，半导体芯片805和SoIC结构单元801)集成至单个器件。这种体系结构提供了更高密度的互连件并且减小了全局互连长度，因此，以更小的形状因数产生了增强的性能和减小的功耗。
本发明的一些实施例提供了用于形成半导体结构的方法，包括：提供第一半导体工件；将第二半导体工件接合至第一半导体工件的第一表面；形成穿过第二半导体工件至第一半导体工件的第一导电通孔；将第三半导体工件接合至第一半导体工件的第二表面，第二表面与第一表面相对；并且形成穿过第一半导体工件和第三半导体工件至第二半导体工件的第二导电通孔，从而使得第一导电通孔和第二导电通孔是电连接的。
在上述方法中，其中，将所述第二半导体工件和所述第三半导体工件接合至所述第一半导体工件包括熔融接合、混合接合、共晶接合或附着接合。
在上述方法中，其中，形成所述第一导电通孔包括形成穿过所述第二半导体工件的硅通孔(TSV)或管芯通孔(TDV)以将所述第一半导体工件的第一有源层电连接至所述第二半导体工件的第二有源层。
在上述方法中，其中，形成所述第二导电通孔包括形成穿过所述第三半导体工件的硅通孔(TSV)或管芯通孔(TDV)以将所述第一半导体工件的第一有源层电连接至所述第三半导体工件的第三有源层。
在上述方法中，其中，所述第一导电通孔和所述第二导电通孔形成为朝向相反方向的锥形。
在上述方法中，还包括：在将所述第三半导体工件接合至所述第一半导体工件之前，将衬底接合至所述第二半导体工件并且从所述第二表面减薄所述第一半导体工件；以及在形成所述第二导电通孔之后，剥离所述衬底。
在上述方法中，还包括：在将所述第三半导体工件接合至所述第一半导体工件之前，将衬底接合至所述第二半导体工件并且从所述第二表面减薄所述第一半导体工件；以及在形成所述第二导电通孔之后，剥离所述衬底，其中，减薄所述第一半导体工件包括将所述第一半导体工件减薄至小于10微米厚。
在上述方法中，还包括：在形成所述第二导电通孔之前，将所述第三半导体工件减薄至小于50微米厚。
本发明的一些实施例提供了用于形成半导体结构的方法，包括：提供包括第一衬底和第一有源层的第一半导体工件；将第二半导体工件接合至第一有源层，其中，第二半导体工件包括第二衬底和第二有源层；将第三半导体工件接合至第一衬底，其中，第三半导体工件包括第三衬底和第三有源层；并且形成连接第一有源层、第二有源层和第三有源层的导电通孔。
在上述方法中，其中，形成所述导电通孔包括形成穿过所述第一半导体工件和所述第三半导体工件或穿过所述第一半导体工件、所述第二半导体工件和所述第三半导体工件的硅通孔(TSV)或管芯通孔(TDV)。
在上述方法中，其中，所述第二半导体工件和所述第三半导体工件包括已知良好管芯(KGD)，并且所述第一半导体工件包括已知良好晶圆(KGW)。
在上述方法中，还包括：在将所述第三半导体工件接合至所述第一衬底之前，将衬底接合至所述第二半导体工件并且减薄所述第一衬底；以及在形成所述导电通孔之后，剥离所述衬底。
在上述方法中，其中，形成所述导电通孔包括形成围绕所述导电通孔的绝缘层。
在上述方法中，其中，所述第二半导体工件的所述第二有源层邻近于所述第一半导体工件的所述第一有源层。
在上述方法中，其中，所述第三半导体工件的所述第三有源层邻近于所述第一半导体工件的所述第一衬底。
在上述方法中，还包括将第四半导体工件接合至所述第二半导体工件或所述第三半导体工件。
在上述方法中，还包括将所述第一半导体工件、所述第二半导体工件或所述第三半导体工件减薄至小于50微米厚。
本发明的一些实施例提供了半导体结构，包括：第一半导体工件；接合至第一半导体工件的第一表面的第二半导体工件；接合至第一半导体工件的第二表面的第三半导体工件；以及电连接第一半导体工件、第二半导体工件和第三半导体工件的多个导电通孔，其中，第一导电通孔在朝向第二半导体工件的方向上是锥形的。
在上述半导体结构中，其中，第二导电通孔在朝向所述第三半导体工件的方向上是锥形的。
在上述半导体结构中，其中，所述第一半导体工件、所述第二半导体工件和所述第三半导体工件小于50微米厚。
本发明的方法和特性在上述实例和描述中描述的已经足够。应该明白，在不背离本发明的精神的情况下，任何修改以及改变均包括在本发明保护的范围内。
此外，本发明的范围不旨在限制说明书中描述的工艺、机械、制造以及物质的组成、方式、方法和步骤的特定的实施例。本领域中的技术人员较易地从本方明的公开、目前存在的或以后待开发的工艺、机械、制造、物质的组成、方式、方法或步骤明白，可以根据本发明利用此处描述的相应的实施例实施基本相同的功能或获得基本相同的结果。相应地，所附权利要求旨在包括它们之内的范围(诸如，工艺、机械、制造、物质的组成、方式、方法或步骤/操作)。此外，每个权利要求均构建了单独的实施例，并且各个权利要求和实施例的组成均在本发明的范围内。

Claims (10)

1.一种用于形成半导体结构的方法，包括：
提供第一半导体工件；
将第二半导体工件接合至所述第一半导体工件的第一表面；
形成穿过所述第二半导体工件至所述第一半导体工件的第一导电通孔；
将第三半导体工件接合至所述第一半导体工件的第二表面，所述第二表面与所述第一表面相对；以及
形成穿过所述第一半导体工件和所述第三半导体工件至所述第二半导体工件的第二导电通孔，从而使得所述第一导电通孔和所述第二导电通孔达成电性连接。
2.根据权利要求1所述的方法，其中，将所述第二半导体工件和所述第三半导体工件接合至所述第一半导体工件包括熔融接合、混合接合、共晶接合或附着接合。
3.根据权利要求1所述的方法，其中，形成所述第一导电通孔包括形成穿过所述第二半导体工件的硅通孔(TSV)或管芯通孔(TDV)以将所述第一半导体工件的第一有源层电连接至所述第二半导体工件的第二有源层。
4.根据权利要求1所述的方法，其中，形成所述第二导电通孔包括形成穿过所述第三半导体工件的硅通孔(TSV)或管芯通孔(TDV)以将所述第一半导体工件的第一有源层电连接至所述第三半导体工件的第三有源层。
5.根据权利要求1所述的方法，其中，所述第一导电通孔和所述第二导电通孔形成为朝向相反方向的锥形。
6.根据权利要求1所述的方法，还包括：
在将所述第三半导体工件接合至所述第一半导体工件之前，将衬底接合至所述第二半导体工件并且从所述第二表面减薄所述第一半导体工件；以及
在形成所述第二导电通孔之后，剥离所述衬底。
7.根据权利要求6所述的方法，其中，减薄所述第一半导体工件包括将所述第一半导体工件减薄至小于10微米厚。
8.根据权利要求1所述的方法，还包括：在形成所述第二导电通孔之前，将所述第三半导体工件减薄至小于50微米厚。
9.一种用于形成半导体结构的方法，包括：
提供包括第一衬底和第一有源层的第一半导体工件；
将第二半导体工件接合至所述第一有源层，其中，所述第二半导体工件包括第二衬底和第二有源层；
将第三半导体工件接合至所述第一衬底，其中，所述第三半导体工件包括第三衬底和第三有源层；以及
形成连接所述第一有源层、所述第二有源层和所述第三有源层的导电通孔。
10.一种半导体结构，包括：
第一半导体工件；
第二半导体工件，接合至所述第一半导体工件的第一表面；
第三半导体工件，接合至所述第一半导体工件的第二表面；以及
多个导电通孔，电连接所述第一半导体工件、所述第二半导体工件和所述第三半导体工件，
其中，第一导电通孔在朝向所述第二半导体工件的方向上是锥形的。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022261811A1 (zh) * 2021-06-15 2022-12-22 华为技术有限公司 多晶圆堆叠结构及其制作方法
CN115732467A (zh) * 2021-08-30 2023-03-03 长鑫存储技术有限公司 半导体结构及其形成方法

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11272618B2 (en) 2016-04-26 2022-03-08 Analog Devices International Unlimited Company Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
TWI708358B (zh) 2017-07-11 2020-10-21 聯華電子股份有限公司 半導體裝置及其製造方法
US10600739B1 (en) * 2017-09-28 2020-03-24 Hrl Laboratories, Llc Interposer with interconnects and methods of manufacturing the same
KR102450580B1 (ko) 2017-12-22 2022-10-07 삼성전자주식회사 금속 배선 하부의 절연층 구조를 갖는 반도체 장치
JP7746012B2 (ja) * 2018-01-23 2025-09-30 ルミエンス フォトニクス アイエヌシー． 高性能の三次元半導体構造の製造方法、及びこの製造方法から生成される構造
KR102503233B1 (ko) 2018-01-24 2023-02-24 삼성전자주식회사 반도체 패키지 및 그 제조 방법
EP3525232A1 (en) * 2018-02-09 2019-08-14 Nexperia B.V. Semiconductor device and method of manufacturing the same
US10354980B1 (en) 2018-03-22 2019-07-16 Sandisk Technologies Llc Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same
US10354987B1 (en) * 2018-03-22 2019-07-16 Sandisk Technologies Llc Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US10978424B2 (en) 2018-08-03 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
KR102564324B1 (ko) 2018-10-15 2023-08-07 삼성전자주식회사 반도체 메모리 장치 및 이의 제조 방법
KR102518803B1 (ko) 2018-10-24 2023-04-07 삼성전자주식회사 반도체 패키지
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
KR102593085B1 (ko) 2018-11-21 2023-10-24 삼성전자주식회사 반도체 장치, 반도체 패키지 및 이의 제조 방법
US11562983B2 (en) * 2019-06-28 2023-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package having multiple chips integrated therein and manufacturing method thereof
DE102019211371A1 (de) * 2019-07-30 2021-02-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Herstellen eines elektronischen Schaltungsbauelements und elektronisches Schaltungsbauelement
US11417629B2 (en) * 2020-02-11 2022-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional stacking structure and manufacturing method thereof
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
US11502038B2 (en) * 2020-08-03 2022-11-15 Nanya Technology Corporation Semiconductor structure having via through bonded wafers and manufacturing method thereof
CN114695224A (zh) * 2020-12-29 2022-07-01 联华电子股份有限公司 芯片键合对准结构与键合芯片结构及其制作方法
US12327815B2 (en) * 2022-08-05 2025-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method of forming the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7671460B2 (en) * 2006-01-25 2010-03-02 Teledyne Licensing, Llc Buried via technology for three dimensional integrated circuits
US20090170241A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US8048794B2 (en) * 2009-08-18 2011-11-01 International Business Machines Corporation 3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport
KR101207273B1 (ko) * 2010-09-03 2012-12-03 에스케이하이닉스 주식회사 임베디드 패키지 및 그 형성방법
US8525343B2 (en) * 2010-09-28 2013-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Device with through-silicon via (TSV) and method of forming the same
US20120193785A1 (en) * 2011-02-01 2012-08-02 Megica Corporation Multichip Packages
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US20130168803A1 (en) * 2011-09-16 2013-07-04 Sionyx, Inc. Semiconductor-On-Insulator Devices and Associated Methods
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022261811A1 (zh) * 2021-06-15 2022-12-22 华为技术有限公司 多晶圆堆叠结构及其制作方法
CN115732467A (zh) * 2021-08-30 2023-03-03 长鑫存储技术有限公司 半导体结构及其形成方法

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