CN106951385B - Serial PWM signal decoding circuit and method based on capacitor charging and discharging structure - Google Patents

Abstract

The invention provides a serial PWM signal decoding circuit based on a capacitor charging and discharging structure, comprising: a sequential logic generating circuit, an input end receives a PWM differential signal, and generates sequential logic signals; at least two capacitor charge and discharge decoding modules, an input end They are respectively connected to the output terminals of the sequential logic generating circuit, and are charged and discharged according to the sequential logic signals; during the decoding process, the voltage of the charging and discharging capacitor of the decoding module before charging and discharging is the common mode voltage VCM, and it is charged and discharged after the charging and discharging is completed. The voltage of the node is V _C , and the PWM signal is decoded by judging the polarity of the voltage difference between the two. The invention also provides a serial PWM signal decoding method based on the capacitor charging and discharging structure. The invention has simple structure, does not need synchronous code stream, avoids the use of complex CDR and oversampling structure, realizes PWM signal decoding at different rates, improves signal transmission efficiency and reduces power consumption.

Description

Serial PWM signal decoding circuit and method based on capacitor charging and discharging structure

technical field

The invention relates to the field of integrated circuit design related to an M-PHY interface, in particular to a serial PWM signal decoding circuit and method based on a capacitor charging and discharging structure.

Background technique

In the field of serial interfaces, PWM signals are often used for data transmission in low-speed mode, such as mipi M_PHY. The characteristics of this signal are that the low level time in a UI accounts for 1/3, and the high level accounts for 2/3 to represent data. 1. The low level time accounts for 2/3, and the high level accounts for 1/3 to represent data 0. Its transmission data rate varies from several megahertz to several hundreds of megahertz to meet the needs of saving power consumption under different data transmission volumes, and at the same time in the low-speed mode, the synchronization code is not sent.

At present, the existing solutions use oversampling or realize serial PWM signal decoding based on CDR structure, but all have complex circuit structures, waste redundant power consumption, cannot cover the range of large data rate changes, and even need to cooperate with synchronization codes to achieve decoding Therefore, there is an urgent need for a PWM signal receiving circuit with a simple structure, low power consumption, adapting to different working rates, and without synchronizing data codes.

SUMMARY OF THE INVENTION

(1) Technical problems to be solved

In view of the above technical problems, the present invention provides a serial PWM signal decoding circuit and method based on a capacitor charging and discharging structure. The invention has a simple structure, avoids the use of complex CDR and oversampling structures, and uses programmable charge-discharge capacitors and current-value programmable current sources to realize the decoding of PWM signals at different rates, and at the same time, it can be realized without synchronization codes. Decoding of serial PWM signals improves signal transmission efficiency and saves power consumption.

(2) Technical solutions

According to an aspect of the present invention, a serial PWM signal decoding circuit based on a capacitor charging and discharging structure is provided, comprising:

A sequential logic generating circuit, whose input terminal receives PWM differential signals, and generates sequential logic signals according to the input PWM differential signals;

at least two capacitor charging and discharging decoding modules, whose input ends are respectively connected with the output ends of the sequential logic generating circuit, receive the sequential logic signal sent by the sequential logic generating circuit, and perform charging and discharging according to the sequential logic signal; wherein,

During the decoding process, the voltage of the charging and discharging capacitor of the capacitor charging and discharging decoding module before charging and discharging is the common mode voltage VCM, and the voltage of the charging and discharging node after the charging and discharging is completed is V _C , which is identified by judging the polarity of the voltage difference between the two The PWM signal is thus decoded.

Preferably, the sequential logic generating circuit includes: input ports PWM_P and PWM_N for receiving input low-voltage differential PWM signals; at least two sets of sequential logic output ports, respectively connected to the input of the at least two capacitor charging and discharging decoding modules port connection, wherein the output signals of the first group of sequential logic output ports are SWP1, SWN1, SWR1 and SA1, which are respectively used to control the charging switch SWP, the discharging switch SWN, the reset switch SWR and the SA port of the first capacitor charging and discharging decoding module ; The output signals of the second group of sequential logic output ports are SWP2, SWN2, SWR2 and SA2, which are respectively used to control the charging switch SWP, discharging switch SWN, reset switch SWR and SA port of the second capacitor charging and discharging decoding module.

Preferably, the capacitor charging and discharging decoding module includes: a charging and discharging capacitor C ₀ , whose charging and discharging node C is connected to the input terminal of the common mode voltage VCM through the switch SWR; a current source I _ch , which is connected in series with the switch SWP for The charging and discharging capacitor C ₀ is charged; the current source I _dis is connected in series with the switch SWN for discharging the charging and discharging capacitor C ₀ ; the positive input terminal of the comparator is connected to the charging and discharging node of the charging and discharging capacitor C ₀ C is connected, and its negative input terminal is connected to the common-mode voltage input terminal VCM, which is used to judge the voltage difference polarity between the voltage V _C and the common-mode voltage VCM; the data input port D of the register is connected to the output terminal of the comparator , its data output port Q is connected to the data output terminal DATA of the capacitor charging and discharging decoding module, and its clock port clk is connected to the port SA of the capacitor charging and discharging decoding module for storing the decoding result.

Preferably, when the low level of the PWM signal arrives, the SWN is disconnected and the SWP is closed, and the current source I _ch charges the charge and discharge capacitor C ₀ ; when the high level of the PWM signal arrives, the SWP is disconnected and the SWN is closed, The current source I _dis discharges the charge and discharge capacitor C ₀ .

Preferably, the current source I _ch and the current source I _dis are both programmable current sources, and the currents of the programmable current source I _ch and the programmable current source I _dis vary according to the data rate of the PWM signal, and the higher the data rate The larger the current; the smaller the vice versa.

Preferably, the charge and discharge capacitor C ₀ is a programmable charge and discharge capacitor, and the capacitance value of the charge and discharge capacitor C ₀ changes according to the change of the data rate of the PWM signal, and the larger the data rate, the smaller the capacitance value;

Preferably, the serial PWM signal decoding circuit includes two capacitor charging and discharging decoding modules, and the two capacitor charging and discharging decoding modules work alternately under the control of the sequential logic generating circuit to realize continuous decoding of the serial PWM signal.

Preferably, the two capacitor charging and discharging decoding modules are respectively a first capacitor charging and discharging decoding module and a second capacitor charging and discharging decoding module; wherein, the first capacitor charging and discharging decoding module performs charging and discharging in odd-numbered bits of the serial PWM signal , complete the data register output and the reset of the module at the even-numbered bits; the second capacitor charge-discharge decoding module charges and discharges at the even-numbered bits of the serial PWM signal, and completes the data register output and the reset of the module at the odd-numbered bits; thus the two modules work alternately Achieve continuous decoding of serial PWM signals.

Preferably, the voltage difference between the voltage VC of the charging and discharging node of the charging and discharging capacitor and the voltage difference of the common mode voltage VCM is kept consistent under different data rates, that is, the following relational formula is satisfied:

Among them, UI is the time length of 1bit data, I0 is the charging and discharging current, C0 is the capacitance of the charging and discharging capacitor, and const is a constant.

According to another aspect of the present invention, a method for decoding a serial PWM signal decoding circuit based on a capacitor charging and discharging structure is provided, comprising:

S1: before the arrival of the PWM signal, reset the initial voltage value of the charging and discharging capacitor C ₀ of a capacitor charging and discharging decoding module to the common mode voltage VCM;

S2: When a bit PWM signal arrives, the charging and discharging capacitor C ₀ is charged and discharged respectively during the low and high level periods of the bit PWM signal, and the charging and discharging capacitor C ₀ is completed when the charging and discharging of the bit PWM signal is completed. The voltage of the charging and discharging node C is V _C ;

S3: Determine the voltage difference _ΔV between the voltage V _C and the common mode voltage VCM to identify the PWM signal and decode the polarity.

(3) Beneficial effects

It can be seen from the above technical solutions that the serial PWM signal decoding circuit and method based on the capacitor charging and discharging structure of the present invention have at least one of the following beneficial effects:

(1) The present invention adopts a sequential logic generating circuit and a capacitor charging and discharging decoding module, which can realize the decoding of serial PWM signals without synchronization codes, has a simple structure, avoids the use of complex CDR and oversampling structure, and improves the signal transmission efficiency , saving power consumption.

(2) The present invention adopts a programmable charge-discharge capacitor and a programmable current source with a current value to realize PWM signal decoding at different rates.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings. The same reference numerals refer to the same parts throughout the drawings. The drawings are not intentionally scaled to actual size, and the emphasis is on illustrating the gist of the present invention.

FIG. 1 is a schematic structural diagram of a serial PWM signal decoding circuit based on a capacitor charging and discharging structure according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a capacitor charging and discharging decoding module according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a working sequence of a capacitor charging and discharging decoding module according to an embodiment of the present invention.

4 is a schematic diagram of a sequential logic signal output by a sequential logic generating circuit according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

It should be noted that, in the drawings or descriptions in the specification, the same drawing numbers are used for similar or identical parts. Implementations not shown or described in the drawings are forms known to those of ordinary skill in the art. Additionally, although examples of parameters including specific values may be provided herein, it should be understood that the parameters need not be exactly equal to the corresponding values, but may be approximated within acceptable error tolerances or design constraints. Directional terms mentioned in the embodiments, such as "up", "down", "front", "rear", "left", "right", etc., only refer to the directions of the drawings. Therefore, the directional terms used are used to illustrate and not to limit the scope of protection of the present invention.

FIG. 1 is a schematic structural diagram of a serial PWM signal decoding circuit based on a capacitor charging and discharging structure according to an embodiment of the present invention. Referring to FIG. 1 , the serial PWM signal decoding circuit based on the capacitor charging and discharging structure in this embodiment includes:

A sequential logic generating circuit, whose input terminal receives PWM differential signals, and generates sequential logic signals according to the input PWM differential signals;

At least two capacitor charging and discharging decoding modules, whose input ends are respectively connected with the output ends of the sequential logic generating circuit, receive the sequential logic signal sent by the sequential logic generating circuit, and perform charging and discharging according to the sequential logic signal; The voltage of the charging and discharging capacitor of the capacitor charging and discharging decoding module before charging and discharging is the common mode voltage VCM, and the voltage of the charging and discharging node of the charging and discharging capacitor after the charging and discharging is completed is V _C . By judging the voltage difference between the two to identify the PWM signal to decode it.

Specifically, the serial PWM signal decoding circuit based on the capacitor charging and discharging structure may include two capacitor charging and discharging decoding modules, and the two charging and discharging decoding modules work alternately under the control of the sequential logic generating circuit to realize the serial PWM signal decoding. Continuous decoding.

More specifically, the two capacitor charging and discharging decoding modules are a first capacitor charging and discharging decoding module and a second capacitor charging and discharging decoding module; wherein, the first charging and discharging decoding module can be performed at odd-numbered bits of the serial PWM signal. Charge and discharge, complete the data register output and module reset at the even-numbered bits, the second charge-discharge decoding module can charge and discharge at the even-numbered bits of the serial PWM signal, and complete the data register output and module reset at the odd-numbered bits, so that the two The modules work alternately to achieve continuous decoding of serial PWM signals. Of course, the working order of the two capacitor charge-discharge decoding modules can also be exchanged and alternated.

In addition, the serial PWM signal decoding circuit based on the capacitor charging and discharging structure may also include more than three capacitor charging and discharging decoding modules, and under the control of the sequential logic generating circuit, the three or more capacitor charging and discharging decoding modules work sequentially in sequence, The continuous decoding of the serial PWM signal can be realized. Taking three capacitor charging and discharging decoding modules as an example, the three capacitor charging and discharging decoding modules are a first capacitor charging and discharging decoding module, a second capacitor charging and discharging decoding module, and a third capacitor charging and discharging decoding module; wherein, the first capacitor The charging and discharging decoding module can charge and discharge the first bit of the serial PWM signal, and complete the data register output and module reset during the charging and discharging of the second and third capacitor charging and discharging decoding modules; the second capacitor charging and discharging decoding module can be used in the serial The second bit of the row PWM signal is charged and discharged, and the data register output and module reset are performed during the charging and discharging of the third and first capacitor charging and discharging decoding modules; the third capacitor charging and discharging decoding module can be used in the third bit of the serial PWM signal. Perform charging and discharging, and perform data register output and module reset during the charging and discharging of the first and second capacitor charging and discharging decoding modules, so that the three modules work alternately to realize continuous decoding of serial PWM signals. Of course, the working order of the capacitor charging and discharging decoding module can also be reversed. It only needs to charge and discharge at least one capacitor charging and discharging decoding module during any bit period, while the other capacitor charging and discharging decoding modules perform data register output and module reset in this bit. Can.

Please continue to refer to FIG. 1 , the sequential logic generating circuit includes:

Input ports PWM_P, PWM_N, used to receive the input low-voltage differential PWM signal;

At least two groups of sequential logic output ports are respectively connected to the input ports of the at least two capacitor charging and discharging decoding modules, wherein,

The output signals of the first group of sequential logic output ports are SWP1, SWN1, SWR1, SA1 respectively; SWP1 is used to control the charging switch SWP of the first capacitor charging and discharging decoding module, and SWN1 is used to control the first capacitor charging and discharging decoding module The discharge switch of the decoding module SWN and SWR1 are used to control the reset switch SWR of the first capacitor charging and discharging decoding module, and SA1 is connected to the SA port of the first capacitor charging and discharging decoding module.

Correspondingly, the output signals of the second group of sequential logic output ports are respectively SWP2, SWN2, SWR2, SA2; SWP2 is used to control the charging switch SWP of the second capacitor charging and discharging decoding module, and SWN2 is used to control the second capacitor charging and discharging decoding module. The discharge switches SWN and SWR2 are used to control the reset switch SWR of the second capacitor charging and discharging decoding module, and SA2 is connected to the SA port of the second capacitor charging and discharging decoding module.

FIG. 2 is a circuit diagram of a capacitor charging and discharging decoding module according to an embodiment of the present invention. Please refer to FIG. 2 , the capacitor charging and discharging decoding module in this embodiment includes:

the charging and discharging capacitor C ₀ , the charging and discharging node C is connected to the common mode voltage input terminal VCM through a switch SWR;

a current source I _ch , which is connected in series with a switch SWP for charging the charging and discharging capacitor C ₀ ;

a current source I _dis , which is connected in series with a switch SWN for discharging the charging and discharging capacitor C ₀ ;

Comparator, its positive input terminal is connected to the charging and discharging node C of the charging and discharging capacitor C ₀ , and its negative input terminal is connected to the common mode voltage input terminal VCM.

The data input port D of the register is connected to the output end of the comparator, the data output port Q is connected to the data output end DATA of the capacitor charging and discharging decoding module, and its clock port clk is connected to the port SA of the capacitor charging and discharging decoding module.

Specifically, when the low level of the PWM signal arrives, the SWR is disconnected and the SWP is closed, and the current source I _ch charges the charging and discharging capacitor C ₀ ; when the high level arrives, the SWP is disconnected and the SWN is closed, the The current source I _dis discharges the charge and discharge capacitor C ₀ .

The capacitor charging and discharging decoding module determines the voltage difference _ΔV between the voltage V _C and the common mode voltage VCM through the comparator to identify the polarity of the PWM signal and decode the PWM signal; the decoding result is stored in the register.

Preferably, the current source I _ch and the current source I _dis are both programmable current sources. The currents of the programmable current source I _ch and the programmable current source I _dis vary according to the change of the data rate of the PWM signal, the higher the data rate, the larger the current; otherwise, the smaller the current. The charging and discharging capacitor C ₀ is a programmable charging and discharging capacitor. Among them, the capacitance value of the charge and discharge capacitor C ₀ changes according to the change of the PWM signal data rate. The larger the data rate, the smaller the capacitance value; otherwise, the larger it is.

The working process of the capacitor charging and discharging decoding module according to the embodiment of the present invention is described in detail below. FIG. 3 is a schematic diagram of a working sequence of a capacitor charging and discharging decoding module according to an embodiment of the present invention.

Referring to Figure 3, before the arrival of the PWM signal, the initial voltage of the charging and discharging capacitor is the common mode voltage VCM. When the low level of the first bit PWM signal arrives, the SWN is turned off and the SWP is turned on. If the PWM signal is 0, that is, The low level is 2/3UI (UI is the time length of 1bit data), the high level is 1/3UI, the charging and discharging capacitor C ₀ is charged in 2/3 UI, and the charging current is I ₀ , which arrives at the high level. When the SWP is turned off and the SWN is turned on, the charge and discharge capacitor C ₀ is discharged for 1/3 UI, the discharge current is I ₀ , and the SWN is turned off. At this time, the voltage V _C of the charge and discharge node C of the charge and discharge capacitor C ₀ is equal to There is a positive voltage difference _ΔV in VCM:

If the PWM signal is 1, that is, the low level is 1/3UI, the high level is 2/3UI, the charging and discharging capacitor C ₀ will be charged in 1/3 UI time, and discharged in 2/3 UI time. The current is I ₀ , and SWN is turned off. At this time, the voltage V _C and VCM of the charging and discharging node C of the charging and discharging capacitor C ₀ have a negative voltage difference - _ΔV :

After the first bit PWM signal ends, the voltage of the charging and discharging node C needs to be maintained for a period of time t ₁ to ensure that the comparator correctly identifies _ΔV or _-ΔV and outputs the comparison result of full swing. The SA signal ends at the end of the first bit PWM signal. The rising edge modulation occurs at the next time _t1 , and the register stores the comparator comparison result and outputs it to DATA under the trigger of this rising edge, and completes the decoding of the first bit PWM signal.

SA needs to go low before the end of the second bit PWM signal. SWR delays t ₂ after the rising edge of SA to ensure that the register is closed for a period of time after completing data registration and output, and resets the charging and discharging capacitor voltage to VCM. SWR needs to be disconnected before the end of the second bit PWM signal, and the capacitor charging and discharging decoding module The charging and discharging are completed during the first bit PWM signal, and the data register output and module reset are completed during the second bit PWM signal.

When the input PWM data rate changes, that is, the value of UI changes, in order to ensure that the decoding effect is not affected by the data rate, _ΔV or _-ΔV should be consistent under different data rates. which is:

const is a constant. When the data rate becomes larger and UI becomes smaller, you can increase I ₀ or decrease C ₀ to ensure the normal operation of the capacitor charging and discharging decoding module. When the data rate becomes smaller and UI becomes larger, you can decrease I ₀ or increase C ₀ to ensure the normal operation of the capacitor charging and discharging decoding module.

The following takes the case of two capacitor charging and discharging decoding modules as an example to describe in detail the output sequential logic process of the sequential logic generating circuit according to the embodiment of the present invention. Figure 4 is a schematic diagram of the sequential logic signal output by the sequential logic generation circuit. Before the arrival of the PWM signal, the initial voltage value of the charging and discharging capacitor of the first capacitor charging and discharging decoding module is the common mode voltage VCM. When the low level of the first bit PWM signal arrives, SWR1 When it is disconnected and SWP1 is closed, the charging and discharging capacitor of the first capacitor charging and discharging decoding module is charged during the low level period. When the high level arrives, SWP1 is disconnected and SWN1 is closed. The discharge is carried out during the flat period. After the high level ends, SWN1 is disconnected to complete the charging and discharging process. After a period of t ₁ to ensure that the comparator outputs the correct comparison result, the SA1 signal has a rising edge at t ₁ after the end of the first bit PWM signal. Modulation, the register stores the comparison result of the comparator under the trigger of this rising edge and outputs it to DATA to complete the decoding of the first bitPWM signal.

SA1 needs to go low before the end of the second bit signal. SWR1 delays t ₂ after the rising edge of SA1 to ensure that the register is closed for a period of time after completing data registration and output, and resets the charge and discharge capacitor voltage to VCM. SWR1 needs to be disconnected before the end of the second bitPWM signal, and the first capacitor is charged and discharged to decode The module completes charging and discharging during the first bit PWM signal, and completes data register output and module reset during the second bit PWM signal.

During the period of the first bit PWM signal, the second capacitor charging and discharging decoding module completes initialization. When the low level of the second bit PWM signal arrives, SWR2 is turned off and SWP2 is closed, and the charging and discharging capacitance of the second capacitor charging and discharging decoding module is low. Charging is performed during the high-level period. When the high-level comes, SWP2 is disconnected and SWN2 is closed. The first capacitor is charged and discharged. The charging and discharging capacitor of the decoding module is discharged during the high-level period. In the process, after a period of time t ₁ to ensure that the comparator outputs the correct comparison result, the SA2 signal undergoes a rising edge modulation at time t ₁ after the end of the first bit PWM signal, and the register will compare the result of the comparator under the trigger of this rising edge. Store and output to DATA to complete the decoding of the first bit PWM signal.

SA2 needs to go low before the end of the second bit signal. SWR2 delays t ₂ after the rising edge of SA2 to ensure that the register is closed for a period of time after completing data registration and output, and resets the charge and discharge capacitor voltage to VCM, SWR2 needs to be disconnected before the end of the third bitPWM signal, and the second capacitor is charged and discharged to decode The module completes charging and discharging during the second bit PWM signal, and completes data register output and module reset during the third bit PWM signal.

Under the control of the sequential logic generation circuit, the two capacitor charging and discharging decoding modules work alternately. The first capacitor charging and discharging decoding module performs charging and discharging in the odd-numbered bits of the serial PWM signal, and completes the data register output and module reset in the even-numbered bits. The two-capacitor charging and discharging decoding module charges and discharges the even-numbered bits of the serial PWM signal, and completes the data register output and module reset at the odd-numbered bits. The two modules work alternately to realize the continuous decoding of the serial PWM signal.

In addition, an embodiment of the present invention also provides a serial PWM signal decoding method, including:

S1: before the arrival of the PWM signal, reset the initial voltage value of the charging and discharging capacitor C ₀ of a capacitor charging and discharging decoding module to the common mode voltage VCM;

S2: When a bit PWM signal arrives, the charging and discharging capacitor C ₀ is charged and discharged respectively during the low and high level periods of the bit PWM signal, and the charging and discharging capacitor C ₀ is completed when the charging and discharging of the bit PWM signal is completed. The voltage of the charging and discharging node C is V _C ;

S3: Determine the voltage difference _ΔV between the voltage V _C and the common mode voltage VCM to identify the PWM signal and decode the polarity.

In the present invention, all sequential logic generating circuits capable of generating and driving the above-mentioned at least two capacitor charging and discharging decoding modules to complete the decoding work can be used in the serial PWM signal decoding circuit based on the capacitor charging and discharging structure of the present invention, regardless of the sequential logic generating circuit. The specific manner in which it is implemented falls within the protection scope of the claims of the present invention.

A serial PWM signal decoding circuit and method based on a capacitor charging and discharging structure in the embodiment of the present invention has a simple structure, avoids the use of complex CDR and oversampling structures, and adopts a programmable capacitance value charging and discharging capacitor and a current value programmable current source to The PWM signal decoding at different rates is realized. At the same time, the PWM signal decoding circuit can completely realize the decoding of all received PWM signals without synchronizing the code stream, thus improving the signal transmission efficiency and reducing the power consumption.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, this application is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

It should be noted that, in the accompanying drawings or the text of the description, the implementations that are not shown or described are in the form known to those of ordinary skill in the technical field, and are not described in detail. In addition, the above definitions of each element and method are not limited to various specific structures, shapes or manners mentioned in the embodiments, and those of ordinary skill in the art can simply modify or replace them, for example:

The charging and discharging decoding module can also discharge during the low level period of the PWM signal and charge during the high level period, and the present invention can also be implemented.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (8)

1. a serial PWM signal decoding circuit based on capacitor charge-discharge structure, is characterized in that, comprises: A sequential logic generating circuit, whose input terminal receives PWM differential signals, and generates sequential logic signals according to the input PWM differential signals; at least two capacitor charging and discharging decoding modules, whose input ends are respectively connected with the output ends of the sequential logic generating circuit, receive the sequential logic signal sent by the sequential logic generating circuit, and perform charging and discharging according to the sequential logic signal; wherein, During the decoding process, the voltage of the charging and discharging capacitor of the capacitor charging and discharging decoding module before charging and discharging is the common mode voltage VCM, and the voltage of the charging and discharging node after the charging and discharging is completed is V _C , which is identified by judging the polarity of the voltage difference between the two PWM signal is thus decoded; where, The capacitor charging and discharging decoding module includes: The charging and discharging capacitor C ₀ , and the charging and discharging node C is connected to the input terminal of the common mode voltage VCM through the reset switch SWR; the current source I _ch , the series charging switch SWP is used to charge the charging and discharging capacitor C ₀ ; a current source I _dis , whose series-connected discharge switch SWN is used to discharge the charge and discharge capacitor C ₀ ; A comparator, whose positive input terminal is connected to the charging and discharging node C of the charging and discharging capacitor C ₀ , and whose negative input terminal is connected to the common mode voltage input terminal VCM, is used to judge the voltage difference between the voltage V _C and the common mode voltage VCM polarity; Register, its data input port D is connected to the output end of the comparator, its data output port Q is connected to the data output end DATA of the capacitor charging and discharging decoding module, and its clock port clk is connected to the capacitor charging and discharging decoding module. The port SA is connected to store the decoding result; The at least two capacitor charging and discharging decoding modules work alternately under the control of the sequential logic generating circuit to realize continuous decoding of serial PWM signals; The voltage difference between the voltage V _C of the charging and discharging node of the charging and discharging capacitor and the voltage difference of the common mode voltage VCM remains the same at different data rates, that is, the following relationship is satisfied: Among them, UI is the 1-bit data time length, I ₀ is the charging and discharging current, C ₀ is the capacitance of the charging and discharging capacitor, and const is a constant. 2. The serial PWM signal decoding circuit based on a capacitor charging and discharging structure according to claim 1, wherein the sequential logic generating circuit comprises: The input ports PWM_P and PWM_N are used to receive the input low-voltage differential PWM signal; At least two groups of sequential logic output ports are respectively connected to the input ports of the at least two capacitor charging and discharging decoding modules, wherein, The output signals of the first group of sequential logic output ports are SWP1, SWN1, SWR1 and SA1, which are respectively used to control the charging switch SWP, the discharging switch SWN, the reset switch SWR and the port SA of the first capacitor charging and discharging decoding module; The output signals of the second group of sequential logic output ports are SWP2, SWN2, SWR2 and SA2, respectively used to control the charging switch SWP, discharging switch SWN, reset switch SWR and port SA of the second capacitor charging and discharging decoding module. 3 . The serial PWM signal decoding circuit based on the capacitor charging and discharging structure according to claim 2 , wherein when the low level of the PWM signal arrives, the discharge switch SWN is turned off and the charge switch SWP is turned on, and the current source I _ch charges the charging and discharging capacitor C ₀ ; when the high level of the PWM signal arrives, the charging switch SWP is turned off and the discharging switch SWN is turned on, and the current source I _dis discharges the charging and discharging capacitor C ₀ . 4. The serial PWM signal decoding circuit based on a capacitor charging and discharging structure according to claim 2, wherein the current source I _ch and the current source I _dis are both programmable current sources, and the programmable current source I The currents of _ch and the programmable current source _Idis vary according to the data rate of the PWM signal. The larger the data rate, the larger the current; otherwise, the smaller it is. 5 . The serial PWM signal decoding circuit based on the capacitor charging and discharging structure according to claim 2 , wherein the charging and discharging capacitor C ₀ is a programmable charging and discharging capacitor, and the capacitance value of the charging and discharging capacitor C ₀ is based on the PWM. 6 . The signal data rate changes, the larger the data rate, the smaller the capacitance value; otherwise, the larger it is. 6 . The serial PWM signal decoding circuit based on a capacitor charging and discharging structure according to claim 2 , wherein the serial PWM signal decoding circuit comprises two capacitor charging and discharging decoding modules, the two capacitor charging and discharging decoding The modules work alternately under the control of the sequential logic generating circuit to realize the continuous decoding of serial PWM signals. 7 . The serial PWM signal decoding circuit based on a capacitor charging and discharging structure according to claim 6 , wherein the two capacitor charging and discharging decoding modules are respectively a first capacitor charging and discharging decoding module and a second capacitor charging and discharging decoding module. 8 . decoding module; wherein, The first capacitor charging and discharging decoding module performs charging and discharging in odd-numbered bits of the serial PWM signal, and completes data register output and module reset in even-numbered bits; The second capacitor charging and discharging decoding module performs charging and discharging in the even-numbered bits of the serial PWM signal, and completes data register output and module reset in the odd-numbered bits; thus, the two capacitor charging and discharging decoding modules work alternately to realize the continuous serial PWM signal. decoding. 8. A method for decoding using the serial PWM signal decoding circuit based on the capacitor charge-discharge structure according to any one of claims 1 to 7, characterized in that, comprising: S1: before the arrival of the PWM signal, reset the initial voltage value of the charging and discharging capacitor C ₀ of a capacitor charging and discharging decoding module to the common mode voltage VCM; S2: When a bit PWM signal arrives, the charging and discharging capacitor C ₀ is charged and discharged respectively during the low and high level periods of the bit PWM signal, and the charging and discharging capacitor C ₀ is completed when the charging and discharging of the bit PWM signal is completed. The voltage of the charging and discharging node C is V _C ; S3: Determine the voltage difference ΔV between the voltage V _C and the common mode voltage VCM to identify the PWM signal and decode the polarity.