CN106961273A - Charge pump circuit based on stable state proof and electric leakage-proof safety and the heavy control technology of electric current - Google Patents

Abstract

The invention discloses a charge pump circuit based on steady-state anti-leakage protection and current sink control technology, relates to the technical field of circuit design, and includes an anti-leakage protection module, a current sink control module, a switch module, a current sink and a current source module, and a loop filter modules and buffer modules. The charge pump does not require the exact match between the circuit current sink and the current source, only that the current of the current sink is greater than or equal to the current of the current source. The working conditions of the circuit are easier to meet, and the compound semiconductor charge pump is easier to realize. At the same time, the anti-leakage protection module is realized by using two diodes, the structure of the module is simple, it will not occupy too much chip area, and it is more convenient to integrate. The anti-leakage protection technology uses the unidirectional conductivity of the diode to solve the leakage problem caused by the mismatch between the current source and the current sink in the steady state, so that the output control voltage of the charge pump circuit is constant in the steady state.

Description

Charge pump circuit based on steady-state anti-leakage protection and current sink control technology

technical field

The invention relates to the technical field of circuit design, in particular to a charge pump circuit based on steady-state anti-leakage protection and current sink control technology.

Background technique

With the continuous development of personal wireless communication, radar, terahertz technology and space communication, higher requirements are placed on the transceiver system, including higher frequency, wider bandwidth, higher integration and more Great power etc. The variable frequency source is an important part of the transceiver, and its performance will directly determine the performance of the transceiver. At present, compared with SiCMOS and SiGe BiCMOS processes, compound semiconductor processes have better frequency and power characteristics and are more suitable for designing high-performance variable frequency sources.

Common direct digital frequency synthesizers, charge pump phase-locked loop frequency synthesizers, and hybrid frequency synthesizers can all be used as variable frequency sources. The advantages of direct digital frequency synthesizers are high frequency accuracy and short transition time, but the disadvantage is that the output frequency is relatively low and the ability to suppress spurs is poor; hybrid frequency synthesizers are generally composed of double phase-locked loops or direct digital frequency Synthesizer plus analog phase-locked loop, the advantage is that the output frequency is relatively high, and the ability to suppress strays is strong, but the disadvantage is that the power consumption is large and the integration level is not high; Short change time, strong ability to suppress strays, high integration, low power consumption and so on. Therefore, in order to meet the comprehensive requirements of the transceiver system in various fields, it is of great significance to use compound semiconductors to realize the phase-locked loop of the charge pump.

However, due to some defects of the compound semiconductor technology itself, the development of the charge pump phase-locked loop using this technology is restricted, mainly because the charge pump circuit is difficult to realize. This is because the charge pump is the core circuit of the charge pump phase-locked loop frequency synthesizer, the circuit must contain a current source and a current sink, and the current source is generally implemented by a P-type transistor and the current sink is implemented by an N-type transistor, requiring the current source and The current sink is matched, so that the control voltage output by the charge pump in the steady state is constant, and the entire phase-locked loop can be locked. Since the commonly used Si CMOS and SiGe BiCMOS both have N-type and P-type transistors, this has a great advantage in realizing the matching of current source and current sink. For compound semiconductors, the process has only N-type transistors and no P-type (complementary) transistors, which makes it difficult to match the current source and current sink, which makes it difficult to realize the charge pump. Therefore, the compound semiconductor charge pump phase-locked loop development has been severely restricted.

At present, for compound semiconductor charge pumps, the method of controlling the current sink current is used to solve the mismatch problem between the current source and the current sink, but this method is difficult to accurately match the current magnitude of the current sink and the current source. In a steady state, it is impossible to truly stabilize the control voltage output by the charge pump.

Contents of the invention

The embodiment of the present invention provides a charge pump circuit based on steady-state anti-leakage protection and current sink control technology, which can solve the problems existing in the prior art.

A charge pump circuit based on steady-state anti-leakage protection and current sink control technology, including anti-leakage protection module, current sink control module, switch module, current sink and current source module, loop filter module and buffer module, anti-leakage protection The module consists of two diodes D1 and D2, which are used to prevent charge leakage in the capacitors C _N and C _P caused by the mismatch between the current source and the current sink in the steady state of the charge pump; the current sink control module consists of F1 and F2 It consists of two parts. F1 is composed of two transistors P1 and P3, a source resistor and four diodes, which are used to control the current of the current sink I _DN1 . During the operation of the charge pump, I _DN1 ≥ I _UP1 can be maintained. F2 is composed of Two transistors P2 and P4, a source resistor and four diodes are used to control the current size of the current sink I _DN2 , and can keep I _DN2 ≥ I _UP2 during the charge pump operation; the switch module consists of four transistors UPN, Composed of UPP, DNP and DNN, the gates are all input terminals of the charge pump circuit, and are used to receive four output signals of the previous stage frequency and phase detector circuit; the current sink and current source module consists of two current sources I _UP1 and I _UP2 and two current sinks I _DN1 and I _DN2 are used to charge and discharge the capacitance of the loop filter module; the loop filter module is composed of resistors and capacitors C _N and C _P in series, one end of the module is grounded, and the other end Connect to the input terminal of the buffer module, and affect the change of the control voltage output by the charge pump through the charging and discharging of the capacitor; the buffer module is composed of two transistors P5 and P7, P6 and P8 and two diodes, which are used for the loop filter module The output voltage signal is level-shifted and the influence of the subsequent circuit on the charge pump is eliminated. The input end of the buffer module is connected to the output end of the loop filter module, and the output end is the output end of the entire charge pump. The differential output control voltage signal V _CN and V _CP are sent to the voltage-controlled oscillator circuit of the latter stage;

In the anti-leakage protection module, the anode of the diode D1 is connected to the gate and the source resistor of the current source I _UP1 , the cathode is connected to the drain of the switch DNP, and the anode of the diode D2 is connected to the gate and the source resistor of the current source I _UP2 , The negative pole is connected to the drain of the switch UPP; the input terminals of F1 and F2 in the current sink control module are respectively connected to the drains of the switches UPP and DNP, and the output terminals are respectively connected to the gates of the current sink I _DN1 and I _DN2 , and the transistor P1 in F1 The gate of the transistor P1 is the input terminal of F1, which is connected to the cathode of the diode D2 and the drain of the switch UPP, the drain of the transistor P1 is connected to the power supply VDD, the source of the transistor P1 is connected to the anode of the first diode, and the cathode of the first diode is connected to The anode of the second diode, the cathode of the second diode is connected to the anode of the third diode, the cathode of the third diode is connected to the anode of the fourth diode, the cathode of the fourth diode is connected to the drain of the transistor P3, the transistor The drain of P3 is short-circuited to the grid, and the grid is connected to the grid of current sink I _DN1 ; the grid of transistor P2 in F2 is the input terminal of F2, connected to the negative pole of diode D1 and the drain of switch DNP, and the drain of transistor P2 The drain is connected to the power supply VDD, the source of the transistor P2 is connected to the anode of the first diode, the cathode of the first diode is connected to the anode of the second diode, the cathode of the second diode is connected to the anode of the third diode, and the third diode The cathode of the diode is connected to the anode of the fourth diode, the drain of the cathode transistor P4 of the fourth diode is connected, the drain of the transistor P4 is shorted to the gate, and the gate is connected to the gate of the current sink I _DN2 ;

The switches UPN and UPP in the switch module are connected to the drain of the current sink I _DN1 , the sources of the switches DNP and DNN are connected to the drain of the current sink I _DN2 ; the drains of the current sources I _UP1 and I _UP2 in the current sink and current source module The pole is connected to the power supply VDD, the gate and source of I _UP1 are connected to both ends of the source resistance of I _UP1 , the gate and source of I _UP2 are connected to both ends of the source resistance of I _UP2 , and the current sink The sources of I _DN1 and I _DN2 are respectively connected to one end of the respective source resistors, and the other ends of the source resistors are connected to the power supply VTT; the size of the power supply VDD is a high potential, and the size of the power supply VTT is a low potential;

Among the resistors and capacitors C _N connected in series in the loop filter module, one end of the resistor is connected to the gate of the transistor P1, and one end of the capacitor C _N is grounded; among the series resistors and capacitors C _P , one end of the resistor is connected to the gate of the transistor P2, and the capacitor C is connected to the gate of the transistor P2. One end of C _P is grounded;

The source of the transistor P5 in the buffer module is connected to the power supply VDD, the gate is connected to the gate of the transistor P1, the drain is connected to the anode of the first diode, the cathode of the first diode is connected to the anode of the second diode, and the The negative pole is connected to the source of the transistor P7, while the negative pole of the second diode outputs the voltage V _CN , the drain and source of the transistor P7 are short-circuited, and connected to the power supply VTT; the source of the transistor P6 is connected to the power supply VDD, and the gate is connected to the transistor P2 The gate of the first diode, the drain is connected to the positive pole of the first diode, the negative pole of the first diode is connected to the positive pole of the second diode, the negative pole of the second diode is connected to the source of the transistor P8, and the negative pole of the second diode outputs the voltage V _CP , the drain and source of the transistor P8 are shorted, and connected to the power supply VTT.

Preferably, the circuit adopts compound semiconductor technology, including GaAs MESFET, GaAs PHEMT and InPPHEMT technology.

Preferably, current sources I _UP1 and I _UP2 , switches UPN, UPP, DNP and DNN, transistors P1, P2, P5, P6, P7 and P8 are all depletion transistors; current sinks I _DN1 and I _DN2 , transistors P3 and P4 are enhancement transistors.

Compared with the prior art, the present invention has the following advantages:

First, starting from the compound semiconductor process, the present invention overcomes the problem that the charge pump is difficult to realize due to the lack of complementary transistors in the technology. The charge pump proposed by the present invention does not require the circuit current sink to be exactly matched (completely equal) to the current source, and only needs to satisfy that the current of the current sink is greater than or equal to the current of the current source. The working conditions of the circuit are easier to meet, and the compound semiconductor charge pump is easier to realize.

Second, the anti-leakage protection module is realized by two diodes, the structure of the module is simple, it will not occupy too much chip area, and it is more convenient to integrate. The anti-leakage protection technology uses the unidirectional conductivity of the diode to solve the leakage problem caused by the mismatch between the current source and the current sink in the steady state, so that the output control voltage of the charge pump circuit is constant in the steady state.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a structural diagram of a charge pump circuit based on steady-state anti-leakage protection and current sink control technology provided by an embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Referring to Fig. 1, the charge pump circuit based on steady-state anti-leakage protection and current sink control technology provided in the embodiment of the present invention includes an anti-leakage protection module, a current sink control module, a switch module, a current sink and a current source module, and a loop Filter module and buffer module. The overall charge pump circuit is in differential form, and the process is a compound semiconductor process; the anti-leakage protection module is composed of two diodes D1 and D2, which are used to prevent the capacitance C caused by the mismatch between the current source and the current sink in the steady state of the charge pump. Charge leakage phenomenon in _N and C _P ; the current sink control module is composed of two parts F1 and F2, F1 is composed of two transistors P1 and P3, a source resistor and four diodes, used to control the current size of the current sink I _DN1 , can keep I _DN1 ≥ I _UP1 during the working process of the charge pump, F2 is composed of two transistors P2 and P4, a source resistor and four diodes, used to control the current of the current sink I _DN2 , during the working process of the charge pump Can keep I _DN2 ≥ I _UP2 ; The switch module is made up of four transistors UPN, UPP, DNP and DNN, and the gate is the input terminal of the charge pump circuit, and is used to receive the four-way Output signal; the current sink and current source module is composed of two current sources I _UP1 and I _UP2 and two current sinks I _DN1 and I _DN2 , which are used to charge and discharge the capacitor of the loop filter module; the loop filter module is composed of series Composed of resistors and capacitors C _N and C _P , one end of the module is grounded, the other end is connected to the input end of the buffer module, and the change of the control voltage output by the charge pump is affected by the charge and discharge of the capacitor; the buffer module is composed of two transistors P5 and P7 respectively It is composed of P6, P8 and two diodes, which are used to level-shift the voltage signal output by the loop filter module and eliminate the influence of the subsequent circuit on the charge pump. The input end of the buffer module is connected to the output end of the loop filter module , the output terminal is the output terminal of the entire charge pump, and the differential output control voltage signals V _CN and V _CP are sent to the voltage-controlled oscillator circuit of the subsequent stage.

In the anti-leakage protection module, the anode of the diode D1 is connected to the gate and the source resistor of the current source I _UP1 , the cathode is connected to the drain of the switch DNP, and the anode of the diode D2 is connected to the gate and the source resistor of the current source I _UP2 , The negative pole is connected to the drain of the switch UPP; the input terminals of F1 and F2 in the current sink control module are respectively connected to the drains of the switches UPP and DNP, and the output terminals are respectively connected to the gates of the current sink I _DN1 and I _DN2 , and the transistor P1 in F1 The gate of the transistor P1 is the input terminal of F1, which is connected to the cathode of the diode D2 and the drain of the switch UPP, the drain of the transistor P1 is connected to the power supply VDD, the source of the transistor P1 is connected to the anode of the first diode, and the cathode of the first diode is connected to The anode of the second diode, the cathode of the second diode is connected to the anode of the third diode, the cathode of the third diode is connected to the anode of the fourth diode, the cathode of the fourth diode is connected to the drain of the transistor P3, the transistor The drain of P3 is short-circuited to the grid, and the grid is connected to the grid of current sink I _DN1 ; the grid of transistor P2 in F2 is the input terminal of F2, connected to the negative pole of diode D1 and the drain of switch DNP, and the drain of transistor P2 The drain is connected to the power supply VDD, the source of the transistor P2 is connected to the anode of the first diode, the cathode of the first diode is connected to the anode of the second diode, the cathode of the second diode is connected to the anode of the third diode, and the third diode The cathode of the diode is connected to the anode of the fourth diode, the cathode of the fourth diode is connected to the drain of the transistor P4, the drain of the transistor P4 is short-circuited to the gate, and the gate is connected to the gate of the current sink I _DN2 .

The switches UPN and UPP in the switch module are connected to the drain of the current sink I _DN1 , the sources of the switches DNP and DNN are connected to the drain of the current sink I _DN2 ; the drains of the current sources I _UP1 and I _UP2 in the current sink and current source module The pole is connected to the power supply VDD, the gate and source of I _UP1 are connected to both ends of the source resistance of I _UP1 , the gate and source of I _UP2 are connected to both ends of the source resistance of I _UP2 , and the current sink The sources of I _DN1 and I _DN2 are respectively connected to one end of their respective source resistors, and the other ends of the source resistors are both connected to the power supply VTT; the power supply VDD is at a high potential, and the power supply VTT is at a low potential.

Among the resistors and capacitors C _N connected in series in the loop filter module, one end of the resistor is connected to the gate of the transistor P1, and one end of the capacitor C _N is grounded; among the series resistors and capacitors C _P , one end of the resistor is connected to the gate of the transistor P2, and the capacitor C is connected to the gate of the transistor P2. One end of C _P is grounded.

The source of the transistor P5 in the buffer module is connected to the power supply VDD, the gate is connected to the gate of the transistor P1, the drain is connected to the anode of the first diode, the cathode of the first diode is connected to the anode of the second diode, and the The negative pole is connected to the source of the transistor P7, while the negative pole of the second diode outputs the voltage V _CN , the drain and source of the transistor P7 are short-circuited, and connected to the power supply VTT; the source of the transistor P6 is connected to the power supply VDD, and the gate is connected to the transistor P2 The gate of the first diode, the drain is connected to the positive pole of the first diode, the negative pole of the first diode is connected to the positive pole of the second diode, the negative pole of the second diode is connected to the source of the transistor P8, and the negative pole of the second diode outputs the voltage V _CP , the drain and source of the transistor P8 are shorted, and connected to the power supply VTT.

The compound semiconductor processes that can be used are GaAs MESFET, GaAs PHEMT and InP PHEMT processes; current sources I _UP1 and I _UP2 , switches UPN, UPP, DNP and DNN, and transistors P1, P2, P5, P6, P7 and P8 are all depleted type transistors; current sinks I _DN1 and I _DN2 , and transistors P3 and P4 are enhancement type transistors.

The working principle of the present invention is as follows.

The four signals output by the frequency and phase detector of the previous stage of the charge pump will be input to the four switches UPN, UPP, DNP and DNN of the charge pump. There will be three working states in the circuit, two of which are unstable states. , one is steady state. Here, "0" and "1" are used to represent low level and high level respectively. When the switch is connected to low level, the switch state is off; when the switch is connected to high level, the switch is closed. The initial state of the circuit should satisfy I _DN1 ≥ I _UP1 , I _DN2 ≥ I _UP2 . V _CP and V _CN are the control voltage signals output by two channels of the charge pump respectively, which can be connected to the voltage-controlled oscillator of the subsequent stage in the way of V _CP -V _CN .

In the case of non-steady state, when UPN=0, UPP=1, DNP=0, DNN=1 (when the reference frequency of the charge pump phase-locked loop is ahead of the comparison frequency output by the frequency divider), I _UP2 flows into I _DN1 and In I _DN2 , since both I _DN1 and I _DN2 are greater than I _UP2 , I _UP2 will not charge _CN , and I _DN1 can extract the charge in _CN to reduce the voltage of V _C1 . The reduction of V _C1 due to the channel length modulation effect will increase the current of I _UP2 , and at the same time, the effect of F1 will also reduce V _F1 so that the current of I _DN1 will decrease. Since V _C1 and V _CN are the input and output signals of the buffer module respectively, V CN will also decrease along with V _C1 . Because UPN ₌ 0, DNP ₌ 0, I _UP1 has only one path to CP, and I _UP1 will charge CP to increase the voltage of V _C2 . Similarly, the increase of V _C2 will cause the current of I _UP1 to decrease and the current of I _DN2 to increase, and V _CP will also increase with V _C2 . At this time, the control voltage (V _CP -V _CN ) will increase, and the output frequency of the voltage-controlled oscillator circuit of the subsequent stage will increase.

In the case of non-steady state, when UPN=1, UPP=0, DNP=1, DNN=0 (when the reference frequency of the charge pump phase-locked loop lags behind the comparison frequency output by the frequency divider), I _UP1 flows into I _DN1 and In I _DN2 , since both I _DN1 and I _DN2 are greater than I _UP1 , so I _UP1 will not charge _{CP, and I DN2 can extract} the charge from CP to reduce the voltage of V _C2 . The reduction of V _C2 due to the channel length modulation effect will increase the current of I _UP1 , and at the same time, the effect of F2 will also reduce V _F2 so that the current of I _DN2 will decrease. Since V _C2 and V _CP are the input and output signals of the buffer module respectively, V _CP will also decrease along with V _C2 . Because UPP=0, DNN=0, there is only one path from IUP2 to _CN , and _IUP2 will charge _CN to increase the voltage of V _C1 . Similarly, the increase of V _C1 will cause the current of I _UP2 to decrease and the current of I _DN1 to increase, and V _CN will also increase with V _C1 . At this time, the control voltage (V _CP -V _CN ) will decrease, and the output frequency of the voltage-controlled oscillator circuit of the subsequent stage will decrease.

Steady-state situation, when UPN=1, UPP=0, DNP=0, DNN=1 (when the reference frequency of the charge pump phase-locked loop is equal to the comparison frequency output by the frequency divider), the I _UP1 current flows into I _DN1 , I _UP2 current flows into I _ND2 . Since I _DN1 ≥ I _UP1 , I _DN2 ≥ I _UP2 , so I _UP1 and I _UP2 will not have additional current flow into C _P and C _N ; in addition, the diode with unidirectional conductivity in the anti-leakage protection module ensures that when the current When the current in the sink is greater than the current in the current source, the charge in the capacitor will not be drawn into the current sink, and the voltages of V _C1 and V _C2 will remain unchanged. At this time, the control voltage (V _CP -V _CN ) is fixed, the output frequency of the subsequent voltage-controlled oscillator circuit will not change, and the entire phase-locked loop is in a locked state.

While preferred embodiments of the invention have been described, additional changes and modifications to these embodiments can be made by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment as well as all changes and modifications which fall within the scope of the invention.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (3)

1. A charge pump circuit based on steady-state anti-leakage protection and current sink control technology, characterized in that it includes an anti-leakage protection module, a current sink control module, a switch module, a current sink and a current source module, a loop filter module and The buffer module and the anti-leakage protection module are composed of two diodes D1 and D2, which are used to prevent the leakage of charges in the capacitors C _N and C _P caused by the mismatch between the current source and the current sink in the steady state of the charge pump; the current sink The control module is composed of two parts, F1 and F2. F1 is composed of two transistors P1 and P3, a source resistor and four diodes, which are used to control the current of the current sink I _DN1 , and can maintain the I _DN1 during the charge pump operation. ≥I _UP1 , F2 is composed of two transistors P2 and P4, a source resistor and four diodes, used to control the current of the current sink I _DN2 , and can maintain I _DN2 ≥I _UP2 during the charge pump operation; switch module It is composed of four transistors UPN, UPP, DNP and DNN, and the gates are the input terminals of the charge pump circuit, which are used to receive the four output signals of the previous stage frequency and phase detector circuit; the current sink and current source modules are composed of two A current source I _UP1 and I _UP2 and two current sinks I _DN1 and I _DN2 are used to charge and discharge the capacitance of the loop filter module; the loop filter module is composed of series resistors and capacitors C _N and C _P , the One end of the module is grounded, and the other end is connected to the input end of the buffer module, which affects the change of the control voltage output by the charge pump through the charging and discharging of the capacitor; the buffer module is composed of two transistors P5 and P7, P6 and P8, and two diodes. In order to perform level conversion on the voltage signal output by the loop filter module and eliminate the impact of the subsequent circuit on the charge pump, the input end of the buffer module is connected to the output end of the loop filter module, and the output end is the output end of the entire charge pump. The differential output control voltage signals V _CN and V _CP are sent to the voltage-controlled oscillator circuit of the subsequent stage; In the anti-leakage protection module, the anode of the diode D1 is connected to the gate and the source resistor of the current source I _UP1 , the cathode is connected to the drain of the switch DNP, and the anode of the diode D2 is connected to the gate and the source resistor of the current source I _UP2 , The negative pole is connected to the drain of the switch UPP; the input terminals of F1 and F2 in the current sink control module are respectively connected to the drains of the switches UPP and DNP, and the output terminals are respectively connected to the gates of the current sink I _DN1 and I _DN2 , and the transistor P1 in F1 The gate of the transistor P1 is the input terminal of F1, which is connected to the cathode of the diode D2 and the drain of the switch UPP, the drain of the transistor P1 is connected to the power supply VDD, the source of the transistor P1 is connected to the anode of the first diode, and the cathode of the first diode is connected to The anode of the second diode, the cathode of the second diode is connected to the anode of the third diode, the cathode of the third diode is connected to the anode of the fourth diode, the cathode of the fourth diode is connected to the drain of the transistor P3, the transistor The drain of P3 is short-circuited to the grid, and the grid is connected to the grid of current sink I _DN1 ; the grid of transistor P2 in F2 is the input terminal of F2, connected to the negative pole of diode D1 and the drain of switch DNP, and the drain of transistor P2 The drain is connected to the power supply VDD, the source of the transistor P2 is connected to the anode of the first diode, the cathode of the first diode is connected to the anode of the second diode, the cathode of the second diode is connected to the anode of the third diode, and the third diode The cathode of the diode is connected to the anode of the fourth diode, the drain of the cathode transistor P4 of the fourth diode is connected, the drain of the transistor P4 is shorted to the gate, and the gate is connected to the gate of the current sink I _DN2 ; The switches UPN and UPP in the switch module are connected to the drain of the current sink I _DN1 , the sources of the switches DNP and DNN are connected to the drain of the current sink I _DN2 ; the drains of the current sources I _UP1 and I _UP2 in the current sink and current source module The pole is connected to the power supply VDD, the gate and source of I _UP1 are connected to both ends of the source resistance of I _UP1 , the gate and source of I _UP2 are connected to both ends of the source resistance of I _UP2 , and the current sink The sources of I _DN1 and I _DN2 are respectively connected to one end of the respective source resistors, and the other ends of the source resistors are connected to the power supply VTT; the size of the power supply VDD is a high potential, and the size of the power supply VTT is a low potential; Among the resistors and capacitors C _N connected in series in the loop filter module, one end of the resistor is connected to the gate of the transistor P1, and one end of the capacitor C _N is grounded; among the series resistors and capacitors C _P , one end of the resistor is connected to the gate of the transistor P2, and the capacitor C is connected to the gate of the transistor P2. One end of C _P is grounded; The source of the transistor P5 in the buffer module is connected to the power supply VDD, the gate is connected to the gate of the transistor P1, the drain is connected to the anode of the first diode, the cathode of the first diode is connected to the anode of the second diode, and the The negative pole is connected to the source of the transistor P7, while the negative pole of the second diode outputs the voltage V _CN , the drain and source of the transistor P7 are short-circuited, and connected to the power supply VTT; the source of the transistor P6 is connected to the power supply VDD, and the gate is connected to the transistor P2 The gate of the first diode, the drain is connected to the positive pole of the first diode, the negative pole of the first diode is connected to the positive pole of the second diode, the negative pole of the second diode is connected to the source of the transistor P8, and the negative pole of the second diode outputs the voltage V _CP , the drain and source of the transistor P8 are shorted, and connected to the power supply VTT. 2. The circuit according to claim 1, wherein the circuit adopts a compound semiconductor process, including GaAsMESFET, GaAs PHEMT and InP PHEMT processes. 3. The circuit according to claim 1, wherein the current sources _IUP1 and _IUP2 , the switches UPN, UPP, DNP and DNN, and the transistors P1, P2, P5, P6, P7 and P8 are all depletion transistors ; Current sinks I _DN1 and I _DN2 , transistors P3 and P4 are enhancement transistors.