CN106980587B - General input/output time sequence processor and time sequence input/output control method - Google Patents

Abstract

The invention relates to a universal input and output timing processor and a timing input and output control method, which is composed of a bus interface bridge, a processor register file, a timing control state machine, a timing generation counter, a timing RAM memory, and a serial-to-parallel conversion controller. The processor register file contains several sets of sequence control registers. The beneficial effects of the present invention are: realizing a universal protocol that supports various digital port input and output timing change requirements, coping with various complex and changeable digital interface protocols; reducing the chip development cycle; and lower power consumption.

Description

A universal input and output timing processor and timing input and output control method

Technical field

The invention relates to the technical field of processors, and specifically relates to a universal input and output timing processor and a timing input and output control method.

Background technique

In existing chips, if you want to implement various digital interfaces, you must add its controller internally. For example, to implement the SPI interface, you must add an SPI controller, to add a UART interface, you must add a UART controller, and to implement read and write access to off-chip SRAM, you must add an SRAM controller. However, the application scenarios of these chips are different for different users. Some customers do not need SPI, but the chip is integrated; some customers need XXX interface, but the chip is not integrated; some customers need 8-channel PWM interface, but the chip only integrates 2 channels. The chip integrates interfaces that customers do not need, resulting in a decrease in cost performance and unnecessary power consumption. Moreover, designing each interface will be more complicated, prolonging the cycle of chip development and production, and also leading to increased costs. At the same time, the addition of too many interfaces makes the chip design complex, has too many loopholes, and increases the probability of errors.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a universal input-output timing processor.

A universal input and output timing processor and a timing input and output control method provided by the present invention are realized through the following technical solutions:

A general input and output timing processor, consisting of a bus interface bridge, a processor register file, a timing control state machine, a timing generation counter, a timing RAM memory, and a serial-to-parallel conversion controller. The processor register file contains multiple sequence controls register group, where:

The bus interface bridge is connected to the processor register file and the sequential RAM memory respectively. The bus interface bridge receives various commands of the CPU from the bus and passes them to each register, which plays a role in command format conversion;

The processor register file is connected to the timing control state machine, and the processor register file is used to temporarily store the processing data of the processor;

The timing control state machine is connected to a timing generation counter. The timing control state machine is composed of an instruction controller, a decoder, and an executor. The instruction fetcher is used to read the control code, and the decoder is used to analyze the code and translate it into an executor for convenience. Execution control code, the executor is used to cooperate with the counter to implement specific control;

The timing generation counter is connected to the timing RAM memory;

The sequential RAM memory is connected to the serial-to-parallel conversion controller group. The sequential RAM memory stores the control codes of each sequence to facilitate the reading of the sequence state machine and the serial-to-parallel conversion controller. The serial-to-parallel conversion controller is used to complete the bit width conversion, from The sequential RAM memory reads the data and then transfers it to the designated pin in turn;

In the sequence control register group, each sequence control register group corresponds to one sequence control.

The serial-to-parallel conversion controller is bidirectional and can read data from the pin currently set as input and write it to a designated location in the memory.

A timing input and output control method that uses the method of exchanging data between chip pins and RAM. Under the control of the controller, when set to output, data is read from RAM and output to the chip pin; when set to input When, the data is read from the chip pin and written to the RAM. There are two RAMs in Figure 2. One RAM (data RAM) stores input and output sequence data. When output, the data in RAM is written to the chip pin. When input is read the data from the chip pins is written to RAM. Another RAM (direction control RAM) stores the input and output direction selection control sequence of the sequence. Under the control of the controller, as the sequence occurs, the input in the RAM is sequentially read and written into the input and output direction selection register of the chip pin, which controls the input and output direction of the chip. It also controls whether the data RAM is currently reading or writing according to the direction. ;

Store one or more sequences in RAM, when only one sequence is running or no sequence is running at the same time; each sequence corresponds to a sequence control register group, with at least 4 registers set in the group, using the baud rate The register controls the speed of this sequence;

The first address register of the sequence stores the starting address of this sequence stored in RAM, and the tail address register stores the end address of this sequence stored in RAM; the control register specifies the attributes of this sequence.

Common attributes are:

1. Directional flexibility control. The direction of this sequence can be controlled using a dedicated RAM storage as described above. This provides high flexibility and can switch the direction at any time as the sequence occurs. However, this attribute can also be used to indicate that this sequence is only input, or only output, or supports both input and output. If input or output only is specified, the direction control RAM will not be read while this sequence occurs.

2. Serial to parallel conversion settings. What is described above is a setup without serial-to-parallel conversion. One RAM read or write can be 1 byte (8 bits), 2 bytes (16 bits) or 4 bytes (32 bits), etc. (This article uses 1 byte as an example. ), each bit corresponds to 1 pin of the chip. But there is also a setting with serial-to-parallel conversion, that is, the data of a RAM corresponds to a pin. When writing to a pin, the data read by the RAM needs to be converted from parallel to serial into a bit stream each time. , sent to one pin of the chip in turn; when the pin is to be read, the data on the pin is converted from serial to parallel data, and then written into RAM. When serial-to-parallel conversion is required, if the direction control of the sequence is provided by RAM, then the data read out from the direction control RAM must also be converted from parallel to serial. If it is provided by the control register of this sequence, it is not needed.

3. Sequence start condition control. A controller can have several sets of sequence control register sets to support multiple sequence occurrences. The starting conditions for each sequence include:

(1) When the designated chip pin has a rising edge;

(2) When the specified chip pin has a falling edge;

(3) When the designated chip pin has a rising edge or falling edge;

(4) When the specified chip pin is equal to 0;

(5) When the specified chip pin is equal to 1;

(6) When the input and output timing processor receives other CPU commands to start;

(7) When a sequence of other specified input and output timing processors (one chip can have multiple input and output timing processors) starts, it starts at the same time;

(8) Start when a specified sequence ends;

4. Big and small endian control. Indicates whether to send the high-order bit or low-order bit of the byte first during serial transmission.

The beneficial effects of the present invention are:

1. Implement a universal protocol that supports input and output timing changes of various digital ports and copes with various complex and changeable digital interface protocols;

2. Each port only needs to support one universal input and output timing processor, reducing the chip development cycle;

3. Lower power consumption;

4. Can be used in various chips with input and output digital interfaces. During the application process, timing processors can also be classified according to application scenarios for simplification. For example, the timing processor on some ports only supports serial input (read the value on a certain pin, convert it into serial data and write it into byte data into RAM) or output (convert RAM byte data into serial data and output it to a certain pin); the timing processor on some ports only supports parallel input (for example, reading data on 8 pins simultaneously and writing it to RAM as 1 byte) or output (for example, reading from RAM 1 byte parallel output to 8 pins), no serial-to-parallel conversion is performed; the timing processor on some ports supports parallel output, but does not support parallel input, etc. These are classifications made to simplify the design based on actual conditions.

Description of the drawings

Figure 1 is a schematic structural diagram of a general-purpose input and output timing processor;

Figure 2 is a schematic diagram of a timing input and output control method;

Figure 3 is a schematic diagram of the serial-to-parallel conversion setup.

Detailed ways

The technical solution of the present invention will be clearly and completely described below through examples. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present invention.

Definition of English abbreviations in this article: CPU: Central Processing Unit; GPIO: General Input and Output Port; MUX: Multiplexer; IIC: Integrated Circuit Bus; UART: Universal Asynchronous Receiver and Transmitter; PWM: Pulse Width Modulation; RAM: Random Memory Access memory; SPI: Serial Peripheral Interface; Peripheral IP: In the reusable design methodology of integrated circuits, IP core, the full name is intellectual property core (English: intellectual property core), refers to the form provided by a certain party. Logic units, reusable modules for chip design.

Example 1:

As shown in Figure 1, a general-purpose input and output timing processor is composed of a bus interface bridge, a processor register file, a timing control state machine, a counter, a timing RAM memory, and a serial-to-parallel conversion controller.

The bus interface bridge is used to receive various commands of the CPU from the bus and pass them to various registers. It functions as a command format conversion.

The processor register file contains several sequence control register groups (each register group corresponds to one sequence control), which are used to temporarily store the processing data of the processor. The sequence head address register records the starting address in the memory where the sequence is to occur, and the sequence tail address register records the end address in the memory where the sequence is to occur. The sequence control register has direction flexibility control, serial-to-parallel conversion, start conditions, big and small endian control, sequence length control, occurrence number control, bit enable, etc.

The sequence length controls the length of the sequence to occur and the number of times the sequence occurs. The maximum sequence length is limited by the size of the memory, and the capacity of the sequential memory is determined according to the application scenario and system specifications. The larger the capacity, the larger the maximum sequence length. The minimum sequence length is 1 bit. Also note that there is not only one sequence stored in the memory, but multiple sequences can be stored. The sequence and number of occurrences of each sequence can also be controlled through a program.

The number of occurrences of each sequence ranges from just one to countless (i.e., continuous occurrences). The conditions for each sequence to start are: 1. Start directly under the control of the CPU; 2. Start when a certain sequence ends or start at the same time as a certain sequence; 3. When the specified rising edge, falling edge, edge appears on the input pin (rising edge or falling edge), starts when equal to 0 or equals to 1. These conditions must be configured into the control register by the CPU in advance. The Sequence Speed register controls how fast the sequence is to occur, i.e. how many clock cycles each bit takes. Support setting different speeds for each sequence.

The bit enable determines which pins participate in this sequence.

The sequence control state machine is the central controller that determines and implements each step of the sequence. The counter matched with it plays the role of timing auxiliary control. The sequence control state machine consists of 3 controllers. The pointer is used to read the control code, and the decoder is used to analyze the code and translate it into a code that the executor can easily execute control. The actuator is used to cooperate with the counter to implement specific control.

The sequential RAM memory stores the control code of each sequence, which is convenient for reading by the sequence state machine and the serial-to-parallel conversion controller. The CPU can access this RAM memory like an ordinary RAM memory, so when the sequence processor is not working, this RAM memory can be used as a general memory for the CPU.

Because the bit width of the data read from the memory and the data written is fixed, and the number of pins applied to each sequence is different, the number of the pins is also different. For example, sequence A controls 4 pins, namely pins 0, 1, 2, and 3; sequence B controls 8 pins, namely pins 0, 1, 5, 6, 10, 11, 12, and 13. . Therefore, a serial-to-parallel conversion controller is needed to complete this conversion operation. The serial-to-parallel conversion controller is used to complete bit-width conversion. It is determined by the central controller, reads data from the memory, and then transmits it to the specified pins in sequence. At the same time, the serial-to-parallel conversion controller is bidirectional, reading data from the pin currently set as input and writing it to the specified location in the memory.

Example 2

As shown in Figure 2, a timing input and output control method uses the method of exchanging data between chip pins and RAM. Under the control of the controller, when set to output, the data is read from the RAM and output to the chip pins. ; When set as input, data is read from the chip pin and written to RAM. There are two RAMs in Figure 2. One RAM (data RAM) stores input and output sequence data. When output, the data in RAM is written to the chip pin. When input is read the data from the chip pins is written to RAM. Another RAM (direction control RAM) stores the input and output direction selection control sequence of the sequence. Under the control of the controller, as the sequence occurs, the input in the RAM is sequentially read and written into the input and output direction selection register of the chip pin, which controls the input and output direction of the chip. It also controls whether the data RAM is currently reading or writing according to the direction. ;

Store one or more sequences in RAM, when only one sequence is running or no sequence is running at the same time; each sequence corresponds to a sequence control register group, with at least 4 registers set in the group, using the baud rate The register controls the speed of this sequence;

The first address register of the sequence stores the starting address of this sequence stored in RAM, and the tail address register stores the end address of this sequence stored in RAM; the control register specifies the attributes of this sequence.

Common attributes are:

1. Directional flexibility control. The direction of this sequence can be controlled using a dedicated RAM storage as described above. This provides high flexibility and can switch the direction at any time as the sequence occurs. However, this attribute can also be used to indicate that this sequence is only input, or only output, or supports both input and output. If input or output only is specified, the direction control RAM will not be read while this sequence occurs.

2. Serial to parallel conversion settings. What is described above is a setup without serial-to-parallel conversion. One RAM read or write can be 1 byte (8 bits), 2 bytes (16 bits) or 4 bytes (32 bits), etc. (This article uses 1 byte as an example. ), each bit corresponds to 1 pin of the chip. But there is also a setting with serial-to-parallel conversion, that is, the data of a RAM corresponds to a pin. When writing to a pin, the data read by the RAM needs to be converted from parallel to serial into a bit stream each time. , sent to one pin of the chip in turn; when the pin is to be read, the data on the pin is converted from serial to parallel data, and then written into RAM. When serial-to-parallel conversion is required, as shown in Figure 3, if the direction control of the sequence is provided by RAM, then the data read out from the direction control RAM must also be converted from parallel to serial. If it is provided by the control register of this sequence, it is not needed.

3. Sequence start condition control. A controller can have several sets of sequence control register sets to support multiple sequence occurrences. The starting conditions for each sequence include:

(1) When the designated chip pin has a rising edge;

(2) When the specified chip pin has a falling edge;

(3) When the designated chip pin has a rising edge or falling edge;

(4) When the specified chip pin is equal to 0;

(5) When the specified chip pin is equal to 1;

(6) When the input and output timing processor receives other CPU commands to start;

(7) When a sequence of other specified input and output timing processors (one chip can have multiple input and output timing processors) starts, it starts at the same time;

(8) Start when a specified sequence ends;

4. Big and small endian control. Indicates whether to send the high-order bit or low-order bit of the byte first during serial transmission.

The above-described embodiments only represent implementations of the present invention, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

Claims (3)

1. A general purpose input output sequential processor, characterized by: the system consists of a bus interface bridge, a processor register file, a time sequence control state machine, a time sequence generation counter, a time sequence RAM memory and a serial-parallel conversion controller, wherein the processor register file comprises a plurality of sequence control register groups, and the system comprises the following components:

the bus interface bridge is respectively connected with the processor register file and the time sequence RAM memory, receives various commands of the CPU from the bus and transmits the commands to each register, thereby playing a role in converting a command format;

the processor register file is connected with the time sequence control state machine and is used for temporarily storing processing data of the processor;

the time sequence control state machine is connected with the time sequence generation counter and consists of an instruction fetching controller, a decoder and an executor, wherein the instruction fetching controller is used for reading control codes, the decoder is used for analyzing the codes and translating the codes into codes which are convenient for the executor to execute control, and the executor is used for executing control in cooperation with the counter;

the time sequence generation counter is connected with a time sequence RAM;

the sequential RAM memory is connected with the serial-parallel conversion controller group, the sequential RAM memory stores control codes of each sequence, and is convenient for reading of the sequential state machine and the serial-parallel conversion controller, and the serial-parallel conversion controller is used for completing bit width conversion, reading data from the sequential RAM memory and then sequentially transmitting the data to a designated pin.

2. The universal input output sequential processor of claim 1, wherein: and each sequence control register group corresponds to 1 sequence control in the sequence control register group.

3. The universal input output sequential processor of claim 1, wherein: the serial-parallel controller is bi-directional and can read data from the pins currently set as inputs and write to designated locations of the memory.