CN107014489B - Light multi-parameter sensing CMOS monolithic integrated circuit - Google Patents

Abstract

An optical multi-parameter sensing CMOS monolithic integrated circuit is composed of a BDJ photoelectric sensing selection unit, a current-voltage linear conversion circuit, a correlated secondary sampling circuit, a differential amplifier output circuit, and a mode timing control circuit. The optical multi-parameter sensing integrated circuit proposed by the present invention is monolithically integrated with a buried CMOS double PN junction photodiode, and can realize real-time monitoring of optical wavelength and light intensity parameters, and has the advantages of small error, high precision, wide detection range, small circuit size, low power consumption, etc., and can be widely used in occasions of optical multi-parameter monitoring.

Description

A CMOS monolithic integrated circuit for optical multi-parameter sensing

technical field

The invention relates to an optical multi-parameter sensing CMOS monolithic integrated circuit.

Background technique

Buried CMOS dual PN junction photodiodes, consisting of two vertically stacked diodes of different depths. The stacked structure of this device makes the transmission depth of light in the silicon crystal strongly dependent on the wavelength when the silicon material is used as a filter. When the incident light power and wavelength are different, the photocurrent measured by the PN junction is also different. same. The photocurrent ratio of the two PN junctions has a good monotonically increasing relationship with the wavelength, which can be used to measure the wavelength of monochromatic light, and the output current is proportional to the incident light power, which can be used to measure the light intensity.

At present, the application of discrete photodiode components has matured, and its related signal processing circuits are often built using discrete components. The disadvantages are complex circuits, large volume, single optical parameters to be detected, and low precision; , can realize the conversion from the parallel structure to the series structure, and provide the possibility to realize multi-parameter detection; the optical multi-parameter sensing circuit based on microelectronics technology can greatly reduce the circuit volume while improving the detection accuracy of weak signals, making the light multi-parameter The miniaturization of the parameter sensing system becomes possible.

Contents of the invention

The present invention overcomes the above-mentioned shortcomings of the prior art and provides an optical multi-parameter sensing CMOS monolithic integrated circuit.

The present invention combines optical multi-parameter sensing technology with microelectronics technology, and designs an optical multi-parameter sensing CMOS monolithic integrated circuit. The circuit uses CMOS technology to bury the double PN junction photodiode sensing unit and signal processing circuit. Monolithic integration, through mode switching, can detect light intensity and light wavelength at the same time, realizing the miniaturization and automation of the optical multi-parameter detection system. The buried CMOS photodiode realizes the conversion of optical signal to electrical signal, and each circuit module integrated with the buried CMOS photodiode converts the weak current responded by the photodiode into an easy-to-measure voltage signal output.

An optical multi-parameter sensing CMOS monolithic integrated circuit of the present invention consists of a BDJ photoelectric sensing selection unit 1, a current and voltage linear conversion circuit 2, a related secondary sampling circuit 3, a differential amplification output circuit 4, and a mode timing control circuit 5 , A total of 5 circuit modules.

In the BDJ photoelectric sensor selection unit 1, the first input terminal 11a and the second input terminal 12a are respectively connected to the first output terminal 51b and the second output terminal 52b of the mode timing control circuit 5, and the output terminal 1b is linear to the current and voltage The second input terminal 22a of the conversion circuit 2 is connected;

BDJ photoelectric sensing selection unit 1 is composed of shallow PN junction photodiode D1, deep PN junction photodiode D2, NMOS transistor N1 and PMOS transistor P1; the shallow PN junction photodiode D1 is connected to the deep PN junction photodiode D2 with a common cathode , and as the output terminal 1b of the BDJ photoelectric sensing selection unit 1, the anode of the deep PN junction photodiode D2 is grounded, the drain of the NMOS transistor N1 is connected to the anode of the shallow PN junction photodiode D1, and the source is grounded, so The source of the PMOS transistor P1 is connected to the anode of the shallow PN junction photodiode D1, and the drain is grounded. The gate of the NMOS transistor N1 and the gate of the PMOS transistor P1 are respectively the first input of the BDJ photoelectric sensor selection unit 1. terminal 11a and a second input terminal 12a;

In the current-voltage linear conversion circuit 2, the first input terminal 21a is connected to the third output terminal 53b of the mode timing control circuit 5, the second input terminal 22a is connected to the output terminal 1b of the BDJ photoelectric sensor selection unit 1, and the output terminal 2b is connected to The first input terminal 31a and the second input terminal 32a of the correlation subsampling circuit 3;

The current-voltage linear conversion circuit 2 is composed of NMOS transistors N2, N3, N4, N5, N6, PMOS transistors P2, P3, P4, P5 and capacitor C1; the source of the PMOS transistor P2 is connected to the power supply VDD, and the gate is connected to the PMOS transistor The gate of the transistor P3, the drain is connected to the source of the PMOS transistor P4, the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P5, the drain is connected to the drain of the NMOS transistor N3, and is used as the current-voltage linear The output terminal 2b of the conversion circuit 2, the gate of the NMOS transistor N3 is connected to the gate of the NMOS transistor N4, the source is connected to the drain of the NMOS transistor N5, the source of the NMOS transistor N5 is grounded, and the gate is used as the current voltage The second input terminal 22a of the linear conversion circuit (2), the source of the PMOS transistor P3 is connected to the power supply VDD, the gate-drain is short-circuited, the drain is connected to the source of the PMOS transistor P5, and the gate-drain of the PMOS transistor P5 is short-circuited, The drain is connected to the drain of the NMOS transistor N4, the gate-drain of the NMOS transistor N4 is short-circuited, the source is connected to the drain of the NMOS transistor N6, the gate-drain of the NMOS transistor N6 is short-circuited, the source is grounded, and the NMOS transistor N4 The drain of N2 and one end of the capacitor C1 are connected to the output end 2b of the current-voltage linear conversion circuit 2, and the drain of the NMOS transistor N2 and the other end of the capacitor C1 are connected to the input end 22a of the current-voltage linear conversion circuit 2, so The gate of the NMOS transistor N2 is used as the first input terminal 21a of the current-voltage linear conversion circuit 2;

In the correlated secondary sampling circuit 3, the first input terminal 31a and the second input terminal 32a are connected to the output terminal 2b of the current-voltage linear conversion circuit 2, and the third input terminal 33a is connected to the third output terminal of the mode timing control circuit 5 53b is connected, and the first output terminal 31b and the second output terminal 32b are respectively connected to the first input terminal 41a and the second input terminal 42a of the differential amplifier output circuit 4;

The relevant secondary sampling circuit 3 is composed of PMOS transistors P6, P7, P8, NMOS transistors N7, N8, N9 and capacitors C2, C3; the source of the PMOS transistor P6 is connected to the power supply VDD, and the gate is connected to the gate of the NMOS transistor N7. Connected, and the port is taken out as the third input terminal 33a of the correlation secondary sampling circuit 3, the source of the NMOS transistor N7 is grounded, the drain is connected to the drain of the PMOS transistor P6, and is connected to the gate of the PMOS transistor P7 and The gate of the NMOS transistor N9 is connected, the source of the PMOS transistor P7 is connected to the drain of the NMOS transistor N8, and the port is drawn out as the first input terminal 31a of the relevant secondary sampling circuit 3, and the drain of the PMOS transistor P7 is Connect the source of the NMOS transistor N8, and lead out the port as the first output end 31b of the relevant secondary sampling circuit 3, the NMOS transistor N8 and the gate of the PMOS transistor P8 are connected to each other, and are connected to the relevant two The third input terminal 33a of the sub-sampling circuit 3, the source of the PMOS transistor P8 is connected to the drain of the NMOS transistor N9, and the port is drawn out as the second input terminal 32a of the relevant sub-sampling circuit 3, the PMOS transistor The P8 drain is connected to the source of the NMOS transistor N9, and the port is drawn out as the second output terminal 32b of the relevant secondary sampling circuit 3, and one end of the capacitor C2, C3 is respectively connected to the first terminal of the relevant secondary sampling circuit 3. The output terminal 31b and the second output terminal 32b, the other terminals of the capacitors C2 and C3 are both grounded;

In the differential amplification output circuit 4, the first input terminal 41a and the second input terminal 42a are respectively connected to the first output terminal 31b and the second output terminal 32b of the relevant secondary sampling circuit 3, and the output terminal OUTPUT is the differential amplification output circuit 4 The output terminal is also the output terminal of the optical multi-parameter sensing integrated circuit of the present invention;

The differential amplification output circuit 4 is composed of NMOS transistors N10, N11, N12, N13, N14, N15, N16 and PMOS transistors P9, P10, P11, P12, P13, P14, P15; the source of the PMOS transistor P9 is connected to the power supply VDD, The gate is connected to the gate of the PMOS transistor P12, the source of the PMOS transistor P10 is connected to the source of the PMOS transistor P11 and connected to the drain of the PMOS transistor P9, and the gate of the PMOS transistor P10 is connected to the NMOS transistor N10 Gate, the gate of the PMOS transistor P11 is connected to the gate of the NMOS transistor N11, the gate of the NMOS transistor N10 is used as the first input terminal 41a of the differential amplifier output circuit 4, and the source is connected to the source of the NMOS transistor N11 And connected to the drain of the NMOS transistor N12, the gate of the NMOS transistor N11 is used as the second input terminal 42a of the differential amplifier output circuit 4, the source of the NMOS transistor N12 is grounded, and the gate is connected to the gate of the NMOS transistor N15 The source of the PMOS transistor P12 is connected to the power supply VDD, the gate and the drain are short-circuited, the gate is connected to the gate of the PMOS transistor P13, the drain is connected to the source of the PMOS transistor P14, and the lead port is connected to the drain of the NMOS transistor N10 The gate of the PMOS transistor P14 is connected to the gate of the PMOS transistor P15, the gate and drain are short-circuited, the drain is connected to the drain of the NMOS transistor N13, the gate and drain of the NMOS transistor N13 are short-circuited, and the gate is connected to the NMOS transistor N13. The gate of the tube N14, the source is connected to the drain of the NMOS tube N15, and the lead port is connected to the drain of the PMOS tube P10, the gate of the NMOS tube N15 is short-circuited, the gate is connected to the gate of the NMOS tube N16, and the source The pole is grounded, the source of the PMOS transistor P13 is connected to the power supply VDD, the drain is connected to the source of the PMOS transistor P15, and the lead port is connected to the drain of the NMOS transistor N11, and the drain of the PMOS transistor P15 is connected to the NMOS transistor N14 The drain, and the lead-out port is used as the output terminal OUTPUT of the whole circuit, the source of the NMOS transistor N14 is connected to the drain of the NMOS transistor N16, and the lead-out port is connected to the drain of the PMOS transistor P11, and the source of the NMOS transistor N16 is grounded ;

The first input terminal Sel of the mode timing control circuit 5 is a test mode selection port, the second input terminal CLK inputs a clock signal, and the first output terminal 51b and the second output terminal 52b are connected to the first port of the BDJ photoelectric sensor selection unit 1. The input terminal 11a, the second input terminal 12a, and the third output terminal 53b are connected to the first input terminal 21a of the current-voltage linear conversion circuit 2 and the third input terminal 33a of the relevant secondary sampling circuit 3;

The mode timing control circuit 5 consists of PMOS transistors P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27 and NMOS transistors N17, N18, N19, N20, N21, N22, N23, N24, Composed of N25, N26, N27, N28 and capacitors C4, C5, C6, C7; the source of the PMOS transistor P16 is connected to the power supply VDD, the gate is connected to the gate of the NMOS transistor N17, and connected to the first input terminal Sel and used as The second output terminal 52b of the mode timing control circuit 5, the drain of the PMOS transistor P16 is connected to the drain of the NMOS transistor N17, and the port is taken as the first output terminal 51b of the mode timing control circuit 5, the NMOS The source of the tube N17 is grounded, the source of the PMOS tube P17 is connected to the power supply VDD, the gate is connected to the gate of the NMOS tube N18, and the lead port is connected to the second input terminal CLK, and the drain of the PMOS tube P17 is connected to the NMOS tube The drain of N18 is connected to the gate of the PMOS transistor P21 and the gate of the NMOS transistor N19, the source of the NMOS transistor N18 is grounded, the source of the PMOS transistor P18 is connected to the power supply VDD, and the gate is connected to the NMOS transistor. The gate of the transistor N20 is connected to the drain of the PMOS transistor P22 and the drain of the NMOS transistor N23, the drain of the PMOS transistor P18 is connected to the source of the PMOS transistor P19, and the gate of the PMOS transistor P19 is connected to the second The input terminal CLK, the drain is connected to the drain of the NMOS transistor N19, and the lead port is connected to one end of the capacitor C4, the gate of the PMOS transistor P20 and the gate of the NMOS transistor N22, and the source of the NMOS transistor N19 is connected to the The drain of the NMOS transistor N20, the source of the NMOS transistor N20 is grounded, the other end of the capacitor C4 is grounded, the source of the PMOS transistor P20 is connected to the power supply VDD, the gate is connected to the gate of the NMOS transistor N22, and the drain is connected to the The source of the PMOS transistor P21, the drain of the PMOS transistor P21 is connected to the drain of the NMOS transistor N21, and connected to one end of the capacitor C5, the gate of the PMOS transistor P22 and the gate of the NMOS transistor N23, the The gate of the NMOS transistor N21 is connected to the second input terminal CLK, the source is connected to the drain of the NMOS transistor N22, the source of the NMOS transistor N22 is grounded, the other end of the capacitor C5 is grounded, and the source of the PMOS transistor P22 is connected to the power supply VDD , the gate is connected to the gate of the NMOS transistor N23, and is connected to the gate of the PMOS transistor P24 and the gate of the NMOS transistor N26, and the drain of the PMOS transistor P22 is connected to the drain of the NMOS transistor N23, and connected to the gate of the NMOS transistor N23. The gate of the PMOS transistor P26 and the gate of the NMOS transistor N24, the source of the NMOS transistor N23 are grounded, the source of the PMOS transistor P23 is connected to the power supply VDD, the gate is connected to the gate of the NMOS transistor N25, and connected to the The drain of the PMOS transistor P27 and the drain of the NMOS transistor N28, The drain of the PMOS transistor P23 is connected to the source of the PMOS transistor P24, the drain of the PMOS transistor P24 is connected to the drain of the NMOS transistor N24, and connected to one end of the capacitor C6 and the gate of the PMOS transistor P25 and the The gate of the NMOS transistor N27, the source of the NMOS transistor N24 is connected to the drain of the NMOS transistor N25, the source of the NMOS transistor N25 is grounded, the other end of the capacitor C6 is grounded, and the source of the PMOS transistor P25 is connected to the power supply VDD , the gate is connected to the gate of the NMOS transistor N27, the drain is connected to the source of the PMOS transistor P26, the drain of the PMOS transistor P26 is connected to the drain of the NMOS transistor N26, and the lead port is connected to one end of the capacitor C7 and The grid of the PMOS transistor P27 and the grid of the NMOS transistor N28 are used as the third output terminal 53b of the mode timing control circuit (5) at the same time, and the source of the NMOS transistor N26 is connected to the drain of the NMOS transistor N27 , the source of the NMOS transistor N27 is grounded, the other end of the capacitor C7 is grounded, the source of the PMOS transistor P27 is connected to the power supply VDD, the gate and the drain are respectively connected to the gate and drain of the NMOS transistor N28, and the NMOS The source of tube N28 is grounded.

The advantages of the present invention are: the optical multi-parameter sensing integrated circuit proposed by the present invention is monolithically integrated with buried CMOS double PN junction photodiodes, which can realize real-time monitoring of optical wavelength and light intensity parameters, with small errors, high precision, and wide detection range Wide, small circuit size, low power consumption and other advantages, it can be widely used in the occasion of optical multi-parameter monitoring.

Description of drawings

Fig. 1 is the unit block diagram of structure of the present invention

Fig. 2 is the schematic diagram of the design of the present invention

Fig. 3 is a partially enlarged view of part S1 in Fig. 2

Fig. 4 is a partial enlarged view of part S2 in Fig. 2

Fig. 5 is a partial enlarged view of part S3 in Fig. 2

Detailed ways

Further illustrate the present invention below in conjunction with accompanying drawing.

An optical multi-parameter sensing CMOS single-chip integrated circuit of the present invention includes a BDJ photoelectric sensing selection unit 1, a current-voltage linear conversion circuit 2, a related secondary sampling circuit 3, a differential amplification output circuit 4, and a mode timing control circuit 5 A total of 5 circuit modules.

The BDJ photoelectric sensing selection unit (1) converts the optical signal into an electrical signal by using the photodiode photoelectric effect, and the BDJ working mode can be selected through the control signal to realize the mutual conversion of the photodiode series and parallel structures; the photodiode D1 and D2 is used to convert the optical signal into an electrical signal, the light intensity has a strong dependence on the output current, and the light wavelength has a linear relationship with the current ratio of D1 and D2. The NMOS transistor N1 and the PMOS transistor P1 constitute a transmission gate. When the input terminal When 11a and 12a are at high and low levels respectively, the transmission gate is turned on, and the photodiodes D1 and D2 work simultaneously, and the output current of the output terminal 1b of the BDJ photoelectric sensor selection unit 1 is the sum of the currents of D1 and D2. When the input When the terminals 11a and 12a are at low and high levels respectively, the transmission gate is cut off, and only the photodiode D2 works, and the output terminal 1b of the BDJ photoelectric sensor selection unit 1 only outputs the photocurrent on D2;

The current-voltage linear conversion circuit 2 has high sensitivity and strong anti-interference ability, and converts the current signal into a voltage signal by reading the weak current at the second input terminal 22a; when the first input terminal 21a inputs a high level, the The NMOS transistor N2 is turned on, and the circuit is in a reset state. When the first input terminal 21a inputs a low level, the NMOS transistor N2 is turned off, and the circuit is integrated and converted into a voltage output by the capacitor C1, wherein the PMOS transistors P2 and P4 The cascode amplifier circuit composed of the NMOS transistors N3 and N5 is used as an operational amplifier in the current-voltage linear conversion circuit 5, and the PMOS transistors P3 and P5 and the NMOS transistors N4 and N6 are cascode amplifier circuits Bias is provided, and the current-voltage linear conversion circuit 5 provides a very low reverse bias voltage for the photodiode through the operational amplifier feedback loop to reduce the dark current, and at the same time, the voltage on the parasitic capacitance of the photodiode remains constant during the integration phase, ensuring The integral voltage output at the output terminal 2b has better linearity;

The correlation sub-sampling circuit 3 is used to eliminate the fixed pattern noise of the circuit; the NMOS transistor N8 and the PMOS transistor P7 constitute the first transmission gate, the NMOS transistor N9 and the PMOS transistor P8 constitute the second transmission gate, when the third When the input signal at the input terminal 33a is at a high level, the first transmission gate is turned on, the second transmission gate is turned off, the output signal of the current-voltage linear conversion circuit 2 is input from the first input terminal 31a, and charges the capacitor C2, and the The voltage across the capacitor C2 is the reference mode voltage. When the input signal at the third input terminal 33a is at a low level, the first transmission gate is turned off, the second transmission gate is turned on, and the output signal of the current-voltage linear conversion circuit 2 is transmitted from the second input terminal 32a input, and charge the capacitor C3, the voltage across the capacitor C3 is the photoelectric sensing voltage;

The differential amplification output circuit 4 is used to make a difference between the voltage signals of the two output terminals of the relevant secondary sampling circuit 3, and finally output the photoelectric sensing voltage with the fixed pattern noise removed; the differential amplification output circuit 4 adopts a rail-to-rail structure, When the input voltages of the input terminals 41a and 42a vary from 0 to the power supply voltage, they can make a difference, and the final signal is output from the output terminal OUTPUT port;

The mode timing control circuit 5 provides two input terminals 11a and 12a of the BDJ photoelectric sensor selection unit 1, the first input terminal 21a of the current-voltage linear conversion circuit 2, and the third input terminal 33a of the relevant secondary sampling circuit 3 respectively. Control signal; the inverter composed of the PMOS transistor P16 and the NMOS transistor N17 inverts the input signal of the first input terminal Sel to provide a voltage to the first output port 51b, and the output voltage of the second output terminal 52b Provided directly by the first input terminal Sel, the NMOS transistors N19, N20, N21, N22, the PMOS transistors P18, P19, P20, P21 and the capacitors C4, C5 together form a first clock control CMOS register, the The PMOS transistor P17 and the NMOS transistor N18 form an inverter, which inverts the input clock signal together with the original clock signal to provide a signal for the first clock control CMOS register, and the inverter formed by the PMOS transistor P22 and the NMOS transistor N23 The phaser is used to invert the voltage output by the first clock-controlled CMOS register at the capacitor C5, and feed it back to the gate of the PMOS transistor P18 and the gate of the NMOS transistor N20 in the first clock-controlled CMOS register and subsequent circuits, the PMOS transistor The inverter where P17 is located, the inverter where the PMOS transistor P22 is located, and the first clock control CMOS register together form the first T' flip-flop, the PMOS transistors P23, P24, P25, P26 and the NMOS transistors N24, N25 , N26, N27, and capacitors C6 and C7 together constitute the second clock-controlled CMOS register, and the in-phase clock signal and inverse-phase clock signal of the register are respectively the output voltage signal at the capacitor C5 of the first clock-controlled CMOS register and the voltage via the PMOS transistor P22 The output voltage signal after the inversion of the inverter, the inverter composed of the PMOS transistor P27 and the NMOS transistor N28 is used to invert the voltage output by the second clock control CMOS register at the capacitor C7, and feed it back to the first The gate of the PMOS transistor P23 and the gate of the NMOS transistor N25 in the second clock control CMOS register, the inverter where the PMOS transistor P27 is located and the first clock control CMOS register together constitute the second T' flip-flop, the first and second T' The flip-flops together form a four-frequency divider, and the frequency-divided signal is output from the capacitor C7, and this output terminal is used as the third output terminal 53b of the timing control circuit 5 of this mode.

The content described in the embodiments of this specification is only an enumeration of the implementation forms of the inventive concept. The protection scope of the present invention should not be regarded as limited to the specific forms stated in the embodiments. The protection scope of the present invention also reaches those skilled in the art. Equivalent technical means conceivable according to the concept of the present invention.

Claims (1)

1. A kind of optical multi-parameter sensing CMOS monolithic integrated circuit, by BDJ photoelectric sensing selection unit (1), current voltage linear conversion circuit (2), relevant secondary sampling circuit (3), differential amplification output circuit (4 ), mode sequence control circuit (5); In the BDJ photoelectric sensor selection unit (1), the first input terminal 11a and the second input terminal 12a are respectively connected to the first output terminal 51b and the second output terminal 52b of the mode timing control circuit (5), and the output terminal 1b Connected to the second input terminal 22a of the current-voltage linear conversion circuit (2); The BDJ photoelectric sensing selection unit (1) is composed of a shallow PN junction photodiode D1, a deep PN junction photodiode D2, an NMOS transistor N1 and a PMOS transistor P1; the shallow PN junction photodiode D1 and the deep PN junction photodiode D2 share The cathode is connected, and as the output terminal 1b of the BDJ photoelectric sensing selection unit (1), the anode of the deep PN junction photodiode D2 is grounded, the drain of the NMOS transistor N1 is connected to the anode of the shallow PN junction photodiode D1, and the source The source of the PMOS transistor P1 is connected to the anode of the shallow PN junction photodiode D1, and the drain is grounded. The gate of the NMOS transistor N1 and the gate of the PMOS transistor P1 are respectively the BDJ photoelectric sensor selection unit ( 1) the first input terminal 11a and the second input terminal 12a; In the current-voltage linear conversion circuit (2), the first input terminal 21a is connected to the third output terminal 53b of the mode timing control circuit (5), and the second input terminal 22a is connected to the output terminal of the BDJ photoelectric sensor selection unit (1) 1b, the output terminal 2b is connected to the first input terminal 31a and the second input terminal 32a of the relevant secondary sampling circuit (3); The current-voltage linear conversion circuit (2) is composed of NMOS transistors N2, N3, N4, N5, N6, PMOS transistors P2, P3, P4, P5 and capacitor C1; the source of the PMOS transistor P2 is connected to the power supply VDD, and the gate is connected to the The gate of the PMOS transistor P3, the drain is connected to the source of the PMOS transistor P4, the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P5, and the drain is connected to the drain of the NMOS transistor N3, and used as the current The output terminal 2b of the voltage linear conversion circuit (2), the gate of the NMOS transistor N3 is connected to the gate of the NMOS transistor N4, the source is connected to the drain of the NMOS transistor N5, the source of the NMOS transistor N5 is grounded, and the gate As the second input terminal 22a of the current-voltage linear conversion circuit (2), the source of the PMOS transistor P3 is connected to the power supply VDD, the gate and drain are short-circuited, the drain is connected to the source of the PMOS transistor P5, and the gate of the PMOS transistor P5 is The drain is short-circuited, the drain is connected to the drain of the NMOS transistor N4, the gate-drain of the NMOS transistor N4 is short-circuited, the source is connected to the drain of the NMOS transistor N6, the gate-drain of the NMOS transistor N6 is short-circuited, and the source is grounded, The drain of the NMOS transistor N2 and one end of the capacitor C1 are connected to the output terminal 2b of the current-voltage linear conversion circuit (2), and the drain of the NMOS transistor N2 and the other end of the capacitor C1 are connected to the current-voltage linear conversion circuit ( 2) the input terminal 22a, the gate of the NMOS transistor N2 is used as the first input terminal 21a of the current-voltage linear conversion circuit (2); In the correlation secondary sampling circuit (3), the first input terminal 31a and the second input terminal 32a are connected to the output terminal 2b of the current-voltage linear conversion circuit (2), and the third input terminal 33a is connected to the mode timing control circuit (5 ) is connected to the third output terminal 53b, and the first output terminal 31b and the second output terminal 32b are respectively connected to the first input terminal 41a and the second input terminal 42a of the differential amplifier output circuit (4); Relevant secondary sampling circuit (3) is made up of PMOS transistor P6, P7, P8 and NMOS transistor N7, N8, N9 and electric capacity C2, C3; Described PMOS transistor P6 source connects power supply VDD, gate and described NMOS transistor N7 The gate is connected, and the port is drawn out as the third input terminal 33a of the relevant secondary sampling circuit (3), the source of the NMOS transistor N7 is grounded, the drain is connected to the drain of the PMOS transistor P6, and is connected with the PMOS transistor P6 drain. The gate of P7 is connected to the gate of the NMOS transistor N9, the source of the PMOS transistor P7 is connected to the drain of the NMOS transistor N8, and the port is drawn out as the first input terminal 31a of the relevant secondary sampling circuit (3), so The drain of the PMOS transistor P7 is connected to the source of the NMOS transistor N8, and the port is drawn out as the first output end 31b of the relevant secondary sampling circuit (3), and the NMOS transistor N8 is connected to the grid of the PMOS transistor P8 , and are commonly connected to the third input terminal 33a of the correlation re-sampling circuit (3), the source of the PMOS transistor P8 is connected to the drain of the NMOS transistor N9, and the port is drawn as the correlation re-sampling circuit (3) ) of the second input terminal 32a, the drain of the PMOS transistor P8 is connected to the source of the NMOS transistor N9, and the port is drawn out as the second output terminal 32b of the relevant secondary sampling circuit (3), and the capacitor C2 One end is connected to the first output end 31b of the relevant secondary sampling circuit (3), one end of the capacitor C3 is connected to the second output end 32b of the relevant secondary sampling circuit (3), and the other ends of the capacitors C2 and C3 are both grounding; In the described differential amplification output circuit (4), the first input terminal 41a and the second input terminal 42a are respectively connected to the first output terminal 31b and the second output terminal 32b of the relevant secondary sampling circuit (3), and the output terminal OUTPUT is the differential The output terminal of the amplified output circuit (4) is also the output terminal of the optical multi-parameter sensing integrated circuit of the present invention; The differential amplifier output circuit (4) is composed of NMOS tubes N10, N11, N12, N13, N14, N15, N16 and PMOS tubes P9, P10, P11, P12, P13, P14, P15; the source of the PMOS tube P9 is connected to the power supply VDD, the gate is connected to the gate of the PMOS transistor P12, the source of the PMOS transistor P10 is connected to the source of the PMOS transistor P11 and connected to the drain of the PMOS transistor P9, and the gate of the PMOS transistor P10 is connected to the NMOS The gate of the transistor N10, the gate of the PMOS transistor P11 is connected to the gate of the NMOS transistor N11, the gate of the NMOS transistor N10 is used as the first input terminal 41a of the differential amplifier output circuit (4), and the source is connected to the NMOS The source of the NMOS transistor N11 is connected to the drain of the NMOS transistor N12, the gate of the NMOS transistor N11 is used as the second input terminal 42a of the differential amplifier output circuit (4), the source of the NMOS transistor N12 is grounded, and the gate is connected to the The gate of the NMOS transistor N15, the source of the PMOS transistor P12 is connected to the power supply VDD, the gate and the drain are short-circuited, the gate is connected to the gate of the PMOS transistor P13, the drain is connected to the source of the PMOS transistor P14, and the lead port is connected to The drain of the NMOS transistor N10, the gate of the PMOS transistor P14 is connected to the gate of the PMOS transistor P15, the gate-drain is short-circuited, the drain is connected to the drain of the NMOS transistor N13, and the gate-drain of the NMOS transistor N13 is short-circuited, The gate is connected to the gate of the NMOS transistor N14, the source is connected to the drain of the NMOS transistor N15, and the lead port is connected to the drain of the PMOS transistor P10, the gate and drain of the NMOS transistor N15 are short-circuited, and the gate is connected to the NMOS transistor N15. The gate of the tube N16, the source is grounded, the source of the PMOS tube P13 is connected to the power supply VDD, the drain is connected to the source of the PMOS tube P15, and the lead port is connected to the drain of the NMOS tube N11, and the drain of the PMOS tube P15 Connect the drain of the NMOS transistor N14, and lead out the port as the output terminal OUTPUT of the whole circuit, the source of the NMOS transistor N14 is connected to the drain of the NMOS transistor N16, and the port is connected to the drain of the PMOS transistor P11, the The source of NMOS transistor N16 is grounded; The first input terminal Sel of the mode timing control circuit (5) is a test mode selection port, the second input terminal CLK inputs a clock signal, and the first output terminal 51b and the second output terminal 52b are connected to the BDJ photoelectric sensor selection unit (1 ) of the first input terminal 11a, the second input terminal 12a, the third output terminal 53b is connected to the first input terminal 21a of the current-voltage linear conversion circuit (2) and the third input terminal 33a of the relevant secondary sampling circuit (3); The mode timing control circuit (5) is composed of PMOS transistors P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27 and NMOS transistors N17, N18, N19, N20, N21, N22, N23, Composed of N24, N25, N26, N27, N28 and capacitors C4, C5, C6, C7; the source of the PMOS transistor P16 is connected to the power supply VDD, the gate is connected to the gate of the NMOS transistor N17, and connected to the first input terminal Sel And as the second output terminal 52b of the mode timing control circuit (5), the drain of the PMOS transistor P16 is connected to the drain of the NMOS transistor N17, and the port is taken as the first output of the mode timing control circuit (5) Terminal 51b, the source of the NMOS transistor N17 is grounded, the source of the PMOS transistor P17 is connected to the power supply VDD, the gate is connected to the gate of the NMOS transistor N18, and the lead port is connected to the second input terminal CLK, and the drain of the PMOS transistor P17 The pole is connected to the drain of the NMOS transistor N18, and the lead port is connected to the gate of the PMOS transistor P21 and the gate of the NMOS transistor N19, the source of the NMOS transistor N18 is grounded, and the source of the PMOS transistor P18 is connected to the power supply VDD, The gate is connected to the gate of the NMOS transistor N20, and is connected to the drain of the PMOS transistor P22 and the drain of the NMOS transistor N23, the drain of the PMOS transistor P18 is connected to the source of the PMOS transistor P19, and the drain of the PMOS transistor P19 is connected to the drain of the PMOS transistor P19. The gate of P19 is connected to the second input terminal CLK, the drain is connected to the drain of the NMOS transistor N19, and the lead port is connected to one end of the capacitor C4 and the gate of the PMOS transistor P20 and the gate of the NMOS transistor N22. The source of the tube N19 is connected to the drain of the NMOS tube N20, the source of the NMOS tube N20 is grounded, the other end of the capacitor C4 is grounded, the source of the PMOS tube P20 is connected to the power supply VDD, and the gate is connected to the gate of the NMOS tube N22 The drain is connected to the source of the PMOS transistor P21, the drain of the PMOS transistor P21 is connected to the drain of the NMOS transistor N21, and connected to one end of the capacitor C5 and the gate of the PMOS transistor P22 and the NMOS transistor N23 gate, the gate of the NMOS transistor N21 is connected to the second input terminal CLK, the source is connected to the drain of the NMOS transistor N22, the source of the NMOS transistor N22 is grounded, the other end of the capacitor C5 is grounded, and the PMOS transistor The source of P22 is connected to the power supply VDD, the gate is connected to the gate of the NMOS transistor N23, and is connected to the gate of the PMOS transistor P24 and the gate of the NMOS transistor N26, and the drain of the PMOS transistor P22 is connected to the gate of the NMOS transistor N23 The drain is connected to the gate of the PMOS transistor P26 and the gate of the NMOS transistor N24, the source of the NMOS transistor N23 is grounded, the source of the PMOS transistor P23 is connected to the power supply VDD, and the gate is connected to the gate of the NMOS transistor N25 pole, and connected to the drain of the PMOS transistor P27 and the NMOS The drain of the transistor N28, the drain of the PMOS transistor P23 is connected to the source of the PMOS transistor P24, the drain of the PMOS transistor P24 is connected to the drain of the NMOS transistor N24, and connected to one end of the capacitor C6 and the PMOS transistor The gate of P25 and the gate of the NMOS transistor N27, the source of the NMOS transistor N24 is connected to the drain of the NMOS transistor N25, the source of the NMOS transistor N25 is grounded, the other end of the capacitor C6 is grounded, and the PMOS transistor P25 The source is connected to the power supply VDD, the gate is connected to the gate of the NMOS transistor N27, the drain is connected to the source of the PMOS transistor P26, the drain of the PMOS transistor P26 is connected to the drain of the NMOS transistor N26, and the lead port is connected to the One end of the capacitor C7 and the gate of the PMOS transistor P27 and the gate of the NMOS transistor N28, this port is also used as the third output terminal 53b of the mode timing control circuit (5), and the source of the NMOS transistor N26 is connected to the The drain of the NMOS transistor N27, the source of the NMOS transistor N27 is grounded, the other end of the capacitor C7 is grounded, the source of the PMOS transistor P27 is connected to the power supply VDD, and the gate and drain are respectively connected to the gate and drain of the NMOS transistor N28. pole, and the source of the NMOS transistor N28 is grounded.