CN107093557B - Method for manufacturing thin film transistor and method for manufacturing array substrate - Google Patents
Method for manufacturing thin film transistor and method for manufacturing array substrate Download PDFInfo
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- CN107093557B CN107093557B CN201710281923.2A CN201710281923A CN107093557B CN 107093557 B CN107093557 B CN 107093557B CN 201710281923 A CN201710281923 A CN 201710281923A CN 107093557 B CN107093557 B CN 107093557B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
- H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
- H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
- H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
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Abstract
本发明公开了一种薄膜晶体管的制造方法及阵列基板的制造方法。薄膜晶体管的制造方法包括如下步骤：形成第一层有源层，包括相对设置的源极区和漏极区；形成第二层有源层，第二层有源层覆盖第一层有源层和第一层有源层所在表面中未被第一层有源层覆盖的位置；在第二层有源层表面形成遮盖层，遮盖层包括遮盖区，遮盖区位于源极区和漏极区之间，且遮盖区与源极区和漏极区之间具有间隔；对第二层有源层进行掺杂，在第二层有源层和第一层有源层重叠的位置形成高掺杂区，在第二层有源层和第一层有源层不重叠的位置且未被遮盖层覆盖的位置形成轻掺杂区，遮盖区与源极区和漏极区的间隔处形成轻掺杂漏区。本发明解决了现有的制造方法工艺复杂的技术问题。
The invention discloses a method for manufacturing a thin film transistor and a method for manufacturing an array substrate. The manufacturing method of the thin film transistor includes the following steps: forming a first layer of active layer, including source regions and drain regions arranged oppositely; forming a second layer of active layer, the second layer of active layer covering the first layer of active layer and the position of the surface where the first layer of active layer is not covered by the first layer of active layer; a cover layer is formed on the surface of the second layer of active layer, and the cover layer includes a cover region, and the cover region is located in the source region and the drain region There is a gap between the cover region and the source region and the drain region; the second active layer is doped to form a highly doped position where the second active layer and the first active layer overlap. Impurity region, a lightly doped region is formed at the position where the active layer of the second layer and the active layer of the first layer do not overlap and is not covered by the masking layer, and a lightly doped region is formed at the gap between the masking region and the source region and the drain region. Doping the drain region. The present invention solves the technical problem that the existing manufacturing method is complicated.
Description
Technical Field
The present invention relates to the field of manufacturing array substrates, and in particular, to a method for manufacturing a thin film transistor and a method for manufacturing an array substrate.
Background
As shown in fig. 1 and 2, a method for manufacturing a thin film transistor having a lightly doped drain structure includes: step 1: forming a first active layer including a source region 11 and a drain region 12; step 2: forming a second-layer active region, the second-layer active layer 20 covering the space between the source region 11 and the drain region 12; and step 3: forming a wide capping region 31 on the surface of the second-layer active region between the source region and the drain region, as shown in fig. 1; and 4, step 4: doping the source region and the drain region to form a heavily doped region; and 5: etching the wide capping region 31 to form a narrow capping region 32 with a space between the narrow capping region 32 and the source and drain regions 11 and 12, as shown in fig. 2; step 6: the second layer active region is doped at portions exposed from the space between the narrow cap region 32 and the source region 11 and the space between the narrow cap region 32 and the drain region 12 to form lightly doped regions, i.e., to form lightly doped drain regions. In the prior art, the doping process needs to be performed twice, and the position of the second doping needs to be covered during the first doping, so that the process is complex, and the process is not favorable for preparing the thin film transistor with the lightly doped drain structure.
Disclosure of Invention
The invention provides a manufacturing method of a thin film transistor and a manufacturing method of an array substrate.
In order to achieve the purpose, the invention provides the following technical scheme:
a method of manufacturing a thin film transistor, comprising the steps of:
forming a first active layer comprising oppositely disposed source and drain regions;
forming a second active layer covering the first active layer and a position of the surface of the first active layer where the first active layer is not covered by the first active layer;
forming a cover layer on the surface of the second active layer, wherein the cover layer comprises a cover region, the cover region is positioned between the source region and the drain region, and a gap is formed between the cover region and the source region and the drain region;
and doping the second layer of active layer, forming a high-doping region at the overlapping position of the second layer of active layer and the first layer of active layer, forming a light-doping region at the non-overlapping position of the second layer of active layer and the first layer of active layer and the position not covered by the covering layer, and forming a light-doping drain region at the interval between the covering region and the source region and the drain region.
As an optional mode, the thin film transistor is a top gate thin film transistor, and forming a capping layer on the surface of the second active layer specifically includes the following steps:
forming a gate insulating layer including a gate insulating region;
and forming a gate layer positioned on the gate insulating layer, wherein the gate layer comprises a gate region and the gate insulating region are arranged in a stacking mode, and the stacked gate insulating region and the gate region serve as the covering region.
As an alternative, before the step of forming the first active layer, the method further comprises the following steps:
forming a flexible glue layer on the first side plate surface of the glass substrate;
and forming a buffer layer on the surface of the flexible glue layer.
As an alternative, the thin film transistor is a bottom gate thin film transistor, and before the step of forming the first active layer, the method further includes the following steps:
forming a gate layer on the first side plate surface of the substrate, wherein the gate layer comprises a gate region;
forming a gate insulating layer covering the gate electrode layer, wherein the gate insulating layer comprises a gate insulating region and the gate insulating region covers the gate electrode region;
in the step of forming the first active layer, the source region and the drain region are positioned at two opposite sides of the gate region, and a space is respectively arranged between the gate region and the source region and between the gate region and the drain region;
the covering region is used for covering a gate region in the gate layer.
As an alternative, before the step of forming the gate layer on the first side plate surface of the substrate, the method further comprises the following steps:
forming a flexible glue layer on the first side plate surface of the glass substrate;
and forming a buffer layer on the surface of the flexible glue layer.
Alternatively, the cover region has the same width as the source region and the cover region and the drain region.
As an alternative, the first active layer is a polysilicon layer and the second active layer is a polysilicon layer.
As an optional mode, the thickness of the first active layer is any value between 100 and 150 nanometers, and the thickness of the second active layer is any value between 10 and 50 nanometers.
As an optional mode, the method further comprises the following steps:
forming a source electrode connected to the source region and a drain electrode connected to the drain region, respectively.
The invention also provides the following technical scheme:
a manufacturing method of an array substrate comprises the manufacturing method of any one of the thin film transistors.
The invention provides a manufacturing method of a thin film transistor, which comprises the following steps:
forming a first active layer, wherein the first active layer comprises a source region and a drain region which are oppositely arranged;
forming a second active layer, wherein the second active layer covers the first active layer and the position, not covered by the first active layer, of the surface of the first active layer; namely, the first layer active layer and the second layer active layer are overlapped at the positions of the source region and the drain region, and only the second layer active layer is arranged at the position outside the source region and the drain region;
forming a covering layer on the surface of the second active layer, wherein the covering layer comprises a covering region, the covering region is positioned between the source region and the drain region, and a gap is formed between the covering region and the source region and between the covering region and the drain region; the covering region covers the region between the source region and the drain region as a channel part, and the second active layer is exposed at the interval between the covering region and the source region and the interval between the covering region and the drain region; to this end, a source region and a drain region which are highly doped are required, and the heights of portions of the second active layer exposed at the space between the cover region and the source region which are lightly doped and the space between the cover region and the drain region are different;
the second layer of active layer is doped, and the doping process is sensitive to the height of the doped region, so that a high-doped region can be formed at the overlapped position of the second layer of active layer and the first layer of active layer only by carrying out the doping process once, a light-doped region is formed at the non-overlapped position of the second layer of active layer and the first layer of active layer and the position which is not covered by the covering layer, and a light-doped drain region is formed at the interval position of the covering region and the source region and the drain region; namely, the high-doped region and the light-doped region can be formed only by carrying out a doping process once, and the manufacturing steps of the manufacturing process of the thin film transistor are simplified. The manufacturing method of the array substrate comprises the manufacturing method of the thin film transistor, and manufacturing steps of the manufacturing process of the array substrate are simplified.
Drawings
Fig. 1 is a schematic structural diagram of a method for manufacturing a thin film transistor having a lightly doped drain structure in the background art after step 3 is performed;
fig. 2 is a schematic structural diagram of a method for manufacturing a thin film transistor having a lightly doped drain structure in the prior art after step 5 is performed;
FIG. 3 is a flow chart of a method of fabricating a thin film transistor of the present invention;
fig. 4 is a schematic structural view of the method for manufacturing a thin film transistor according to the embodiment of the present invention after the step of forming the first active layer is completed;
fig. 5 is a schematic structural view of the method of manufacturing a thin film transistor shown in fig. 4 after the step of forming the second active layer is completed;
FIG. 6 is a schematic structural diagram of the thin film transistor shown in FIG. 4 after the doping step is performed on the second active layer;
fig. 7 is a schematic structural view of a thin film transistor according to another embodiment of the present invention after the step of forming a first active layer is completed;
fig. 8 is a schematic structural view of the method of manufacturing a thin film transistor shown in fig. 7 after the step of forming the second active layer is completed;
fig. 9 is a schematic structural view of the thin film transistor shown in fig. 7 after the doping step is performed on the second active layer.
Description of the main element reference numerals:
background art:
11 source region, 12 drain region, 20 second layer active layer, 31 wide cap region, 32 narrow cap region;
in the invention:
110 source region, 120 drain region, 200 second active layer,
310 covers the area of the substrate to be covered,
the gate insulator region 411, the gate region 412,
500 flexible glue layers, 600 buffer layers.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 3 to 9, the method for manufacturing a thin film transistor of the present invention includes:
forming a first active layer including a source region 110 and a drain region 120 oppositely disposed;
forming a second active layer 200, the second active layer 200 covering the first active layer and a position of the surface of the first active layer not covered by the first active layer;
forming a cover layer on the surface of the second active layer, wherein the cover layer comprises a cover region 310, the cover region 310 is located between the source region 110 and the drain region 120, and a gap is formed between the cover region 310 and the source region 110 and the drain region 120;
the second active layer 200 is doped, a highly doped region is formed at a position where the second active layer 200 overlaps the first active layer, a lightly doped region is formed at a position where the second active layer 200 does not overlap the first active layer and is not covered by the capping layer, and a lightly doped drain region is formed at a position where the capping region 310 is spaced apart from the source region 110 and the drain region 120.
The manufacturing method of the thin film transistor comprises the following steps:
forming a first active layer, wherein the first active layer comprises a source region and a drain region which are oppositely arranged;
forming a second active layer, wherein the second active layer covers the first active layer and the position, not covered by the first active layer, of the surface of the first active layer; namely, the first layer active layer and the second layer active layer are overlapped at the positions of the source region and the drain region, and only the second layer active layer is arranged at the position outside the source region and the drain region;
forming a covering layer on the surface of the second active layer, wherein the covering layer comprises a covering region, the covering region is positioned between the source region and the drain region, and a gap is formed between the covering region and the source region and between the covering region and the drain region; the covering region covers the region between the source region and the drain region as a channel part, and the second active layer is exposed at the interval between the covering region and the source region and the interval between the covering region and the drain region; to this end, a source region and a drain region which are highly doped are required, and the heights of portions of the second active layer exposed at the space between the cover region and the source region which are lightly doped and the space between the cover region and the drain region are different;
the second layer of active layer is doped, and the doping process is sensitive to the height of the doped region, so that a high-doped region can be formed at the overlapped position of the second layer of active layer and the first layer of active layer only by carrying out the doping process once, a light-doped region is formed at the non-overlapped position of the second layer of active layer and the first layer of active layer and the position which is not covered by the covering layer, and a light-doped drain region is formed at the interval position of the covering region and the source region and the drain region; namely, the high-doped region and the light-doped region can be formed only by carrying out a doping process once, and the manufacturing steps of the manufacturing process of the thin film transistor are simplified.
In the method for manufacturing a thin film transistor having a lightly doped drain structure in the background art, since doping is performed twice, in order to prevent the doping process from affecting the second active region between the source region and the drain region during the first doping, the thickness of the required wide capping region is large, that is, the thickness of the wide capping region serving as a doping mask is large, which causes the technical problem that the thin film transistor manufactured by the method has low threshold voltage and low on-state current. The manufacturing method of the thin film transistor only needs to dope once, and does not need a doping mask any more, so that the thin film transistor manufactured by the manufacturing method of the thin film transistor does not have the technical problem of low threshold voltage and on-state current caused by the larger thickness of the doping mask.
The method for manufacturing a thin film transistor of the present invention can be applied to the manufacture of a top gate thin film transistor, and can also be applied to the manufacture of a bottom gate thin film transistor. A method of manufacturing a top gate type thin film transistor and a method of manufacturing a bottom gate type thin film transistor are described below, respectively.
When the manufacturing method of the thin film transistor is used for manufacturing the top gate type thin film transistor, the step of forming the covering layer on the surface of the second layer active layer specifically comprises the following steps: as shown in figures 4 to 6 of the drawings,
forming a gate insulating layer including the gate insulating region 411;
a gate layer is formed over the gate insulating layer, the gate layer including a gate region 412 and the gate region 412 being disposed in a stack with the gate insulating region 411, the stacked gate insulating region 411 and gate region 412 serving as a footprint 310.
Therefore, the gate insulating layer and the gate electrode layer which are stacked and arranged in the thin film transistor are integrally used as the covering layer, the covering layer does not need to be arranged independently, the doping process is simplified to one time, and the manufacturing efficiency of the thin film transistor is improved.
When the manufacturing method of the thin film transistor is used for manufacturing the top gate type thin film transistor, before the step of forming the first active layer, the method further comprises the following steps: as shown in figures 4 to 6 of the drawings,
forming a flexible glue layer 500 on the first side plate surface of the glass substrate, wherein the flexible glue layer is formed by coating polyimide;
and forming a buffer layer 600 on the surface of the flexible adhesive layer, wherein the buffer layer is formed by depositing silicon nitride with the thickness of 50-150 nanometers and silicon dioxide with the thickness of 100-150 nanometers through a vapor deposition method.
The buffer layer is used for resisting water, oxygen and the like; the flexible glue layer is used as a flexible substrate, when the thin film transistor is used as a thin film transistor of an array substrate of the flexible screen, the glass substrate needs to be peeled off in the formation process of the array substrate, and the flexible glue layer is used as the flexible substrate of the array substrate.
When the method for manufacturing a thin film transistor of the present invention is used for manufacturing a bottom gate thin film transistor, as shown in fig. 7 to 9, before the step of forming the first active layer, the method further includes the steps of:
forming a gate layer on the first side plate surface of the substrate, wherein the gate layer comprises a gate region 412;
forming a gate insulating layer covering the gate layer, the gate insulating layer including a gate insulating region 411 and the gate insulating region 411 covering the gate region 412;
in the step of forming the first active layer, the source region 110 and the drain region 120 are located at two opposite sides of the gate region 412, and a space is respectively arranged between the gate region 412 and the source region 110 and the drain region 120;
the capping region 310 is used to cap the gate region 412 in the gate layer.
Compared with the existing manufacturing method of the bottom gate type thin film transistor with the lightly doped drain region structure, only one doping process is needed, and the manufacturing process of the thin film transistor is simplified.
When the method of manufacturing a thin film transistor of the present invention is used for manufacturing a bottom gate thin film transistor, as shown in fig. 7 to 9, before the step of forming a gate layer on the first side plate surface of the substrate, the method further includes the following steps:
forming a flexible glue layer 500 on the first side plate surface of the glass substrate, wherein the flexible glue layer is formed by coating polyimide;
and forming a buffer layer 600 on the surface of the flexible adhesive layer, wherein the buffer layer is formed by depositing silicon nitride with the thickness of 50-150 nanometers and silicon dioxide with the thickness of 100-150 nanometers through a vapor deposition method.
The buffer layer is used for resisting water, oxygen and the like; the flexible glue layer is used as a flexible substrate, when the thin film transistor is used as a thin film transistor of an array substrate of the flexible screen, the glass substrate needs to be peeled off in the formation process of the array substrate, and the flexible glue layer is used as the flexible substrate of the array substrate.
Specifically, the spacing between the cover region and the source region and the spacing between the cover region and the drain region are the same.
Specifically, the first active layer is a polysilicon layer, and the second active layer is a polysilicon layer.
Specifically, the thickness of the first active layer is any value between 100 and 150 nanometers, and the thickness of the second active layer is any value between 10 and 50 nanometers.
The manufacturing method of the thin film transistor of the invention also comprises the following steps:
a source electrode connected to the source region and a drain electrode connected to the drain region, respectively, are formed.
It should be noted that the manufacturing method of the thin film transistor further includes other necessary steps, which are not described in detail.
The invention also provides a manufacturing method of the array substrate, which comprises the manufacturing method of the thin film transistor. The manufacturing method of the array substrate simplifies the manufacturing steps of the manufacturing process of the array substrate.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
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| CN115347000B (en) * | 2022-08-03 | 2025-09-16 | 武汉华星光电技术有限公司 | Array substrate and display panel |
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| CN101840865A (en) * | 2010-05-12 | 2010-09-22 | 深圳丹邦投资集团有限公司 | Manufacturing method of thin film transistor and transistor manufactured by method |
| CN103548146A (en) * | 2011-04-07 | 2014-01-29 | 代表亚利桑那大学的亚利桑那校董会 | Dual active layer for semiconductor device and manufacturing method thereof |
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| JP3255942B2 (en) * | 1991-06-19 | 2002-02-12 | 株式会社半導体エネルギー研究所 | Method for manufacturing inverted staggered thin film transistor |
| KR100653853B1 (en) * | 2005-05-24 | 2006-12-05 | 네오폴리((주)) | Crystallization method of amorphous semiconductor thin film using non-metal seed epitaxial growth and manufacturing method of polycrystalline thin film transistor using same |
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| CN101840865A (en) * | 2010-05-12 | 2010-09-22 | 深圳丹邦投资集团有限公司 | Manufacturing method of thin film transistor and transistor manufactured by method |
| CN103548146A (en) * | 2011-04-07 | 2014-01-29 | 代表亚利桑那大学的亚利桑那校董会 | Dual active layer for semiconductor device and manufacturing method thereof |
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