CN107170708A - Beneficial to the via-hole fabrication process of filling - Google Patents
Beneficial to the via-hole fabrication process of filling Download PDFInfo
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- CN107170708A CN107170708A CN201710318371.8A CN201710318371A CN107170708A CN 107170708 A CN107170708 A CN 107170708A CN 201710318371 A CN201710318371 A CN 201710318371A CN 107170708 A CN107170708 A CN 107170708A
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 230000009286 beneficial effect Effects 0.000 title claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 19
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 5
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 6
- 230000003667 anti-reflective effect Effects 0.000 claims description 5
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000000992 sputter etching Methods 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 abstract description 7
- 239000010937 tungsten Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 238000001459 lithography Methods 0.000 abstract 1
- 239000011799 hole material Substances 0.000 description 99
- 239000010410 layer Substances 0.000 description 49
- 239000007789 gas Substances 0.000 description 16
- 239000000126 substance Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention provides a kind of via-hole fabrication process for being beneficial to filling, is sequentially depositing etching stopping layer, inner layer dielectric layer, anti-reflecting layer in semiconductor device surface, and anti-reflecting layer, inner layer dielectric layer and part etching stopping layer are etched into first through hole；The bottom of first through hole is etched to silicon dioxide layer, the second through hole is formed；Antireflection material is filled in the second through hole；Make the third through-hole that bore is more than the second through hole by lithography；Third through-hole bottom is etched to the silicon dioxide layer formation fourth hole of semiconductor devices, remaining antireflection material in fourth hole is removed, forms fifth hole；Continue to etch fifth hole.Upper through-hole critical size is done through hole pattern of the big and then formation compared with big open end by the via-hole fabrication process that the present invention is provided, so as to reduce the negative effect that depth-to-width ratio is brought to subsequent technique, and then subsequent metal tungsten is reduced to through hole filling difficulty, increase subsequent technique window.
Description
Technical field
The present invention relates to field of semiconductor technology, more particularly to a kind of via-hole fabrication process for being beneficial to filling.
Background technology
As cmos device develops into 40nm and its with lower node, the critical size (CD) of through hole (CT) is with through hole spacing
The diminution of size is also required to do corresponding diminution.The thing followed is the key index depth-to-width ratio (AR of via etch and filling
Ratio further increase), and then huge challenge is brought to our traditional etchings and fill process.
The specific implementation step of existing via etch is：Via etch stop liner 02 is utilized after the formation of cmos device 01
(CESL, CT Etch Stop Layer), HARP (High aspect ratio process, high-aspect-ratio technique), TEOS
The CVD such as (tetraethoxysilanc, tetraethyl orthosilicate) (chemical membrane) mode formed inner layer dielectric layer 03 (ILD,
Inter Layer Dielectric) structure, as shown in Figure 1；One layer of photoresist 04 is applied by photoetching process after surface planarisation,
And development is exposed to it with the light shield for making through hole, as shown in Figure 2；Followed by traditional etching process formation institute
The through hole 05 needed, as shown in figure 3, being filled in through hole 05 with tungsten (W) 06 to leading portion (FEOL, Front End
Of Line) device and back segment (BEOL, Back End Of Line) plain conductor connection, as shown in Figure 4.
The principle of traditional via etch is to utilize of a relatively high gas (such as C of C/F ratios4F8、C5F8) as main
Etchant, being formed in the presence of the power of plasma source has OX/SiN (namely CxFy or CxHFy, wherein x and y representatives
Different numerals, is mainly used to control C/F ratios) the CF free radicals of high selectivity, the larger inert gas Ar of molecular weight is by substrate
Bias assigns and interrupting the molecular link for the material surface molecule that is etched compared with kinetic energy, and CF free radicals react therewith, vapour
Matter is taken away by air pump, and be etched material surface or side wall of byproduct residue is adjusted as profile.O2It is exactly accessory substance cleaning gas
Body (polymer clean gas), the via profiles so that required for obtaining us are adjusted as what accessory substance was measured.And it is usual
For considering for via openings (CT open), we have to use higher substrate bias and larger O2Flow is carried
It can overcome the influence that higher and higher depth-to-width ratio (AR ratio) is brought with less accessory substance for high bomb, and thus
The via profiles for causing current industry are mostly vertical or subvertical patterns.With the spacing dimension of through hole 05 of device
Brought AR ratio further increase is further reduced, causes filling of the subsequent metal tungsten 06 to through hole 05 to be increasingly stranded
Difficulty, or even hollow hole (W seam) 07 is formed, as shown in figure 5, this hollow hole 07 is to device and follow-up wire
Connection causes strong influence.
The content of the invention
The present invention proposes a kind of via-hole fabrication process for being beneficial to filling, for solving filling of the above-mentioned tungsten to through hole
The problem of easily producing hollow hole.
To reach above-mentioned purpose, the present invention provides a kind of via-hole fabrication process for being beneficial to filling, comprised the following steps：
Step one：One semiconductor devices is provided, etching stopping layer, inner layer dielectric layer, anti-reflective are sequentially depositing on its surface
Layer is penetrated, and the anti-reflecting layer, inner layer dielectric layer and part etching stopping layer are etched into first through hole；
Step 2：Structure to step one formation is performed etching, and the bottom of the first through hole is etched into silica
Layer, forms the second through hole；
Step 3：To the structure deposit anti-reflective material of step 2 formation so that filling antireflection in second through hole
Material；
Step 4：The first photoresistance is deposited in step 3 formation structure, and by former second through hole correspondence on the first photoresistance
Develop third through-hole at place, and the bore of third through-hole is more than the bore of second through hole；
Step 5：Structure to step 4 formation is performed etching, and third through-hole bottom is etched into the semiconductor
The silicon dioxide layer formation fourth hole of device, removes the remaining antireflection material in the fourth hole, forms the 5th
Through hole；
Step 6：Continue to etch fifth hole.
Preferably, forming the second photoresistance in step one on the anti-reflecting layer, formed by exposure, development, etching
First through hole.
Preferably, etching described in step one is plasma etching, etching gas include CF4And CH2F2。
Preferably, plasma etching the second through hole of formation, etching gas bag are carried out in step 2 to the first through hole
Include CF4、C4F6, Ar and O2。
Preferably, the silicon dioxide layer thickness is etched away in step 2 3/4ths form the second through hole.
Preferably, the diameter of the fourth hole is gradually reduced from top to bottom.
Preferably, removing in the fourth hole the remaining antireflection material in step 5 by the described 4th
It is passed through in through hole comprising O2Plasma gas.
Preferably, step 6, which is used, includes C4F6, Ar and O2Plasma gas etch it is remaining in the fifth hole
Silica, is then used comprising CH2F2、CH3F, Ar and O2Plasma gas continue to etch the fifth hole.
Preferably, the semiconductor devices is cmos device.
Compared with prior art, the beneficial effects of the invention are as follows：The present invention provides a kind of through hole making side for being beneficial to filling
Method, comprises the following steps：
Step one：One semiconductor devices is provided, etching stopping layer, inner layer dielectric layer, anti-reflective are sequentially depositing on its surface
Layer is penetrated, and anti-reflecting layer, inner layer dielectric layer and part etching stopping layer are etched into first through hole；
Step 2：Structure to step one formation is performed etching, and the bottom of first through hole is etched into silicon dioxide layer, shape
Into the second through hole；
Step 3：To the structure deposit anti-reflective material of step 2 formation so that filling antireflection material in the second through hole；
Step 4：The first photoresistance is deposited in step 3 formation structure, and by former second through hole correspondence on the first photoresistance
Develop third through-hole at place, and the bore of third through-hole is more than the bore of the second through hole；
Step 5：Structure to step 4 formation is performed etching, and third through-hole bottom is etched into the two of semiconductor devices
Silicon oxide layer formation fourth hole, removes remaining antireflection material in fourth hole, forms fifth hole；
Step 6：Continue to etch fifth hole.
Upper through-hole critical size is done through hole of the big and then formation compared with big open end by the via-hole fabrication process that the present invention is provided
Pattern, so that the negative effect that depth-to-width ratio is brought to subsequent technique is reduced, and then it is difficult to through hole filling to reduce subsequent metal tungsten (W)
Degree, increases subsequent technique window.
Brief description of the drawings
Via etch and the process schematic of filling that Fig. 1~Fig. 4 provides for prior art；
Fig. 5 produces hollow hole schematic diagram for the through hole filling that prior art is provided；
The via-hole fabrication process process schematic that Fig. 6~12 provide for the present invention.
In Fig. 1-Fig. 5：01-CMOS devices, 02- etching stopping layers, 03- inner layer dielectric layers, 04- photoresists, 05- through holes,
06- tungstens, 07- hollow hole；
In Fig. 6~12：10-CMOS devices, 20- etching stopping layers, 30- inner layer dielectric layers, 40- anti-reflecting layers, 51- first
Through hole, the through holes of 52- second, 53- third through-holes, 54- fourth holes, 55- fifth holes, 60- antireflection materials, the light of 70- first
Resistance, 90- silicon dioxide layers.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
The present invention provides a kind of via-hole fabrication process for being beneficial to filling, comprises the following steps：
Step one：There is provided has silicon dioxide layer 90 on a cmos device 10, cmos device 10, sharp first on its surface
With CVD mode depositing etch stop layer 20, then HARP, TEOS is utilized to form inner layer dielectric layer with similar mode
30, redeposited one layer of anti-reflecting layer 40 after surface planarisation is carried out to inner layer dielectric layer 30, the is deposited on the anti-reflecting layer 40
Two photoresistances, are made photoetching and then etching using through hole light shield, are etched using plasma gas, etching gas include CF4And CH2F2, will
The anti-reflecting layer 40, inner layer dielectric layer 30 and part etching stopping layer 20 etch first through hole 51, as shown in Figure 6；
Step 2：First through hole 51 is performed etching, etched using plasma gas, etching gas include CF4、C4F6、Ar
And O2, the bottom of the first through hole 51 is etched to silicon dioxide layer 90, the thickness of silicon dioxide layer 90 is etched away four points
Three, formed the second through hole 52, as shown in Figure 7；
Step 3：Fig. 8 is refer to, the antireflection material 60 to filling mobility and fillibility in the second through hole 52, such as
BARC (Bottom Anti Reflection Coating), carries out planarization process so that it possesses even curface to it
Condition, good precondition is provided for follow-up exposure imaging；
Step 4：Fig. 9 is refer to, the first photoresistance 70 is deposited in step 3 formation structure, uses the through hole in step one
Light shield makees photoetching so that develop third through-hole 53 on the first photoresistance 70 in place of the former correspondence of second through hole 52, but specifically make
The bore of third through-hole 53 is more than the bore of second through hole 52, that is to say, that bridging can occur between through hole is not caused
Under the premise of the critical size of through hole is done greatly as far as possible, to be subsequently formed larger through hole opening；
Step 5：Third through-hole 53 is performed etching, etched using plasma gas, mainly using CF4, Ar and O2Deng mixed
Close gas and the high energy that bombs is combined to BARC/OX low selection ratios by the anti-BARC and its silica of surrounding in through hole using it
Pushed away under under the limitation of the exposure imaging figure of third through-hole 53, and then form larger through hole opening, namely fourth hole 54, such as
Shown in Figure 10, the diameter of the fourth hole 54 is gradually reduced from top to bottom.
Then, the remaining antireflection material 60 in the fourth hole 54, the main strong oxygen using high flow capacity are removed
The property changed gas O2, dissociated by plasma and remove the BARC of the internal residual of fourth hole 54, the silica in hole is complete
It is complete exposed clean to be removed when next step is etched, Figure 11 is refer to, fifth hole 55 is formed；
Step 6：Continue to etch fifth hole 55, Figure 12 is refer to, mainly using C4F6, the mixed gas such as Ar and O2 provides
Higher OX/SiN selection ratio, is parked in the surface of etching stopping layer 20 simultaneously by the antireflection material of the residual at the hole bottom of fifth hole 55
Material 60 is removed totally, and the opening of fifth hole 55 is further expanded, and etching stopping layer 20 finally is expanded into bore, mainly made
Use CH2F2、CH3F, Ar and O2 provide SiN/OX high selectivity, and the 5th with big open end pattern required for ultimately forming is led to
Hole 55, so as to improve the precondition of subsequent metal tungsten filling.
Upper through-hole critical size is done through hole of the big and then formation compared with big open end by the via-hole fabrication process that the present invention is provided
Pattern, so that the negative effect that depth-to-width ratio is brought to subsequent technique is reduced, and then it is difficult to through hole filling to reduce subsequent metal tungsten (W)
Degree, increases subsequent technique window.
Above-described embodiment is described the present invention, but the present invention is not limited only to above-described embodiment.Obvious this area
Technical staff can carry out various changes and modification to invention without departing from the spirit and scope of the present invention.So, if this hair
These bright modifications and variations belong within the scope of the claims in the present invention and its equivalent technologies, then the present invention is also intended to include
Including these changes and modification.
Claims (9)
1. a kind of via-hole fabrication process for being beneficial to filling, it is characterised in that comprise the following steps：
Step one：One semiconductor devices is provided, etching stopping layer, inner layer dielectric layer, anti-reflecting layer are sequentially depositing on its surface,
And the anti-reflecting layer, inner layer dielectric layer and part etching stopping layer are etched into first through hole；
Step 2：Structure to step one formation is performed etching, and the bottom of the first through hole is etched into silicon dioxide layer, shape
Into the second through hole；
Step 3：To the structure deposit anti-reflective material of step 2 formation so that filling antireflection material in second through hole；
Step 4：The first photoresistance is deposited in step 3 formation structure, and former second through hole correspondence part on the first photoresistance is aobvious
Shadow goes out third through-hole, and the bore of third through-hole is more than the bore of second through hole；
Step 5：Structure to step 4 formation is performed etching, and third through-hole bottom is etched into the semiconductor devices
Silicon dioxide layer formation fourth hole, remove the remaining antireflection material in the fourth hole, form fifth hole；
Step 6：Continue to etch fifth hole.
2. the via-hole fabrication process as claimed in claim 1 for being beneficial to filling, it is characterised in that in the antireflection in step one
The second photoresistance is formed on layer, first through hole is formed by exposure, development, etching.
3. the as claimed in claim 2 via-hole fabrication process for being beneficial to filling, it is characterised in that etching described in step one for etc.
Ion etching, etching gas include CF4And CH2F2。
4. the via-hole fabrication process as claimed in claim 1 for being beneficial to filling, it is characterised in that logical to described first in step 2
Hole carries out plasma etching the second through hole of formation, and etching gas include CF4、C4F6, Ar and O2。
5. the via-hole fabrication process as claimed in claim 1 for being beneficial to filling, it is characterised in that described two are etched away in step 2
3/4ths of silicon oxide layer thickness form the second through hole.
6. the via-hole fabrication process as claimed in claim 1 for being beneficial to filling, it is characterised in that used in step 5 and include CF4、
Ar and O2Plasma gas etch to form fourth hole, the diameter of the fourth hole is gradually reduced from top to bottom.
7. the via-hole fabrication process as claimed in claim 1 for being beneficial to filling, it is characterised in that the described 4th is removed in step 5
The remaining antireflection material into the fourth hole by being passed through comprising O in through hole2Plasma gas.
8. the via-hole fabrication process as claimed in claim 1 for being beneficial to filling, it is characterised in that step 6 uses and includes C4F6、Ar
And O2Plasma gas etch remaining silica in the fifth hole, then use comprising CH2F2、CH3F, Ar and O2
Plasma gas continue to etch the fifth hole.
9. the via-hole fabrication process as claimed in claim 1 for being beneficial to filling, it is characterised in that the semiconductor devices is CMOS
Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710318371.8A CN107170708A (en) | 2017-05-08 | 2017-05-08 | Beneficial to the via-hole fabrication process of filling |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710318371.8A CN107170708A (en) | 2017-05-08 | 2017-05-08 | Beneficial to the via-hole fabrication process of filling |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107170708A true CN107170708A (en) | 2017-09-15 |
Family
ID=59812474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710318371.8A Pending CN107170708A (en) | 2017-05-08 | 2017-05-08 | Beneficial to the via-hole fabrication process of filling |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109494186A (en) * | 2018-11-22 | 2019-03-19 | 上海华力集成电路制造有限公司 | Conducive to the production method of the rewiring through-hole taper pattern of filling |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030022522A1 (en) * | 2001-07-13 | 2003-01-30 | Yukio Nishiyama | Method for manufacturing semiconductor device |
| CN101593725A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The formation method of contact hole |
| CN102760688A (en) * | 2011-04-28 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Dual damascene structure and formation method thereof as well as semiconductor device |
| CN103904024A (en) * | 2012-12-26 | 2014-07-02 | 第一毛织株式会社 | Method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith |
| CN104425358A (en) * | 2013-08-28 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming plug |
-
2017
- 2017-05-08 CN CN201710318371.8A patent/CN107170708A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030022522A1 (en) * | 2001-07-13 | 2003-01-30 | Yukio Nishiyama | Method for manufacturing semiconductor device |
| CN101593725A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The formation method of contact hole |
| CN102760688A (en) * | 2011-04-28 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Dual damascene structure and formation method thereof as well as semiconductor device |
| CN103904024A (en) * | 2012-12-26 | 2014-07-02 | 第一毛织株式会社 | Method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith |
| CN104425358A (en) * | 2013-08-28 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming plug |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109494186A (en) * | 2018-11-22 | 2019-03-19 | 上海华力集成电路制造有限公司 | Conducive to the production method of the rewiring through-hole taper pattern of filling |
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Application publication date: 20170915 |
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