CN107195545A - The semiconductor devices formed for the method for thermal annealing and by this method - Google Patents

Abstract

According to various embodiments, a kind of method can include：Dopant is arranged in semiconductor regions；The radiation absorption layer for including at least one allotrope of carbon or being formed by least one allotrope of carbon is formed at least a portion of semiconductor regions；And illumination radiation absorbed layer is to be at least partially heated semiconductor regions at least in part by using electromagnetic radiation, to activate dopant at least in part.Additionally provide a kind of semiconductor devices formed by the above method.

Description

Method for thermal annealing and semiconductor device formed by the method

technical field

Various embodiments generally relate to methods for thermal annealing and semiconductor devices formed by the methods.

Background technique

In general, semiconductor technology may process semiconductor material on or in a substrate (also called a wafer or carrier), for example to manufacture integrated circuits (also called chips). During processing of semiconductor materials, certain processing steps may be applied, such as thinning the substrate, doping the semiconductor material, or forming one or more layers over the substrate.

In order to dope a semiconductor material, dopants may be implanted into the semiconductor material. The semiconductor material can be further processed to fully activate the dopants. Dopant activation may provide the desired electronic interaction from the dopant in the semiconductor material. To activate the dopants, thermal energy may be transferred to the semiconductor material after dopant implantation. Typically, thermal annealing by furnace or rapid thermal processing is used to provide thermal equilibrium or rapid processing with high peak temperatures in less than a second to minimize chemical diffusion of dopants. To transfer thermal energy to the semiconductor material, a laser can be used, which is also known as laser thermal annealing (LTA).

Generally, the wavelength of the laser light is adjusted according to the semiconductor material to provide maximum transfer of energy to the semiconductor material. In other words, high transfer efficiency can be provided, which reduces the energy required for LTA. Alternatively, adjust the wavelength of the laser light according to the desired absorption length. Short wavelengths can lead to energy concentration in surface parts.

On the other hand, due to the high absorption, the penetration depth of the laser is limited according to the wavelength of the laser. The total energy of the laser can be limited by the thermal limit that the semiconductor material can withstand. Thus, the processing itself may limit the depth of semiconductor material to which dopants are activated.

On the other hand, even if the wavelength of the laser light is tuned for maximum energy transfer, there is still a significant portion of the laser light that is inherently reflected by the semiconductor material and can no longer be used to transfer energy to the semiconductor material. For example, semiconductor materials typically reflect about 60% of laser light. Therefore, the total energy required to obtain the desired amount of thermal energy transferred to the semiconductor material is much higher than this thermal energy. In other words, the power consumption of the laser source and the corresponding capital cost of providing processing equipment with the required power capabilities (eg, adequate optics, multiple pulsed lasers, and multiple wavelength lasers) are generally high.

Typically, anti-reflective coatings are formed over semiconductor materials to reduce the amount of reflected light. However, the anti-reflective coating may affect the result of the heat treatment due to the mechanical stress introduced in the anti-reflective coating. Conventional anti-reflective coatings are based on constructive and destructive interference interactions provided by a composite layer structure and thus may require more effort to prepare. In addition, inherent stresses may be built into the antireflective coating due to fabrication, which may relax as the underlying portion of the semiconductor material melts. A topographical map of the relaxed anti-reflective coating can be incorporated into the cured portion of the semiconductor material. Coatings subjected to compressive stress are prone to cracking and spalling if the support provided by the mechanically rigid underlying semiconducting material is lost due to melting. Furthermore, the coating can intermix with the molten semiconductor material and contaminate the semiconductor material. This can lead to process failures or limit the scope of processes such as heat treatment.

Contents of the invention

According to various embodiments of the invention, a method may include: disposing a dopant in a semiconductor region; forming a radiation absorbing layer over at least a portion of the semiconductor region, the radiation absorbing layer comprising at least one isotope of carbon an isotrope or formed from the allotrope; and at least partially activating the dopant by at least partially irradiating the radiation absorbing layer with electromagnetic radiation to at least partially heat the semiconductor region.

Description of drawings

In the drawings, like reference numerals generally refer to like parts throughout the views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the accompanying drawings, in which:

1A, 1B and 1C respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments;

2A, FIG. 2B and FIG. 2C respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments;

3A, 3B and 3C respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments;

4A and 4B respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments;

5A and FIG. 5B respectively show schematic diagrams of reflection characteristics of semiconductor devices according to various embodiments in methods according to various embodiments;

6A and 6B show a schematic side view or a schematic cross-sectional view, respectively, of a radiation absorbing layer according to various embodiments in a method according to various embodiments;

Figures 7A, 7B and 7C each show a schematic side view of a radiation absorbing layer according to various embodiments in a method according to various embodiments;

8A and 8B respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments;

Figure 9 shows a schematic perspective view of a radiation absorbing layer according to various embodiments in a method according to various embodiments;

10A, 10B and 10C respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments;

11A, 11B and 11C respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments;

12A and 12B respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments;

Figure 13 shows a schematic top view of a semiconductor device according to various embodiments in a method according to various embodiments;

14 shows a schematic cross-sectional view of a semiconductor device according to various embodiments in a method according to various embodiments;

15A and 15B respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments;

16A, 16B and 16C respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments; and

17A and 17B illustrate semiconductor devices according to various embodiments in methods according to various embodiments, respectively.

detailed description

The following detailed description shows, by way of illustration, the drawings and specific details of embodiments in which the invention can be practiced.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations or designs.

The word "over" as used in reference to a deposited material formed "on" a side or surface may be used herein to mean that the deposited material may be formed "directly" on the implied side or surface, for example in direct contact therewith . The term "over" as used in reference to deposited material formed "on" a side or surface may be used herein to mean that the deposited material may be formed "indirectly" on the implied side or surface, where one or more additional A layer is arranged between an implied side or surface and the deposition material.

The term "towards" as used with respect to extending "towards" or "towards" adjacent a structure (or substrate, wafer, or carrier) may be used herein to mean extending along or along a surface of a substrate, wafer, or carrier. Positional relationship. This means that the surface of the substrate (eg the surface of the carrier or the surface of the wafer) can be used as a reference, often referred to as the main processing surface of the substrate (or the main processing surface of the carrier or wafer). Furthermore, the term "width" used in reference to the "width" of a structure (or of a structural element) may be used herein to refer to the lateral extension of a structure. Furthermore, the term "height" used in relation to the height of a structure (or of a structure element) may be used herein to denote the extension of a structure in a direction perpendicular to the substrate surface (eg, perpendicular to the main processing surface of the substrate). The term "thickness" used in relation to the "thickness" of a layer may be used herein to denote the spatial extension of the layer perpendicular to the surface of the support (material) on which the layer is deposited. If the surface of the support is parallel to the surface of the substrate (eg parallel to the main processing surface), the "thickness" of a layer arranged on the support may be the same as the height of the layer. Furthermore, a "vertical" structure may refer to a structure extending in a direction perpendicular to a lateral direction (eg, perpendicular to the main processing surface of a substrate), and a "vertical" extending may refer to a structure extending in a direction perpendicular to a lateral direction. The extension of the direction (for example, the extension perpendicular to the main processing surface of the substrate).

The phrase "at least one of" with reference to a group of elements may be used herein to mean at least one element from a group of elements. For example, the phrase "at least one of" with reference to a set of elements may be used herein to refer to a selection of one of the listed elements, a plurality of the listed elements, a plurality of individually listed elements. element or multiples of the listed elements.

According to various embodiments, the metallic material may comprise or be formed of at least one chemical element from the following group of chemical elements (also referred to as metals): tungsten (W), aluminum (Al), copper ( Cu), nickel (Ni), magnesium (Mg), chromium (Cr), iron (Fe), zinc (Zn), tin (Sn), gold (Au), silver (Ag), iridium (Ir), platinum ( Pt), indium (In), cadmium (Cd), bismuth (Bi), vanadium (V), titanium (Ti), palladium (Pd), zirconium (Zr), or may include at least one of these chemical elements A metal alloy of a chemical element or formed from the metal alloy. As an example, a metal alloy may comprise or be formed from at least two metals (e.g., two or more metals in the case of an intermetallic compound); or at least one metal (e.g., one or more a metal) and at least one other chemical element (for example, a nonmetal or semimetal). As an example, a metal alloy may comprise or be formed from at least one metal and at least one non-metal such as, for example, carbon (C) or nitrogen (N) in the case of steel or nitrides). As examples, metal alloys may include or be formed from more than one metal (e.g., two or more metals), such as various compounds of gold and aluminum, various compounds of copper and aluminum, copper and zinc Various compounds of copper (for example, "brass") or various compounds of copper and tin (for example, "bronze"), which include, for example, various intermediate metal compounds. According to various embodiments, the metal material may be conductive.

A semiconducting material, layer, region, etc., is understood to have a moderate electrical conductivity, e.g., a conductivity (measured at room temperature and in the direction of a constant electric field, e.g., at a constant electric field) in the range of about ^10-6 Siemens per meter (S/m) to About 10 ⁶ S/m. A conductive material (e.g., metallic material), layer, region, etc. may be understood to have a high electrical conductivity, e.g., a conductivity (measured at room temperature and in a constant electric field direction, e.g., a constant electric field) greater than about 10 ⁶ S/m, e.g., greater than About 10 ⁷ S/m. An electrically insulating material, layer, region, etc. may be understood to have a low electrical conductivity, e.g., an electrical conductivity (measured at room temperature and in the direction of a constant electric field, e.g., at a constant electric field) of less than about ^10-6 S/m, such as less than about ^10-10 S/m.

According to various embodiments, a semiconductor region (e.g., comprising or formed from a substrate) may include or be formed from various types of semiconductor materials, including, for example, Group IV semiconductors (e.g., silicon or germanium), compound semiconductors such as III-V compound semiconductors such as gallium arsenide, or other types of semiconductors including group III semiconductors, group V semiconductors, or polymers. In one embodiment the semiconductor region is made of silicon (doped or undoped), in an alternative embodiment the semiconductor region is a silicon-on-insulator (SOI) wafer. Alternatively, any other suitable semiconductor material may be used for the semiconductor region, for example, semiconductor compound materials such as gallium phosphide (GaP), indium phosphide, and any suitable semiconductor material such as indium gallium arsenide (InGaAs) Ternary semiconductor compound material or quaternary semiconductor compound material.

According to various embodiments, the semiconductor region may be processed to form one or more semiconductor chips in and/or over the semiconductor region. A semiconductor chip may include an active chip region. The active chip region may be provided in a portion of the semiconductor region and may include one or more semiconductor circuit elements such as transistors, resistors, capacitors, diodes, and the like. One or more semiconductor circuit elements may be configured to perform computational or memory operations. Alternatively or additionally, one or more semiconductor circuit elements may be configured to perform switching or rectification operations, eg in power electronics.

According to various embodiments, the semiconductor chip may be cut from the semiconductor region by removing material from a cutout region of the semiconductor region, also referred to as dicing or singulating the semiconductor region. For example, removal of material from a kerf region of a semiconductor region may be handled by scribing and breaking, dicing, blade dicing, or mechanical sawing (eg, using a dicing saw). After dicing the semiconductor chip, the semiconductor chip can be electrically contacted and encapsulated, for example by means of a mold material, into a chip carrier (also called chip housing), which can then be suitable for use in an electronic device. For example, a semiconductor chip may be wire bonded to a chip carrier, and the chip carrier may be soldered to a printed circuit board.

According to various embodiments, doping in (e.g. crystalline) substrate materials (e.g. silicon) may be provided, for example, by enhancing light absorption due to covering the substrate material with carbon allotropes such as carbon nanotubes (CNTs). Agent activation. CNTs can inherently provide low radiation reflection. Illustratively, a substrate surface covered with a carbon allotrope (eg, CNT) may appear optically black due to minimized reflection of radiation, resulting in enhanced absorption of radiation in the substrate.

According to various embodiments, a suitable catalyst (eg, a metal, a metal containing material, or a metal alloy such as a metal compound) may be provided for the formation of the carbon allotrope. The catalyst (also referred to as a catalyst layer) can be deposited (eg, using PVD processing) as islands on the substrate. The islands may have very low lateral extension (eg less than a few nanometers, eg less than 10 nm). The islands can serve as growth sites for carbon allotropes of CNTs. Depending on the processing conditions (including the precursors), the carbon allotrope can grow on or under the catalyst islands previously deposited onto the substrate (eg, comprising silicon).

According to various embodiments, a radiation absorbing layer for the semiconductor region may be provided. The radiation absorbing layer can increase the absorption of light (eg, in the form of a laser or flash) by reducing the portion of the light that is reflected. The energy (energy of the laser) utilization (eg, the transferred portion of energy) for the radiation absorbing layer may be greater than the energy utilization for the semiconductor region (eg for the planar surface of the semiconductor region). The energy delivered to the semiconductor region may optionally be used to melt a portion of the semiconductor region.

According to various embodiments, the surface of the semiconductor region may be selectively covered with a radiation absorbing layer, eg to increase absorption of laser light. The radiation absorbing layer can increase (or maximize) absorption of laser light and conduction of heat to the semiconductor region. Forming the radiation absorbing layer can be provided by various processes described herein.

According to various embodiments, the radiation absorbing layer (eg, at least one carbon allotrope) may have high electrical conductivity (eg, metallic properties) or moderate electrical conductivity (eg, semiconducting properties). Optionally, the radiation absorbing layer (e.g., at least one carbon allotrope) may have a thermal conductivity of greater than about 500 watts per meter Kelvin (W/m·K), such as greater than about 1000 W/m·K , such as more than about 2000W/m·K, such as more than about 3000W/m·K, such as more than about 4000W/m·K, such as more than about 5000W/m·K, such as more than about 5500W/m·K , for example greater than or equal to about 6000 W/m·K. At least one of electrical conductivity and thermal conductivity may be understood to be parallel to a direction pointing to the semiconductor region (eg, parallel to a macroscopic surface normal of the semiconductor region). According to various embodiments, the radiation absorbing layer may comprise a plurality of particles, each particle comprising or being formed from at least one carbon allotrope. Multiple particles may be set separately from each other.

According to various embodiments, increased absorption of light (eg laser light) results in increased energy transfer via the radiation absorbing layer to the semiconductor region. Increased absorption of light (or correspondingly energy transfer to the semiconductor region) leads to thermal activation of the dopant. During thermal activation of the dopant, the semiconductor region may be partially shielded by the radiation absorbing layer, which exemplarily results in an identification fingerprint of the radiation absorbing layer remaining in the semiconductor region. An identifying marker may provide indirect evidence of increased absorption of light (or correspondingly energy transfer). For example, if the radiation absorbing layer includes a plurality of carbon nanotubes that conduct heat locally to the semiconducting region, the identification mark will appear. This spatial inhomogeneity of the radiation absorbing layer can alter the electronic properties of the semiconductor region.

The use of a radiation absorbing layer according to various embodiments may be confirmed by various types of structural and/or chemical analysis to reveal the presence of identifying markings. The identification mark may be characterized by portions of the semiconductor region that are embedded in another part of the semiconductor region separately from each other (eg, disjointly) and whose electronic properties differ from the other part.

1A , 1B and 1C show schematic cross-sectional or side views of a semiconductor device according to various embodiments in a method according to various embodiments.

According to various embodiments, a method may include disposing a dopant 108 in the semiconductor region 102 in 100a, eg, through the surface 104 of the semiconductor region 102 . The semiconductor region 102 may include or be formed from a wafer (also referred to as a substrate), for example a semiconductor wafer such as a silicon wafer. In one embodiment, semiconductor region 102 may be a portion of a wafer. In one embodiment, semiconductor region 102 may be a wafer.

Disposing the dopant in the semiconductor region 102 may include forming a concentration of the dopant (in other words, atoms of the dopant) in the semiconductor region 102 greater than about 10 ¹⁵ atoms per cubic centimeter (atoms/cm ³ ), such as Greater than about 10 ¹⁶ atoms/cm ³ , such as greater than about 10 ¹⁷ atoms/cm ³ , such as greater than about 10 ¹⁸ atoms/cm ³ , such as greater than about 10 ¹⁹ atoms/cm ³ , such as greater than about 10 ²⁰ atoms/cm ³ , such as Greater than about 10 ²¹ atoms/cm ³ or even higher (e.g., substantially equal to the solubility of the dopant in semiconductor region 102), for example in the range from about 10 ¹⁶ atoms/cm ³ to about 10 ²² atoms/cm ³ Within, for example, in the range from about 10 ¹⁶ atoms/cm ³ to about 10 ¹⁸ atoms/cm ³ .

Disposing dopants in semiconductor region 102 may include delivering dopants 108 into semiconductor region 102 in 100a, eg, by ion beam implantation. In other words, dopants may be implanted into the semiconductor region 102 by ion beam implantation. To implant the dopant 108 , the semiconductor region 102 may be irradiated with an ion beam 106 comprising ions of the dopant 108 . Alternatively or additionally, the dopant 108 may be provided by a gas 106 comprising the dopant 108 (also referred to as a dopant source gas), from which the dopant 108 is released and diffuses into the semiconductor region 102 in. Alternatively or additionally, dopants may be provided via a dopant source layer (see FIG. 3A ).

By disposing 106 a dopant 108 in the semiconductor region 102 , a layer 1081 (also referred to as doped layer 1081 ) comprising the dopant and the material of the semiconductor region 102 may be formed. The doped layer 108 l may be formed in the surface portion 102 s of the semiconductor region 102 , wherein the surface portion 102 s of the semiconductor region 102 adjoins the surface 104 of the semiconductor region 102 . In other words, the doped layer 108 l may be formed between the surface 104 of the semiconductor region 102 and the base region 112 b of the semiconductor region 102 . As an example, the doped layer 108l may include or be formed of a backside collector layer.

According to various embodiments, the method may include forming, in 100b, a radiation absorbing layer 114 over the semiconductor region 102 (eg, over the doped layer 1081 ), eg to reduce reflection. The surface 104 of the semiconductor region 102 may be at least partially covered by the radiation absorbing layer 114 . In one embodiment, surface 104 may be partially covered by radiation absorbing layer 114 . In one embodiment, surface 104 may be completely covered by radiation absorbing layer 114 .

Reducing the reflectivity may result in increased absorption of electric field radiation via the radiation absorbing layer 114 . In other words, the absorption coefficient of the radiation absorbing layer 114 may be greater than the absorption coefficient of the semiconductor region 102 . Accordingly, the reflection coefficient of the radiation absorbing layer 114 may be smaller than the reflection coefficient of the semiconductor region 102 . The absorption coefficient may describe the fraction of incident electromagnetic radiation that is absorbed, for example, by the semiconductor region 102 or the radiation absorbing layer 114 . Absorbed electromagnetic radiation can be converted into heat energy. The reflection coefficient may describe the fraction of incident electromagnetic radiation that is reflected (including re-emitted) by the semiconductor region 102 and the radiation absorbing layer 114, respectively. Reflection coefficient may be understood as also relating to inhomogeneous reflection (re-emission), eg by scattering of electromagnetic radiation.

According to various embodiments, the method may include at least partially activating the dopant 108 by at least partially irradiating the radiation absorbing layer 114 with electromagnetic radiation 110 in 100c. Electromagnetic radiation may be at least partially absorbed (in other words, converted into thermal energy) by the radiation absorbing layer 114 . Thermal energy may then be transferred (conducted) to the semiconductor region 102 , for example via thermal conduction.

By irradiating the radiation absorbing layer 114, the semiconductor region 102 may be at least partially heated (in other words, at least a portion of the semiconductor region 102 may be heated). By activating the dopant 108, an activated dopant 108a may be provided. By activating the dopant 108, the dopant 108 may be incorporated into the semiconductor region 102, for example in the lattice structure of the semiconductor region 102, to provide an activated dopant 108a. Alternatively or additionally, the dopant 108 may chemically react with the semiconductor region 102 , eg, with the material of the semiconductor region 102 , by activating the dopant 108 to provide the activated dopant 108 a. By activating the dopant 108, at least one electrical property of the surface portion 102s (eg of the doped layer 108l) may be changed. For example, the electrical conductivity of the surface portion 102s , eg of the doped layer 1081 , may be increased by activating the dopant 108 .

During heating of the semiconductor region 102 , the temperature of the semiconductor region 102 , for example the temperature of the surface portion 102 s of the semiconductor region 102 , may be increased, for example by a temperature difference. The temperature difference may be at least about 200 Kelvin (K), such as at least about 400K, such as at least about 600K, such as at least about 800K, such as at least about 1000K, such as in the range from about 600K to about 1500K. The temperature difference may be provided over the heating time to define a ratio of temperature difference to heating time (also referred to as heating rate). The heating rate may be greater than about 100 Kelvin per second (K/s), such as greater than about 200 K/s, such as greater than about 300 K/s, such as greater than about 400 K/s, such as greater than about 1000 K/s (corresponding to ¹⁰ K/s ), such as greater than about 2000 K/s, such as greater than about 5000 K/s, such as greater than about 10 ⁴ K/s, such as greater than about 10 ⁵ K/s, such as greater than about 10 ⁶ K/s, such as greater than about 10 ⁷ K/s s, such as greater than about 10 ⁸ K/s, such as greater than about 10 ⁹ K/s, such as greater than about 10 ¹⁰ K/s. The heating time may be defined by (eg, equal to) the irradiation time, in other words, the irradiation time is the time during which the radiation absorbing layer 114 is irradiated with the electromagnetic radiation 110 (eg, forming a temperature gradient towards the radiation absorbing layer 114). The exposure time (e.g., per radiation pulse) may be less than about one microsecond (1 μs), such as less than about 1 nanosecond (1 ns), such as less than about 100 picoseconds (100 ps), such as less than about 10 picoseconds (10 ps).

The temperature difference and the heating depth (in other words the depth of the semiconductor region to which it is heated eg by at least the temperature difference) may define the temperature gradient formed by irradiating the radiation absorbing layer 114 . A temperature gradient may be directed towards the radiation absorbing layer 114 . The temperature gradient can be defined by the ratio of the temperature difference and the heating depth, for example, at least about 200 Kelvin (K) per heating depth (d), such as at least about 400K/d, such as at least about 600K/d, such as at least about 800K/d , for example at least about 1000K/d, for example in the range from about 600K/d to about 1500K/d. For example, the temperature gradient can be at least about 200 Kelvin per micron (K/μm), such as at least about 400 K/μm, such as at least about 600 K/μm, such as at least about 800 K/μm, such as at least about 1000 K/μm, such as between about In the range of 600K/μm to about 1500K/μm.

To activate the dopant 108, the semiconductor region 102 may be at least partially—for example at least a surface portion of the semiconductor region 102—heated to a temperature of at least 70% of the melting temperature of the semiconductor region (greater than or equal to the doping activation temperature), For example greater than 900°C (eg, to provide a mixed or glassy phase).

According to various embodiments, the thickness 112 (also referred to as the heating thickness 112 , eg, the melting depth if melted) of the portion of the semiconductor region 102 that is heated with, for example, at least a temperature difference (eg, the surface portion 102s ) may be greater than about 0.4 μm, such as greater than about 0.5 μm, such as greater than about 0.6 μm, such as greater than about 0.7 μm, such as greater than about 0.8 μm, such as greater than about 0.9 μm, such as greater than about 1 μm, such as greater than about 1.5 μm, such as greater than about 2 μm, For example in the range from about 1 μm to about 100 μm. Heating depth 112 may be a spatially averaged depth. The heating depth 112 may be greater than the thickness of the doped layer 1081, for example greater than the implantation depth (the penetration depth of the ion beam into the semiconductor region 102), which may be defined by the energy of the ions in the ion beam. Heating depth 112 may define a temperature gradient (eg, along a depth direction, eg, parallel to a macroscopic surface normal of semiconductor region 102 ), eg, by a temperature difference within heating depth 112 .

The semiconductor region 102 may be heated at least partially, which means that at least the surface portion 102s of the semiconductor region 102 may be heated. Surface portion 102s may optionally be segmented. For example, the surface portion 102s may include multiple segments that are heated to a temperature greater than the temperature between the segments. Accordingly, a mask 1802 may be used to expose segments of the surface portion 102s (see, eg, FIG. 10A ).

According to various embodiments, the heat treatment may include or be formed by at least one of non-equilibrium heat treatment and athermal heat treatment. The non-thermal heating treatment can include forming electromagnetic radiation from an electromagnetic radiation source, wherein the wavelength of the electromagnetic radiation can be independent of the temperature of the electromagnetic radiation source. For example, the wavelength of the electromagnetic radiation may be defined by at least one of: the material (eg, optionally active material) of the electromagnetic radiation source, the optical resonator of the electromagnetic radiation source, and the energy supplied to the electromagnetic radiation source. For example, the source of electromagnetic radiation may comprise or may be formed by a source of athermal electromagnetic radiation.

According to various embodiments, the source of electromagnetic radiation may comprise or be formed by an optical resonator, eg in the case of a laser source. In this case, electromagnetic radiation may comprise or may be laser radiation, polarized radiation, pulsed radiation and/or coherent radiation. Pulsed radiation may comprise at least one pulse of electromagnetic radiation (one or more pulses of electromagnetic radiation).

The non-equilibrium heat treatment may include creating a temperature gradient in the semiconductor region 102 . For example, a non-equilibrium heat treatment may require a furnace. Illustratively, in non-equilibrium heat processing, substantially no thermal equilibrium is reached during heating. For example, in a non-equilibrium heating process, the radiation absorbing layer 114 can absorb a greater amount of electromagnetic radiation than it emits, for example, the radiation absorbing layer 114 can absorb at least twice the amount of electromagnetic radiation it emits, e.g. At least five times the electromagnetic radiation it emits, such as at least ten times the electromagnetic radiation it emits, such as (eg during irradiation) at least one hundred times the electromagnetic radiation it emits. Alternatively or additionally, in a non-equilibrium heating process, the thermal energy introduced by the electromagnetic radiation may propagate further (e.g., to the semiconductor region) after the electromagnetic radiation is turned off or interrupted (e.g., between pulses of the electromagnetic radiation). 102, for example propagated to a part of the semiconductor region 102 deeper than the heating depth). For example, the non-equilibrium heat treatment may include or be accomplished by heating the semiconductor region 102 substantially only through the radiation absorbing layer 114 . As used herein, heating the semiconductor region 102 may be understood as transferring thermal energy (e.g., via electromagnetic radiation) into the semiconductor region 102 and/or through the surface 104 of the semiconductor region 102 (to and from the semiconductor region 102 ). A portion adjacent to surface 104, also referred to as surface portion 102s). For example, heating the semiconductor region 102 can include irradiating the radiation absorbing layer 114 with electromagnetic radiation, wherein the electromagnetic radiation can be at least partially absorbed by the radiation absorbing layer 114 and at least partially absorbed by (e.g., adjacent to) the radiation absorbing layer 114 of the semiconductor region 102. ) of the surface portion 102s absorbs. In this regard, a "region adjacent to the surface" or "surface portion 102s" may refer to a region to a depth 112 of up to about 100 μm, up to about 50 μm, up to about 20 μm, such as up to about 15 μm, such as up to about 10 μm , such as up to about 5 μm, such as up to about 3 μm, such as up to about 2 μm.

According to various embodiments, the electromagnetic radiation may comprise at least one discrete wavelength (one or more discrete wavelengths, e.g., two discrete wavelengths, three discrete wavelengths, four discrete wavelengths, five discrete wavelengths, more than five discrete wavelengths, such as ten or more discrete wavelengths). Radiation having discrete wavelengths may be understood as radiation having distinct (eg linear) radiation intensity peaks at discrete wavelengths. Radiation intensity peaks may be broadened to define a wavelength range (eg, width) around discrete wavelengths. The radiation intensity peak may have a width (e.g., full width at half maximum (FWHM)) of less than about 25% of (the value of) the discrete wavelength, such as less than about 10% of the discrete wavelength, such as less than about 5% of the discrete wavelength, such as Less than about 2.5% of the discrete wavelength, such as less than about 1% of the discrete wavelength. For example, radiation intensity peaks having a FWHM of less than about 25% (e.g., 10%, 5%, or 1%) of the peak position and/or less than about 10 nm (e.g., 5 nm, 1 nm, 0.5 nm, or 0.1 nm) can be viewed as discrete wavelengths. If the electromagnetic radiation includes more than one discrete wavelength (eg, more than one radiation intensity peak), then optionally at least two adjacent discrete wavelengths may partially overlap. For example, if the radiation intensity between two radiation intensity peaks falls to less than about 50% of the maximum radiation intensity of the radiation intensity peak of two adjacent radiation intensity peaks having the lower maximum radiation intensity (e.g., 25%, 10 %, 5% or 1%), then two adjacent radiation intensity peaks of electromagnetic radiation can be regarded as discrete wavelengths. Alternatively or additionally, if the distance between two adjacent radiation intensity peaks (for example, between the positions of two adjacent radiation intensity peaks) is larger than the radiation intensity having the larger width among the two adjacent radiation intensity peaks The width of the peak (FWHM), for example greater than 200% of the width, eg greater than 500% of the width, two adjacent radiation intensity peaks of the electromagnetic radiation can be regarded as discrete wavelengths.

According to various embodiments, the electromagnetic radiation used to irradiate the radiation absorbing layer 114 may comprise or may be electromagnetic radiation (e.g., having at least one discrete wavelength) within the electromagnetic radiation range (also referred to as the absorbing range) for which The reflectivity of the semiconductor region 102 is less than the reflectivity of the radiation absorbing layer 114, for example less than the reflectivity of the radiation absorbing layer 114 by at least about 0.1, at least about 0.2, at least about 0.3, at least about 0.4, at least about 0.5, at least about 0.6. In other words, the radiation absorbing layer 114 can define an absorption range (eg, defining at least one of electromagnetic radiation, a wavelength range, an energy range, and a frequency range) for which the radiation absorbing layer 114 has a higher reflectivity than the semiconductor region 102 A reflectivity greater than at least the stated value.

According to various embodiments, thermal energy may be absorbed primarily by surface portion 102 (in other words, within the heating depth), for example, more than about 50% (e.g., more than about 75%, such as more than about 80%) of the thermal energy converted from electromagnetic radiation. For example, more than about 90%) more thermal energy may be absorbed by surface portion 102s.

According to various embodiments, the semiconductor region 102 may comprise or be formed of a single-crystal semiconductor material (also referred to as the single-crystal material of the semiconductor region 102 ). Alternatively or additionally, the semiconductor region 102 may comprise or be formed of a polycrystalline semiconductor material (also referred to as the polycrystalline material of the semiconductor region 102 ).

2A , 2B and 2C respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments.

According to various embodiments, the method may include arranging 106 a dopant 108 in the semiconductor region 102 in 200a, for example away from the surface 104 of the semiconductor region 102 . The arrangement 106 of the dopant 108 in 200a may be configured in a similar manner to the arrangement 106 of the dopant 108 in 100a. Illustratively, the dopant 108 may be arranged away from the surface 104 of the semiconductor region 102 by using a large implantation depth. Alternatively or additionally, after arranging 106 the dopant 108 , the doped layer 1081 may be covered (eg at least partially) by the (eg undoped) material of the semiconductor region 102 . For example, the doped layer 1081 may be at least partially buried in the semiconductor region 102 .

By arranging 106 a dopant 108 in the semiconductor region 102 , a doped layer 1081 comprising the material of the semiconductor region 102 and the dopant may be formed. Doped layer 1081 may be formed in surface portion 102s of semiconductor region 102 , wherein surface portion 102s of semiconductor region 102 includes surface 104 (eg, planar surface 104 ) of semiconductor region 102 . In other words, the doped layer 108 l may be formed between the surface 104 of the semiconductor region 102 and the base region 112 b of the semiconductor region 102 , for example away from the surface 104 of the semiconductor region 102 .

According to various embodiments, the method may include forming a radiation absorbing layer 114 over the semiconductor region 102 in 200b, for example away from the base region 112b of the semiconductor region 102 . Forming radiation absorbing layer 114 in 200b may be configured similarly to forming radiation absorbing layer 114 in 100b (see FIG. 1B ).

According to various embodiments, the method may include at least partially activating the dopant 108 by at least partially irradiating the radiation absorbing layer 114 with the electromagnetic radiation 110 to at least partially heat the semiconductor region 102 in 200c. In other words, activated dopants 108a may be provided. Activation of dopant 108 in 200c may be configured similarly to activation of dopant 108 in 100c.

3A and 3B respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments.

According to various embodiments, arranging dopants in the semiconductor region 102 may include forming a dopant source layer 302 on the semiconductor region 102 (eg, on the surface 104 of the semiconductor region 102 ) in 300 a. The dopant source layer 302 may be formed by at least one of physical vapor deposition, chemical vapor deposition, or fluid deposition (eg, spin coating). Alternatively or additionally, the dopant source layer 302 may include or be formed of a doped oxide layer. In at least one embodiment, the dopant source layer 302 may be provided by (eg, as part of) another wafer (and more generally, another semiconductor region). Another semiconductor region may be arranged over the semiconductor region 102 . By heating the other semiconductor region, dopants may diffuse out of the other semiconductor region and into the semiconductor region 102 (which may also be referred to as face-to-face transfer).

The dopant source layer 302 may include a dopant 108, for example disposed in or as part of a host material of the dopant source layer 102, for example chemically bonded to the host material. middle. The dopant source layer 302 may be formed by depositing a host material over the semiconductor region 102 (eg, over the surface 104 of the semiconductor region 102 ).

According to various embodiments, arranging the dopant in the semiconductor region 102 may include transferring the dopant 108 , for example from the dopant source layer 302 , into the semiconductor region 102 in 300 b. Dopant source layer 302 (eg, a host material) may be configured to provide dopant 108 , for example, by heating dopant source layer 302 . Dopant source layer 302 may be heated by irradiating with electromagnetic radiation 110 or tempering. The dopant 108 provided by the dopant source layer 302 may migrate (eg, by chemical reaction and/or diffusion) into the semiconductor region 102 , eg to form a doped layer 1081 (see eg FIGS. 1B and 2B ).

According to various embodiments, irradiating the dopant source layer 102 with electromagnetic radiation 110 may not be sufficient to simultaneously activate the dopant 108 . In other words, as shown in FIGS. 1C and 2C , after delivering the dopant 108 into the semiconductor region 102 , a radiation absorbing layer 114 may be disposed over the semiconductor region 102 to activate the dopant 108 . Accordingly, the dopant source layer 102 may be removed from the semiconductor region 102 (to expose the semiconductor region 102 ) prior to forming the radiation absorbing layer 114 .

FIG. 3C shows a schematic cross-sectional or side view of a semiconductor device according to various embodiments in a method according to various embodiments.

According to various embodiments, the method may include heating the semiconductor region 102 by irradiating the radiation absorbing layer 114 with the electromagnetic radiation 110 in 300c.

By heating, the semiconductor region 102 (eg, the surface portion 102s of the semiconductor region 102 ) may optionally be at least partially melted, in other words partially (eg, segmentally) or completely melted. For example, during activation of the dopant, the surface portion 102s of the semiconductor region 102 may be partly in a molten phase and partly in a solid phase (mixed phase). Alternatively or additionally, the semiconductor region 102 may be at least partially in a glass phase (eg, between a solid phase and a molten phase). The glass phase may have a greater viscosity than the molten phase of the semiconductor region 102 .

Alternatively, the semiconductor region 102 may remain in the solid phase (in other words, not leave the solid phase) during heating. Maintaining the solid phase of the semiconductor region 102 may promote homogeneous activation and/or dopant distribution in the semiconductor region 102 .

The melting temperature of the semiconductor region 102 may be less than at least one of (eg, about 75%, eg, about 50%, eg, about 25%) of the melting temperature and the sublimation temperature of the radiation absorbing layer 114 .

The absorption (absorption coefficient) of the semiconductor region 102 (eg, its material) may be smaller in the glass phase or molten phase than in the solid phase. In other words, at least partially melting the semiconductor region 102 may reduce the absorption coefficient of the semiconductor region 102 . By using the radiation-absorbing layer 114 , the absorption of the electromagnetic radiation 110 can be maintained independently of the state of the semiconductor region 102 , for example.

By heating, the semiconductor region 102 can be at least partially (e.g., at least the surface portion 102s of the semiconductor region 102) heated to a temperature equal to or greater than the melting temperature of the semiconductor region 102, such as greater than 1200° C. (e.g., to provide a glass phase or transition of at least one of the molten phases). The temperature may be provided for a time greater than the heating time.

According to various embodiments, heating the semiconductor region 102 may define a temperature peak (e.g., a maximum temperature at the end of the heating time) greater than 70% of the melting temperature of the semiconductor region 102, such as greater than 900° C., such as greater than the melting temperature of the semiconductor region 102 temperature.

According to various embodiments, absorption of electromagnetic radiation 110 (eg, including laser light) via the radiation absorbing layer 114 may result in a stable energy transfer (from the electromagnetic radiation) to the semiconductor region 102 .

4A and 4B respectively show a schematic cross-sectional view or a side view of a semiconductor device according to various embodiments in a method according to various embodiments.

According to various embodiments, the method may include irradiating the radiation absorbing layer 114 with electromagnetic radiation 110 incident on the semiconductor region 102 (incident electromagnetic radiation 110 ) in 400 a.

Reflection coefficient may define the fraction of reflected electromagnetic radiation 410 to incident electromagnetic radiation 110 . Electromagnetic radiation 110 (illustratively, incident electromagnetic radiation 110 ) may be provided by irradiating radiation absorbing layer 114 . Electromagnetic radiation 110 may be provided by an electromagnetic radiation source (eg, a laser source).

According to various implementations, the reflectance may depend on the angle of incidence 410w (also referred to as principal angle of incidence 410w) between the incident electromagnetic radiation 110 and the macroscopic surface plane 404 (illustratively, the mean surface plane 404 ) of the semiconductor region 102 . The macroscopic surface plane 404 may be arranged and aligned such that it includes a maximum number of points (or correspondingly a maximum intersection with the surface of the semiconductor region 102 ) of the surface of the semiconductor region 102 .

According to various implementations, the incident electromagnetic radiation 110 may be in a direction substantially perpendicular to the macroscopic surface plane 404 . In other words, the angle of incidence 110w may range from about 80° to about 100°, for example about 90°. In other words, incident electromagnetic radiation 110 may be substantially parallel to macroscopic surface normal 404n of semiconductor region 102 . The macroscopic surface normal 404 n of the semiconductor region 102 may be perpendicular to the macroscopic surface plane 404 of the radiation absorbing layer 114 .

If the incident electromagnetic radiation 110 is in a direction substantially normal to the macroscopic surface plane 404, the reflection coefficient may be minimized. The reflection coefficient may depend on the angle of incidence, the wavelength of the electromagnetic radiation and the material of the semiconductor region 102 . Alternatively or additionally, the reflectance may depend on the polarization of the electromagnetic radiation 110 .

The reflectance provided by the radiation absorbing layer 114 according to various embodiments may also be referred to as a total effective reflectance. The reflectance provided by the planar surface of the semiconductor region 102 may also be referred to as a reference reflectance. The total effective reflectance may be less than the reference reflectance (eg about 75% of the reference reflectance, eg about 50% of the reference reflectance, eg about 25% of the reference reflectance). The total effective reflectance may be less than about 0.59 (in other words, less than 59% of incident electromagnetic radiation 110 may be reflected), such as less than about 0.5, such as less than about 0.4, such as less than about 0.3, such as less than about 0.2, such as less than about 0.1, such as Less than about 0.05, for example in the range from about 0.01 to about 0.5.

According to various embodiments, the radiation absorbing layer 114 may include or be formed from a plurality of protrusions 412, such as the elongated protrusions 412 shown in detail view 400b (see FIG. 4B)). For example, each protrusion in plurality of protrusions 412 may be tubular. A plurality of recesses 412 r shaped according to the plurality of protrusions 412 may be formed between the plurality of protrusions 412 .

As shown in detailed view 400b , radiation absorbing layer 114 may provide scattering of incident electromagnetic radiation 110 via a plurality of protrusions 412 . As described below, radiation absorbing layer 114 may be configured to provide multiple scattering of incident electromagnetic radiation 110 . Multiple scattering may include at least two scattering events (a first scattering and a second scattering).

A first portion 110a of incident electromagnetic radiation 110 (also referred to as first scattered electromagnetic radiation 110a) may be directed toward the radiation absorbing layer (in a first scattering event) at a first protrusion 104a (e.g., a first CNT) of the radiation absorbing layer 114. The second protrusions 104b (eg, second CNTs) of 114 are scattered. A second portion 110b of the incident electromagnetic radiation 110 (e.g., the remaining incident electromagnetic radiation 110) may be directed into the first protrusion 104a of the radiation absorbing layer 114 and further directed into the semiconductor region 102 to be absorbed (for absorbing it The energy is transferred to the semiconductor region 102).

A first portion 410 of the first scattered electromagnetic radiation 110a (also referred to as second scattered electromagnetic radiation 410 ) may be scattered at a second protrusion 114b of the radiation absorbing layer 114 remote from the radiation absorbing layer 114 (second scattering). A second portion 110c of the first scattered electromagnetic radiation 110a (e.g., the remaining first scattered electromagnetic radiation 110a) may be directed into the second protrusion 114b of the radiation absorbing layer 114 and further directed into the semiconductor region 102 to be absorbed ( used to transfer its energy to the semiconductor region 102).

As shown in FIG. 4B , the second scattered electromagnetic radiation 410 may be directed away from the semiconductor region 102 . Alternatively, the radiation absorbing layer 114 may be configured such that the second scattered electromagnetic radiation 410 may be directed to another protrusion of the radiation absorbing layer 114 . In other words, multiple scattering may include more than two scattering events. Exemplarily, electromagnetic radiation scattered at a portion of the radiation-absorbing layer 114 can be directed to at least one further portion of the radiation-absorbing layer 114 such that at least one further portion of the electromagnetic radiation can be absorbed by at least one of the radiation-absorbing layers 114 Another part absorbs. For example, electromagnetic radiation may be scattered at least one of the interior or exterior of the radiation absorbing layer 114 . For example, at least a portion of the electromagnetic radiation may be transmitted into the protrusions of the radiation absorbing layer 114 . The total effective reflection coefficient can be defined by the superposition of all multiple scattering events. As shown in Figure 4B, if the multiple scattering includes two scattering events, the total effective reflection coefficient can be defined by the superposition of the first scattering event and the second scattering event

According to various embodiments, the correlation between the reflection coefficient and its associated angle of incidence may depend on the shape and material of the radiation absorbing layer 114 and the wavelength of the electromagnetic radiation. For example, the reflectance may decrease as the angle of incidence 410w decreases. The variation of the reflectance with the angle of incidence 410w of the radiation absorbing layer 114 may be smaller than that of the semiconductor region 102 (eg, having a planar surface 104 ).

In contrast to this, antireflective coatings are based on constructive interference (in a direction towards the semiconductor region 102 ) and destructive interference (in a direction away from the semiconductor region 102 ). Optionally, an antireflection coating (also referred to as an antireflection layer) may be formed between the radiation absorbing layer 114 and the semiconductor region 102 (see FIG. 11B ).

FIG. 5A shows in a schematic diagram 500 a reflection properties of a semiconductor device according to various embodiments in a method according to various embodiments. Schematic 500a shows reflection properties 502, 504, 506 relating reflection coefficient 501 to energy 503 (in electron volts-eV) of electromagnetic radiation (eg, for a principal angle of incidence substantially equal to 90°).

The schematic diagram 500a shows the reflection characteristic 502 and the reflection characteristic 504 of the reference reflection coefficient, ie the dependence between the reference reflection coefficient of electromagnetic radiation and the energy 503 . The reflection characteristic 502 represents the reference reflection coefficient 501 expected from theory, while the reflection characteristic 504 represents the reference reflection coefficient 501 according to the measurement (for example, at the flat surface of the semiconductor region 102 ).

The schematic diagram 500a shows the reflection characteristic 506 of the total effective reflection coefficient. The reflection characteristic 506 represents the reflection coefficient 501 of the radiation absorbing layer 114 according to various embodiments, a detailed view is provided in diagram 500b.

According to various embodiments, the electromagnetic radiation may comprise or be formed from radiation ranging from ultraviolet radiation to infrared radiation. For example, electromagnetic radiation may include radiation in the range from about 0.1 eV (corresponding to a wavelength of about 12400 nm, such as in mid-infrared radiation) to about 12.4 eV (corresponding to a wavelength of about 100 nm, such as in vacuum ultraviolet radiation), For example in the range from about 1 eV (corresponding to a wavelength of about 1240 nm, for example in near-infrared radiation) to about 7 eV (corresponding to a wavelength of about 180 nm, for example in vacuum ultraviolet radiation), for example in the range from about 2 eV (corresponding to A wavelength of about 620 nm, for example in red visible radiation) to about 6 eV (corresponding to a wavelength of about 205 nm, for example in deep ultraviolet radiation), for example in the range from about 3 eV (corresponding to a wavelength of about 410 nm, for example in ultraviolet visible radiation) to about 5 eV (corresponding to a wavelength of about 250 nm, eg in deep UV radiation), for example about 4 eV (corresponding to a wavelength of about 308 nm, eg in intermediate UV radiation). According to various embodiments, the wavelength of the radiation may be in a wavelength range where the reflectivity of the semiconductor region 102 is less than the reflectivity of the radiation absorbing layer 114 . This wavelength range may also be referred to herein as the "absorption range".

According to various embodiments, the reflective properties 506 (e.g., the total reflectance 501) of the radiation absorbing layer 114 may be, for example, in the range (e.g., the absorption range) from about 3 eV (corresponding to about 415 nm) to about 7 eV (e.g., from less than about 0.5, such as less than about 0.45, such as less than about 0.4, for electromagnetic radiation in the range of about 3.5 eV (corresponding to about 350 nm) to about 5 eV (corresponding to about 250 nm). Electromagnetic radiation may be incident along a direction of a macroscopic surface normal of the semiconductor region 102 . The macroscopic surface normal of the semiconductor region 102 may be perpendicular to the macroscopic surface plane 404 of the radiation absorbing layer 114 (see eg FIGS. 4A and 4B ).

FIG. 5B shows in a schematic diagram 500 b reflection characteristics of a semiconductor device according to various embodiments in a method according to various embodiments. Schematic 500b shows reflection characteristics 512, 506 over a wavelength 505 (eg, in nanometers (nm)) of electromagnetic radiation (eg, for a principal angle of incidence substantially equal to 90°).

The schematic diagram 500a shows the reflection characteristics 512 for the reference reflection coefficient and the reflection characteristics 506 for the total effective reflection coefficient (in other words, for the radiation absorbing layer 114 according to various embodiments).

According to various embodiments, the electromagnetic radiation may comprise or be formed by radiation having a wavelength in the absorption range, for example, from about 250 nm (corresponding to about 5 eV) to about 350 nm (corresponding to about 3.5 eV). range, such as from about 300nm (corresponding to about 4.1eV) to about 320nm (corresponding to about 3.88eV), or for example from about 500nm (corresponding to about 2.5eV) to about 600nm (corresponding to about 2eV ), for example, includes or is formed by green light (eg, green laser).

Larger wavelengths can increase the penetration depth of electromagnetic radiation, which can increase heating depth. Alternatively or additionally, larger wavelengths may be provided to increase the delivered energy since the energy is distributed over a larger heating depth.

According to various embodiments, the total effective reflectance may be reduced 522 by increasing at least one of the thickness of the radiation absorbing layer 114 and the number of carbon allotropes of the radiation absorbing layer 114 .

6A and 6B each show a schematic side view 600 of a radiation absorbing layer 114 over a semiconductor region 102 according to various embodiments in a method according to various embodiments. FIG. 6A shows a segmented radiation absorbing layer 114 , while FIG. 6B shows a continuous radiation absorbing layer 114 .

The segmented radiation absorbing layer 114 may include or be formed from a plurality of separate portions 602a, 602b. Each of the plurality of discrete portions 602a, 602b may include a plurality of protrusions 114a, 114b (eg, provided by a plurality of carbon allotropes). Openings 602o may be formed between adjacent ones of the plurality of separated portions 602a, 602b. The opening 602 may partially expose the semiconductor region 102 . This may enable adjustment of the heating profile of the semiconductor region 102 (in other words, the distribution of thermal energy transferred into the semiconductor region 102 ). Illustratively, each of the plurality of discrete portions 602a, 602b may be disposed over a portion of the semiconductor region 102 that is intended to be heated (eg, heated beyond a dopant activation temperature), such as to is being activated.

Optionally, at least two of the plurality of separate portions 602a, 602b are different in their reflective properties, eg in terms of their reflectance coefficients for predetermined wavelengths (eg outside the absorption range).

The continuous radiation absorbing layer 114 may continuously cover the semiconductor region 102 . Optionally, the continuous radiation absorbing layer 114 may comprise or be formed from a plurality of contiguous portions 602a, 602b, such as in the previously described configuration.

7A to 7C respectively show schematic side views of forming the radiation absorbing layer 114 according to various embodiments in the method according to various embodiments.

The method may include forming a catalyst layer 702 (also may be referred to as a seed layer 702 ) over the semiconductor region 102 in 700a. The catalyst layer 702 may include or be formed of a metal material (also referred to as a metal catalyst), such as at least one of nickel, cobalt, yttrium, and an alloy including cobalt and iron. The catalyst layer 702 may include or be formed of nanoparticles, for example including or being formed of a metallic material. The catalyst layer 702 may include or be formed from a plurality of separate islands 702a. Each island 702a of catalyst layer 702 may include or be formed from one or more nanoparticles, eg, an accumulation of more than one nanoparticle. The lateral extension 701 (perpendicular to the macroscopic surface normal) of each island 702a of the catalyst layer 702 may be less than about 50 nm, such as less than about 10 nm, such as less than about 5 nm, such as less than about 1 nm.

According to various embodiments, catalyst layer 702 may be formed by physical vapor deposition (eg, by sputtering).

According to various embodiments, the lateral extension (e.g., diameter) of each island in the plurality of discrete islands 702a may be less than or equal to about 50 nm, such as less than or equal to about 25 nm, less than or equal to about 10 nm, less than or equal to Equal to about 5nm.

The method may include exposing the catalyst layer to a gaseous precursor 704 in 700a. The gaseous precursor 704 (also referred to as a carbon-containing gas) may include or be formed from a molecule containing carbon, such as, for example, at least one of acetylene, ethylene, ethanol, and methane. The gaseous precursor 704 may be provided in a mixture with a process gas (eg, including or formed from at least one of ammonia, nitrogen, and hydrogen). The structured surface 104 of the semiconductor region 102 may be heated during formation of the radiation absorbing layer 114 , for example to greater than about 500° C., for example to about 700° C.

According to various embodiments, forming the radiation absorbing layer 114 may include, for example, chemical vapor deposition using a gaseous precursor 704 . Optionally, the formation of the radiation absorbing layer 114 may be enhanced, eg, by plasma. Alternatively or additionally, forming the radiation absorbing layer 114 may include physical vapor deposition, such as laser deposition or cathodic arc deposition.

According to various embodiments, catalyst layer 702 may be configured to crack gaseous precursor 704 , for example, by pyrolytic decomposition of gaseous precursor 704 (pyrolysis-induced decomposition). Cracking of gaseous precursor 704 may provide carbon from gaseous precursor 704 . Carbon may accumulate to the catalyst layer, for example, by forming at least one allotrope of carbon 712 (also referred to as at least one carbon allotrope 712), such as the carbon nanotube radiation absorbing layer 114 shown schematically in FIG. 7B 702 island 702a. Alternatively or additionally, other types of allotropes 712 of carbon may be formed, such as at least one of graphite, fullerenes, and carbon nanofoams.

The method may include forming the radiation absorbing layer 114 in a first formation mode in 700b. At least one carbon allotrope 712 of radiation absorbing layer 114 may be formed using carbon from gaseous precursor 704 . At least one carbon allotrope 712 may be formed over catalyst layer 702 . For example, each allotrope of carbon 712 may form one of the plurality of protrusions 114a, 114b. Illustratively, one or more carbon allotropes in at least one allotrope 712 may grow on top of each island 702a of catalyst layer 702 .

The method may include forming the radiation absorbing layer 114 in the second formation mode in 700b. At least one carbon allotrope 712 of radiation absorbing layer 114 may be formed using carbon from gaseous precursor 704 . At least one allotrope 712 may be formed between the catalyst layer 702 and the semiconductor region 102 . Illustratively, at least one carbon allotrope 712 may elevate islands 702a of catalyst layer 702 .

FIG. 8A shows a schematic cross-sectional or side view of a semiconductor device 800 a according to various embodiments in a method according to various embodiments.

By activating the dopant, a doped layer 1081 may be formed in the semiconductor region 102 at the first side 102b of the semiconductor region 102 (see FIGS. 1C and 2C ). The first side 102 b (also referred to as the bottom side 102 b ) may be opposite to the second side 102 t (also referred to as the top side 102 t ) of the semiconductor region 102 . The activated dopant 108a may be disposed in the doped layer 1081 proximate to (eg, in physical contact with) the first side 102b (eg, the surface 104 ) of the semiconductor region 102 . In other words, the semiconductor device 800a may include an activated dopant 108a disposed proximate to the surface 104 (eg, in physical contact with the surface 104 of the semiconductor region 102).

Optionally, the semiconductor device 800a may include a semiconductor circuit element 1702, such as a power semiconductor circuit element 1702, formed over the semiconductor region at the second side 102t of the semiconductor region or/and on the semiconductor region at the second side 102t of the semiconductor region. in the area. For example, the semiconductor circuit element 1702 may include at least one transistor (in other words, one or more transistors, such as one or more insulated gate bipolar transistors) in electrical contact 1704 with the doped layer 1081 of the semiconductor region 102 or may be formed by the at least one transistor. A transistor is formed.

Optionally, the semiconductor device 800a may include at least one first contact pad 1706 (eg, at least one collector contact pad 1706 ) formed in electrical contact with the doped layer 1081 of the semiconductor region 102 . In other words, at least one first contact pad 1706 may be electrically connected to the semiconductor circuit element 1702 via the doped layer 1081. Alternatively or additionally, the semiconductor device 800a may include at least one second contact pad 1708 (eg, source/drain contact pad 1708), in other words, the semiconductor device 800a may include an electrical contact 1710 with the semiconductor circuit element 1702. One or more second contact pads 1708 are formed on the second side 102t. The more than one second contact pads 1708 may optionally include gate contact pads, which may be formed electrically insulated from the semiconductor region 102 , for example.

FIG. 8B shows a schematic cross-sectional or side view of a semiconductor device 800 b according to various embodiments in a method according to various embodiments.

According to various embodiments, methods may include removing the radiation absorbing layer 114 . Removing the radiation absorbing layer 114 may include or be formed by at least one of chemical treatment and heat treatment.

The chemical treatment may include or be formed by at least one of wet chemical etching and dry chemical etching (eg, plasma etching).

For example, at least one carbon allotrope 712 of radiation absorbing layer 114 may be removed by plasma ashing. For plasma ashing, a plasma source may provide a plasma (eg, monatomic plasma) to which the radiation absorbing layer 114 is exposed. For example, the plasma may include or be formed from at least one of oxygen and fluorine. The plasma (also referred to as reactive species) may chemically react with at least one carbon allotrope 712 of the radiation absorbing layer 114 to form ash, which may be further removed by a vacuum pump. During plasma ashing, heat may optionally be applied to the radiation absorbing layer 114 .

During removal of the radiation absorbing layer 114, the semiconductor device 800b may be oriented such that the radiation absorbing layer 114 faces gravity. This may allow the islands 712 of the catalyst layer 702 (see, eg, the second mode of formation in FIG. 7C ) to descend when their connection to the semiconductor region 102 is lost. As an example, this may facilitate cleaning of the semiconductor region 102 .

Alternatively or additionally, removing the radiation absorbing layer 114 may include a wet etching process to remove the islands 712 of the catalyst layer 702 .

Fig. 9 shows a schematic perspective view of a radiation absorbing layer 114 according to various embodiments in a method according to various embodiments.

According to various embodiments, the radiation absorbing layer 114 may include or be formed of a wood-like structure (eg, wood of CNTs). The wood-like structure may comprise or be formed by a plurality of protrusions 114a, 114b, for example in the shape of a tube (tubes 114a, 114b) and arranged remotely from each other. The wood-like structure may include or be formed from carbon nanotubes. Each protrusion of the plurality of protrusions 114 a , 114 b may extend away from the semiconductor region 102 , eg, in a direction perpendicular to a macroscopic surface normal 404 n of the semiconductor region 102 . The extension of each of the plurality of protrusions 114 a , 114 b may be greater than at least one of the distance between them or their extension parallel to the macroscopic surface normal 404 n of the semiconductor region 102 . In other words, each of the plurality of protrusions 114a, 114b may be elongated. Optionally, each protrusion of the plurality of protrusions 114a, 114b may comprise a hollow surrounded by at least one wall. For example, carbon nanotubes may be single-walled or multi-walled, such as double-walled.

FIG. 10A shows a semiconductor device 1000 a according to various embodiments in a schematic cross-sectional view or a side view in a method according to various embodiments.

According to various embodiments, constructing the radiation absorbing layer 114 may include using a mask 1802 . Accordingly, a mask 1802 may be formed over the semiconductor region 102 , for example over the surface 104 of the semiconductor region 102 . Mask 1802 may be formed prior to forming radiation absorbing layer 114 . The mask 1802 may include a plurality of openings 1804 exposing the semiconductor region 102 , eg exposing the surface 104 of the semiconductor region 102 .

According to various embodiments, the openings of the plurality of openings 1804 may be arranged in a pattern, eg, in a checkerboard structure, eg periodically (eg, in two dimensions). According to various embodiments, the mask 1802 may include or be formed of an oxide, such as at least one of a semiconductor oxide, a metal oxide, and a polymer such as a photoresist or other resist.

According to various embodiments, radiation absorbing layer 114 may be formed over mask 1802 . After the radiation absorbing layer 114 is formed, the mask 1802 may be removed together with the portion of the radiation absorbing layer 114 disposed over the material of the mask 1802 (also referred to as a lift-off process).

According to various embodiments, the lift-off process may include: forming a sacrificial layer (eg, which may include or be formed of a polymer, such as photoresist or other resist) over the semiconductor region 102; constructing the sacrificial layer to provide mask 1802 ; form radiation absorbing layer 114 over mask 1802 (and semiconductor region 102 ); remove mask 1802 such that at least a portion of radiation absorbing layer 114 remains over semiconductor region 102 . Exemplarily, when the mask 1802 is removed (for example using a mask remover, which for example includes at least one of a solvent or an etchant), the radiation absorbing layer 114 separated from the semiconductor region 102 by the mask 1802 At least a portion is lifted off and removed along with the underlying mask 1802 . After the lift-off process, at least one further portion of the radiation absorbing layer 114 may remain over regions of the semiconductor region 102 exposed by the plurality of openings 1804, for example in the plurality of openings 1804 where the radiation absorbing layer 114 and the semiconductor region 102 are physically connected to each other. touch. Exemplarily, at least one further portion of the radiation absorbing layer 114 remaining above the semiconductor region 102 comprises an inverted structure of the mask 1802 .

For example, the mask 1802 may be configured to form a first region 1904a and a second region 1904b having different reflective properties (see FIG. 11C or see FIGS. 5A and 5B ). For example, through a first lift-off process, a first catalyst layer may be formed. In addition, through the second lift-off process, a second catalyst layer may be formed. The first catalyst layer and the second catalyst layer may differ from each other, for example, in at least one of island density (number per area), metallic material, lateral extension of the islands, and nanoparticle density.

FIG. 10B shows a semiconductor device 1000 b according to various embodiments in a schematic cross-sectional view or a side view in a method according to various embodiments.

According to various embodiments, activating the dopant may include or may be formed by irradiating the radiation absorbing layer 114 with the laser source 1812 (laser light source). Laser source 1812 may be configured to provide a laser beam 1814 comprising optionally coherent electromagnetic radiation (eg, laser light).

According to various implementations, the laser source 1812 may be configured to provide a pulsed laser beam 1814 . Alternatively or additionally, laser source 1812 may be configured to provide continuous laser beam 1814 .

According to various embodiments, irradiating the radiation absorbing layer 114 may include or be formed by scanning the radiation absorbing layer 114 with electromagnetic radiation, such as a laser beam 1814 . In other words, electromagnetic radiation, such as laser beam 1814, may be moved over radiation absorbing layer 114, for example, according to a predetermined irradiation pattern.

Laser beam 1814 may comprise or be formed from an fluence (eg, per pulse) in the range of about 2 J/cm2 to about 10 J/cm2, in the range of about 3 J/cm2 to about 5 J/cm2.

FIG. 10C shows a schematic cross-sectional or side view of a semiconductor device 1000c according to various embodiments in a method according to various embodiments.

According to various embodiments, the semiconductor device 1000c may include a metallization layer 1822 formed over the semiconductor region 102, for example over the activated dopant 108a. Metallization layer 1822 may include or be formed from a metallic material, such as copper. The metallization layer 1822 may include or be formed of at least one contact pad. According to various embodiments, metallization layer 1822 , such as at least one contact pad, may include or be formed from an opaque material. In other words, metallization layer 1822, such as at least one contact pad, may be opaque.

FIG. 11A shows a schematic cross-sectional or side view of a semiconductor device 1100 a according to various embodiments in a method according to various embodiments.

According to various embodiments, the semiconductor device 1100a may comprise a plurality of semiconductor circuit elements 1702a , 1702b , 1702c electrically connected 1904 to each other in parallel and in electrical contact with the doped layer 1081 of the semiconductor region 102 . By way of example, the plurality of semiconductor circuit elements 1702a, 1702b, 1702c may be part of or form a power semiconductor circuit element.

Optionally, the semiconductor device 1100 a may include a first metallization layer 1922 on the second side 102 t of the semiconductor region 102 . Each semiconductor circuit element of plurality of semiconductor circuit elements 1702 a , 1702 b , 1702 c may be electrically connected 1904 to first metallization layer 1922 . At least one second contact pad 1708 may be formed from the first metallization layer 1922 .

According to various embodiments, each semiconductor circuit element of the plurality of semiconductor circuit elements 1702a, 1702b, 1702c may comprise or be formed of a diode structure or a transistor structure (also referred to as a transistor cell).

Optionally, the semiconductor device 1100 a may include a second metallization layer 1822 on the first side 102 b of the semiconductor region 102 . Each semiconductor circuit element of the plurality of semiconductor circuit elements 1702a, 1702b, 1702c may be electrically connected 1904 to the second metallization layer 1822 eg via the active dopant 108a of the semiconductor region 102 (eg via the doped layer 108l). At least one first contact pad 1706 may be formed from the second metallization layer 1822 .

According to various embodiments, each semiconductor circuit element of the plurality of semiconductor circuit elements 1702a, 1702b, 1702c (eg, power semiconductor circuit elements) may comprise or be formed of a vertical structure. A vertical structure may be understood as providing current flow from the second side 102 t of the semiconductor region 102 to the first side 102 b of the semiconductor region 102 and vice versa, for example perpendicular to the macroscopic surface plane 404 of the semiconductor region 102 .

According to various embodiments, each semiconductor circuit element of the plurality of semiconductor circuit elements 1702a, 1702b, 1702c (eg, power semiconductor circuit elements) may include at least one gate contact pad. At least one gate contact pad may be provided by (eg formed from) at least one of the first metallization layers 1922 (if present).

According to various embodiments, each semiconductor circuit element of the plurality of semiconductor circuit elements 1702a, 1702b, 1702c (eg, power semiconductor circuit elements) may include or be formed from a transistor (eg, a power transistor).

FIG. 11B shows a schematic cross-sectional or side view of a semiconductor device 1100 b according to various embodiments in a method according to various embodiments.

According to various embodiments, the semiconductor device 1100 b may include a sacrificial layer 1912 formed over the semiconductor region 102 , eg, before forming the radiation absorbing layer 114 and/or after disposing dopants in the semiconductor region 102 . Sacrificial layer 1912 may be processed to form mask 1812 .

Alternatively or additionally, sacrificial layer 1912 may facilitate removal of radiation absorbing layer 114 . In this case, the transparency (eg, transparency factor) of the sacrificial layer 1912 may be greater than the transparency (eg, transparency factor) of the semiconductor region 102 . Alternatively or additionally, the thermal conductivity of the sacrificial layer 1912 may be greater than the thermal conductivity of the semiconductor region 102 . The sacrificial layer 1912 may be removed along with the radiation absorbing layer 114 after activating the dopants (similar to a lift-off process).

Alternatively or additionally, sacrificial layer 1912 may include or be formed from an anti-reflective coating (eg, including at least one anti-reflective layer). The anti-reflective coating may be configured to reduce the reflectivity of the semiconductor region 102 , eg, the surface 104 of the semiconductor region 102 . In other words, the reflection coefficient of the anti-reflection coating may be smaller than the reflection coefficient of the semiconductor region 102 .

FIG. 11C shows a schematic cross-sectional or side view of a semiconductor device 1100 c according to various embodiments in a method according to various embodiments.

According to various embodiments, forming the radiation absorbing layer 114 may include forming at least two regions 1904a, 1904b (eg, segments 602a, 602b ) that are different from each other, eg, at least in their reflection (eg, for a given wavelength or range of wavelengths) The properties differ, the reflection properties describing for example the wavelength-dependent reflection coefficient (see Figures 5A and 5B). By way of example, the at least two regions 1904a, 1904b may comprise or be formed by the first region 1904a and the second region 1904b.

According to various embodiments, the first region 1904a of the radiation absorbing layer 114 and the second region 1904b of the radiation absorbing layer 114 may differ in at least one structural characteristic selected from the group consisting of: roughness (root mean square), (e.g., also single-walled or multi-walled) a carbon allotrope 712, the spatially averaged structural height 1101 (referring to the thickness 1101 of the corresponding regions 1904a, 1904b or the carbon allotrope 712 parallel to the macroscopic surface normal extension) and the density (eg, number per area) of carbon allotropes 712 .

According to various embodiments, the height 1101 of the at least one carbon allotrope may be in the range of about 0.1 μm to about 10 μm, in the range of about 0.1 μm to about 1 μm, for example about 0.5 μm.

The first region 1904a and the second region 1904b may be provided to tune the absorption of the radiation absorbing layer 114, eg, according to a predetermined pattern or adjustment. In other words, configuring the radiation absorbing layer 114 may include adjusting the spatially distributed reflectivity. This may enable adjustment of the spatially resolved energy transfer to the semiconductor region 102 , eg via the radiation absorbing layer 114 .

12A shows a schematic cross-sectional view (eg, see schematic cross-sectional view 2106 of FIG. 13 ) or a side view, eg, semiconductor circuit element 1702a, of a semiconductor device 1200a according to various embodiments in a method according to various embodiments. , 1702b, 1702c, such as a power semiconductor circuit element 1702.

The semiconductor device 1200a may include a doped layer 1081 formed on the first side 102b. The doped layer 1081 (in other words, the activated dopant) may include or be formed of the first doping type. The doped layer 108l may comprise or be formed by a collector region (doped region in the form of a collector region).

The semiconductor device 1200a may also include a first contact pad 1706 in the form of a collector contact pad 1706 (eg, a drain contact pad). The first contact pad 1706 may electrically contact the doped layer 108l. The first contact pad 1706 may include or be formed of a metallization layer. The first contact pad 1706 may cover more than half of the doped layer 1081 , substantially cover the doped layer 1081 (eg, greater than 80% of the doped layer 1081 ). The first contact pad 1706 may include or be formed from an opaque layer.

Furthermore, the semiconductor device 1200 a may include a first doped region 2006 . The first doped region 2006 may comprise or be formed by a base region. The first doped region 2006 may comprise (eg, have a dopant having) the same doping type as the doped layer 1081 (in other words, the dopant of the doped layer 1081), eg, the first doping type. The semiconductor device 1200a may further include a second contact pad 1708a in electrical contact with the first doped region 2006 . The second contact pad 1708a may include or be formed from an emitter contact pad 1708a (eg, a source contact pad 1708a ). The second contact pad 1708a may include or be formed of a metallization layer.

Furthermore, the semiconductor device 1200a may include a second doped region 2004 formed between the first doped region 2006 and the doped layer 108l. The second doped region 2004 may include or be formed of a drift region. The second doped region 2004 may include a different doping type (second doping type) from the doping layer 1081, for example, a dopant having the second doping type. The second doped region 2004 may include an epitaxially formed layer.

The semiconductor device 1200a may also include an additional second contact pad 1708b. The additional second contact pad 1708b may comprise or be formed by the gate contact pad 1708b. The further second contact pad 1708b may be formed electrically insulated from the second doped region 2004 , for example by an electrically insulating layer formed between the further second contact pad 1708b and the second doped region 2004 . The additional second contact pad 1708b may include or be formed of a metallization layer.

Additionally, the semiconductor device 1200 a may include a third doped region 2008 . The third doped region 2008 may include or be formed by an emitter region. The third doped region 2008 may include (eg, have a dopant of) a different doping type than the doped layer 1081, eg, a second doping type. The dopant concentration of the third doped region 2008 may be greater than the dopant concentration of the second doped region 2004 .

Optionally, the semiconductor device 1200a may include a fourth doped region 2002 between the second doped region 2004 and the doped layer 108l. The fourth doped region 2002 may include or be formed of a field stop region. The fourth doped region 2002 may include a dopant having a different doping type than the doped layer 1081. The fourth doped region 2002 may include a higher dopant concentration than the second doped region 2004 .

According to various embodiments, the first doping type may be an n-doping type and the second doping type may be a p-doping type. Alternatively, the first doping type may be a p-doping type and the second doping type may be an n-doping type.

Optionally, the doped layer 1081 may include or be formed by a plurality of first segments having a first doping type and a plurality of second segments having a second doping type. In other words, the plurality of first segments may comprise a different doping type than the doping type of the plurality of second segments. The segments of the first plurality of segments and the segments of the second plurality of segments may be arranged in an alternating sequence, eg adjacent to each other.

The semiconductor device 1200a, such as the semiconductor circuit element 1702, may include or be formed of a transistor structure, such as a planar transistor structure (providing vertical current flow). A transistor structure may include or be formed from multiple p-n junctions. A p-n junction may be formed by an interface of two doped regions having different doping types, for example an interface between at least one of: the first doped region 2006 and the second doped region 2004; the first doped region 2006 and the third doped region 2008; the second doped region 2004 and the doped layer 108l; the doped layer 108l and the fourth doped region 2002 (if present, eg in an IGBT).

According to various embodiments, the second doped region 2004 and the fourth doped region 2002 may include the same doping type. As mentioned above, the doped layer 1081 may differ from the second doped region 2004 and the fourth doped region 2002 in terms of doping type. In this case, the doped layer 108l may provide a backside emitter region (eg, for an IGBT). Alternatively, the doped layer 1081 may have the same doping type as the second doped region 2004 and the fourth doped region 2002 . In this case, the doped layer 1081 may provide a contact enhancement region (eg, for a vertical MOSFET).

According to various embodiments, the semiconductor device 1200a, eg, the semiconductor circuit element 1702, may include or be formed from an insulated gate bipolar transistor.

12B shows a schematic cross-sectional view (eg, schematic cross-sectional view 2106 as shown in FIG. Circuit elements 1702a, 1702b, 1702c, such as power semiconductor circuit elements 1702 .

The semiconductor device 1200b may include a doped layer 1081 formed on the first side 102b. The doped layer 1081 (in other words, the activated dopant) may include or be formed of the first doping type.

The semiconductor device 1200b may further include a first contact pad 1706 electrically contacting the doped layer 108l. The first contact pad 1706 may include or be formed by an electrode contact pad. The first contact pad 1706 may include or be formed of a metallization layer. The first contact pad 1706 may substantially cover the doped layer 1081 . The extension of the first doped region 2006 (for example, along the direction from the second side 102t to the first side 102b, in other words, the vertical direction) may be smaller than the extension of the second doped region 2004 (for example, in the direction from the second side 102t side 102t pointing in the direction of the first side 102b). Exemplarily, the first doped region 2006 may provide a thin doped region and/or the second doped region 2004 may provide a thick drift region. The first doped region 2006 may be electrically and/or physically connected to the second contact pad 1708 .

Furthermore, the semiconductor device 1200 b may include a first doped region 2006 . The first doped region 2006 may include or be formed by the first junction region. The first doped region 2006 may comprise a dopant having a different doping type than the doping layer 1081 (in other words, the dopant of the doping layer 1081 ), for example a second doping type. The semiconductor device 1200 b may further include a second contact pad 1708 in electrical contact with the first doped region 2006 . The second contact pad 1708 may include or be formed by an electrode contact pad. The second contact pad 1708a may include or be formed of a metallization layer. Furthermore, the semiconductor device 1200b may include a second doped region 2004 formed between the first doped region 2006 and the doped layer 108l. The second doped region 2004 may include or be formed by the second junction region. The second doped region 2004 may include the same doping type as the doping type of the doped layer 1081, for example, a dopant having the first doping type.

Optionally, the semiconductor device 1200b may include a third doped region 2002 between the second doped region 2004 and the doped layer 108l. The third doped region 2002 may include or be formed of a field stop region. The third doped region 2002 may include (eg, have a dopant having) the same doping type as the doping type of the doped layer 1081. The third doped region 2002 may include a higher dopant concentration than the second doped region 2004 .

The semiconductor device 1200b, for example a semiconductor circuit element 1702 such as a power semiconductor circuit element, may comprise or be formed of a diode structure, eg a planar diode structure (providing vertical current flow). The diode structure may comprise or be formed by a p-n junction, for example formed by the interface of two doped regions having different doping types, such as the interface between the first doped region 2006 and the second doped region 2004 .

Optionally, the doped layer 1081 may include or be formed by a plurality of first segments having a first doping type and a plurality of second segments having a second doping type. The segments of the first plurality of segments and the segments of the second plurality of segments may be arranged in an alternating order. In this case, the doped layer 1081 may be part of a reverse diode structure.

FIG. 13 shows a schematic top view (showing the top side of the semiconductor device 1300 ) of a semiconductor device 1300 according to various embodiments in a method according to various embodiments.

The device may include a first contact terminal 2708a and a second contact terminal 2708b. The first contact terminal 2708a may cover an active region of the semiconductor device 1300 where a plurality of semiconductor circuit elements 2106 (eg transistor structures or diode structures) may be disposed, as seen in the detailed (enlarged) top view 2104 .

The first contact terminal 2708a (eg, source contact terminal 2708a ) may be electrically connected to the second contact pad 1708a (eg, source contact pad 1708a ) of each semiconductor circuit element in the plurality of semiconductor circuit elements 2106 . The second contact terminal 2708b (eg, gate contact terminal 2708b ) may be electrically connected to a further second contact pad 1708b (eg, gate contact pad 1708b ) of each semiconductor circuit element of the plurality of semiconductor circuit elements 2106 . Therefore, a plurality of semiconductor circuit elements 2106 can be connected in parallel.

Each of the plurality of semiconductor circuit elements 2106 may be in the shape of a bar cell or a square cell, optionally including a trench structure for a gate terminal (see FIG. 15B ), as described below. For example, each of the plurality of semiconductor circuit elements 2106 may include or be formed from an insulated gate bipolar transistor (IGBT), such as a field stop IGBT (including a field stop region).

The device may include an edge termination structure 2102, which may be electrically isolated from the second contact terminal 2708b. The edge termination structure 2102 may be electrically connected from the first contact terminal 2708a.

14 shows a schematic cross-sectional view (eg, schematic cross-sectional view 2106v as shown in FIG. 13 ) of a semiconductor device 1400 similar to semiconductor device 1200a according to various embodiments in a method according to various embodiments, It shows the electric field distribution 2202 over the semiconductor region 102 . At least one first contact pad 1706 may be electrically connected to a third contact terminal 2710 (eg, collector terminal 2710 ).

The semiconductor device 1400 may include or be formed of a punch trough structure.

The additional second contact pad 1708b may be formed, for example, by an electrically insulating layer 2208 formed between the additional second contact pad 1708b and the second doped region 2004 and formed between the additional second contact pad 1708b and the second contact pad The electrically insulating layer 2208 between 1708a is electrically insulated from the second doped region 2004 .

15A, 15B show schematic cross-sectional views of semiconductor devices 1500a, 1500b according to various embodiments, respectively, in methods according to various embodiments (see, for example, schematic cross-sectional view 2106v of FIG. 13 ).

The semiconductor device 1500a may include or be formed from a non-punched trench structure. The semiconductor device 1500b may include or be formed of trenches and field stop structures.

The second doped region 2004 may be a portion of a substrate (eg, a semiconductor substrate) having a second doping type (eg, n-type doping type). The doped layer 108l may be formed in the substrate, eg by doping implantation. The doped layer 1081 may provide at least one of better adjustability, lower switching losses, higher switching robustness, and DC functionality of the semiconductor devices 1500a, 1500b. For example, the doping concentration of the doped layer 108l may define the voltage drop of the semiconductor device 1500a, 1500b in the conduction mode. Doped layer 108l may provide a backside emitter.

According to various embodiments, the semiconductor device 1500b may include a trench structure 2308 in which an additional second contact pad 1708b (eg, gate contact pad 1708b ) may extend. In other words, the further second contact pad 1708 b may extend into the second doped region 2004 , for example between the first doped region 2006 and the second doped region 2004 .

The fourth doped region 2002 may be formed in the substrate, eg by doping implantation. The fourth doped region 2002 may be formed between the doped layer 108 l and the second doped region 2004 . The fourth doped region 2002 may enable the thickness of the second doped region 2004 to be reduced (eg, include or be formed by a base region) without reducing the robustness of the semiconductor device 1500b. According to various embodiments, the robustness of the semiconductor device 1500b may be comparable to that of the semiconductor device 1500a. In addition, the fourth doped region 2002 can reduce the collector-emitter saturation voltage (VCEsat).

The first doped region 2006 may include or be formed of a highly doped semiconductor region having a first doping type (eg, p-doping type). The doped layer 1081 may comprise or be formed from a highly doped semiconductor region having the first doping type. The second doped region 2004 may comprise or be formed by a lowly doped semiconductor region having the second doping type. The third doped region 2008 and the fourth doped region 2002 may each comprise or be formed by a highly doped semiconductor region having the second doping type. A lowly doped region may include a lower doping concentration than a highly doped region.

16A , 16B and 16C respectively show schematic cross-sectional views (eg, schematic cross-sectional view 2106v shown in FIG. 13 ) of semiconductor devices according to various embodiments in methods according to various embodiments.

Figure 16A shows a semiconductor device 1600a having a diode structure, eg similar to semiconductor device 1200b. A second contact pad 1708 (eg, anode contact pad 1708 ) may be electrically connected to a first contact terminal 2708 (eg, anode contact terminal 2708 ). The first doped region 2006 may comprise or be formed by a highly doped semiconductor region having the first doping type. The doped layer 1081 may comprise or be formed from a highly doped semiconductor region having the second doping type. The second doped region 2004 may comprise or be formed by a lowly doped semiconductor region having the second doping type.

Figure 16B shows a semiconductor device 1600b having a transistor structure, eg similar to semiconductor device 1500b. The first doped region 2006 may include or be formed by a first highly doped semiconductor region 2006a having a first doping type and a second highly doped semiconductor region 2006b having a first doping type, wherein the first highly doped The dopant concentration of the semiconductor region 2006a may be higher than the dopant concentration of the second highly doped semiconductor region 2006b. The doped layer 108l may comprise or be formed of a highly doped semiconductor region having the first doping type. The second doped region 2004 may include or be formed of a lowly doped semiconductor region having the second doping type. The third doped region 2008 and the fourth doped region 2002 may each comprise or be formed by a highly doped semiconductor region having the second doping type.

FIG. 16C shows a semiconductor device 1600c having a transistor structure (eg, an inverted transistor structure), eg, similar to semiconductor device 1500b, in which the doped layer 108l includes layers disposed between two second segments 2404 (eg, a plurality of second segment ) between at least one first segment 2402 (eg, a plurality of first segments 2402). The first segment 2402 (eg, a plurality of first segments) may include or be formed from a highly doped semiconductor region having a second doping type (eg, a different doping type than the second doped region 2004 ). The two second segments 2404 (eg, a plurality of second segments) may include or be formed from a highly doped semiconductor region having a first doping type (eg, the same doping type as the second doped region 2004 ) . The segments of the first plurality of segments and the segments of the second plurality of segments may be arranged in an alternating sequence, eg adjacent to each other.

17A shows a schematic first cross-sectional view (e.g., parallel to the macroscopic surface normal, or a corresponding top view) of a semiconductor device 1700 according to various embodiments in a method according to various embodiments, while FIG. 17B The semiconductor device 1700 is shown in a schematic second cross-sectional view 1701 (or corresponding side view) perpendicular to the first cross-sectional view.

The semiconductor device may include or be formed from the semiconductor region 102 . The semiconductor region 102 may include a surface 102 and a first portion 102e adjacent to the surface 104 . The first portion 102e may include a dopant. For example, the first portion 102e may be a portion of the doped layer 108l.

Furthermore, the semiconductor region 102 may include a plurality of second portions 102h adjacent to the surface. Each of the plurality of second portions 102h may include a dopant. For example, the plurality of second portions 102h may be part of the doped layer 108l.

Each of the plurality of second portions 102h may be embedded within the first portion 102e. In other words, each of the plurality of second portions 102h may be at least partially surrounded by the first portion 102e (eg, excluding only the surface 104). The plurality of second portions 102h may be spaced apart (eg, disjoint) from each other. In other words, adjacent portions of the plurality of second portions 102h may be disposed away from each other.

According to various embodiments, the first portion 102e may include or be formed of a less activated dopant than each of the plurality of second portions 102h. The electrical conductivity of the first portion 102h may be less than the electrical conductivity of each of the plurality of second portions 102h (eg, about 75%, eg, about 50%, eg, about 25%). Illustratively, the plurality of second portions 102h may be in physical contact with the at least one carbon allotrope 712 of the radiation absorbing layer during irradiation. Accordingly, thermal energy may be transferred from the carbon allotrope 712 of the radiation absorbing layer into the semiconductor region 102 through the plurality of second portions 102h, resulting in a thermal energy between the plurality of second portions 102h and the first portion 102e during heating of the semiconductor region 102. The temperature difference (eg, the temperature of the plurality of second portions 102h may be greater than the temperature of the first portion 102e). Higher temperatures can lead to enhanced activity of dopants. Illustratively, the configuration (eg, structure, size, and arrangement) of the plurality of second portions 102h may be an identifying marker of the carbon allotrope 712 of the radiation absorbing layer.

In addition, preferred embodiments will be described below:

According to various embodiments, a method may include: disposing a dopant in a semiconductor region (e.g., through a surface of the semiconductor region); or over the entire semiconductor region) to form a radiation absorbing layer comprising or formed from at least one allotrope of carbon; and at least partially irradiating the radiation absorbing layer with electromagnetic radiation to at least partially The semiconductor region is heated to at least partially activate the dopant.

According to various embodiments of the present invention, a method may include: disposing a dopant in a semiconductor region on a first side thereof; forming a dopant on at least a portion of the semiconductor region on the first side of the semiconductor region a radiation absorbing layer; at least partially activating the dopant by at least partially irradiating the radiation absorbing layer with electromagnetic radiation to heat at least a portion of the semiconductor region on a first side of the semiconductor region; and A doped region is formed at the second side, on or/and in the semiconductor region, wherein the doped region may comprise or be formed of a different doping type than the dopant, to A power semiconductor circuit element is formed including dopants and doped regions.

According to various embodiments, the electromagnetic radiation may comprise or be formed from at least one discrete wavelength.

According to various embodiments, the electromagnetic radiation may comprise or be formed by laser radiation.

According to various embodiments, the electromagnetic radiation may comprise or be formed from pulsed electromagnetic radiation.

According to various embodiments, heating the semiconductor region may comprise or result from a non-thermal equilibrium heating process.

According to various embodiments, the electromagnetic radiation may comprise or be formed by non-thermally formed (in other words, non-thermally generated) electromagnetic radiation.

According to various embodiments, substantially only at least one of the surface of the semiconductor region or the side of the semiconductor region (eg on which the radiation absorbing layer is arranged) may be heated to eg the dopant activation temperature.

According to various embodiments, the temperature gradient in the semiconductor region may be formed by heating the semiconductor region.

According to various embodiments, a temperature gradient may be directed towards the radiation absorbing layer.

According to various embodiments, the semiconductor region may be heated, eg, above or equal to the dopant activation temperature, substantially only through the radiation absorbing layer.

According to various embodiments, the dopant activation temperature may be greater than about 400°C, such as at least about 600°C, such as at least about 800°C, such as at least about 900°C.

According to various embodiments, a temperature gradient of at least 200 K/μm may be formed in the semiconductor region by irradiating the radiation absorbing layer.

According to various embodiments, a temperature gradient may be directed towards the radiation absorbing layer.

According to various embodiments, the electromagnetic radiation may comprise or be formed by at least one of pulsed radiation, polarized radiation, at least one discrete wavelength radiation, and coherent radiation.

According to various embodiments, the radiation absorbing layer may be configured to substantially completely absorb electromagnetic radiation.

According to various embodiments, the non-thermal equilibrium heat treatment may include forming a temperature gradient in the semiconductor region.

According to various embodiments, substantially only the surface of the semiconductor region close to the radiation absorbing layer may be heated (eg at least within the heating depth).

According to various embodiments, the semiconductor region may be heated only by the radiation absorbing layer. In other words, the semiconductor region can be heated substantially only via the radiation absorbing layer. In other words again, energy for heating can enter the semiconductor region essentially only through the radiation absorbing layer.

According to various embodiments, the method may further comprise that on the side (of the semiconductor region) opposite to the dopant in the semiconductor region (in other words, on the first side or the corresponding surface of the semiconductor region through which the dopant is arranged The opposite second side, for example on the side opposite to the radiation absorbing layer or on the second side opposite to the first side of the semiconductor region from which the radiation absorbing layer is formed or removed) is on the semiconductor region or/and on the semiconductor region A doped region (eg, a doped semiconductor region) is formed in the region, wherein the doped region includes a different doping type than the dopant to form a power semiconductor circuit element including the dopant and the doped region.

According to various embodiments, the method may further comprise: forming a dopant on and/or in the semiconductor region on a side of the semiconductor region opposite to a surface of the semiconductor region through which dopants are arranged in the semiconductor region. A doped region, wherein the doped region includes a doping type other than the dopant to form a power semiconductor circuit element comprising the dopant and the doped region.

According to various embodiments, the doped region may include or be formed by at least one of a drift region, an emitter region, a junction region.

According to various embodiments, the doped region may be part of a diode structure, such as a vertical diode structure.

According to various embodiments, the doped region may be part of a transistor structure, such as a vertical transistor structure.

According to various embodiments, the method may further include forming an opaque layer over the semiconductor region after activating the dopant.

According to various embodiments, the opaque layer may be electrically conductive.

According to various embodiments, the opaque layer may include or be formed of metal.

According to various embodiments, the radiation absorbing layer may be configured such that a first reflective characteristic (eg for a certain wavelength or range of wavelengths) of a first region of the radiation absorbing layer is in contrast to a second reflective characteristic of a second region of the radiation absorbing layer. The characteristics are different. In other words, the radiation-absorbing layer can comprise or be formed by, for example, two regions whose reflection properties with respect to electromagnetic radiation differ from one another.

According to various embodiments, the radiation absorbing layer may be structured by at least one of: lift-off treatment, chemical treatment, electrochemical machining, and mechanical machining. In other words, constructing the radiation absorbing layer may comprise or be formed by at least one of the following types of treatment: lift-off treatment; chemical treatment; electrochemical treatment or mechanical treatment.

According to various embodiments, the radiation absorbing layer may be constructed by performing a lift-off process using a mask.

According to various embodiments, the radiation absorbing layer may include or be formed of a plurality of protrusions.

According to various embodiments, the radiation absorbing layer may comprise or be formed from at least one of the following types of allotropes of carbon: single-walled carbon nanotubes, multi-walled carbon nanotubes, graphite, fullerenes, and carbon nanofoams .

According to various embodiments, the radiation absorbing layer may include or be formed of a plurality of carbon nanotubes.

According to various embodiments, the plurality of carbon nanotubes may extend in a direction away from the semiconductor region, for example along a macroscopic surface normal of the semiconductor region.

According to various embodiments, the radiation absorbing layer may comprise at least one opening, eg a plurality of openings, partially exposing the semiconductor region.

According to various embodiments, the radiation absorbing layer may comprise a plurality of separate parts.

According to various embodiments, the radiation absorbing layer may be constructed using a mask for adjusting the spatial distribution of the reflectivity of the radiation absorbing layer.

According to various embodiments, the radiation absorbing layer may be heated to a temperature less than the evaporation temperature of the semiconductor region during activation of the dopant.

According to various embodiments, forming the radiation absorbing layer may include: forming a catalyst layer on the semiconductor region; and exposing the catalyst layer to a gaseous precursor comprising carbon, wherein the catalyst layer is configured to crack the gaseous precursor to form a radiation absorbent layer.

According to various embodiments, the gas precursor may include or be formed from organic molecules.

According to various embodiments, the catalyst layer may include or be formed of a catalyst metal.

According to various embodiments, the catalyst layer may include or be formed of a plurality of islands separated from each other.

According to various embodiments, the electromagnetic radiation may comprise or be formed by radiation ranging from ultraviolet radiation to infrared radiation. In other words, electromagnetic radiation may also include at least one of ultraviolet radiation, visible light radiation or infrared radiation.

According to various embodiments, the electromagnetic radiation may comprise or be formed by ultraviolet radiation. Alternatively or additionally, electromagnetic radiation may comprise or be formed by infrared radiation. Alternatively or additionally, electromagnetic radiation may comprise or be formed by visible radiation.

According to various embodiments, electromagnetic radiation may comprise or be formed from a discrete spectrum (radiation having one or more discrete wavelengths).

According to various embodiments, arranging the dopant may include implanting ions into the semiconductor region (eg, by irradiating the semiconductor region with ions), wherein the ions may include or be formed from the dopant (also referred to as dopant ions). In other words, arranging the dopant may include implanting dopant ions into the semiconductor region to form a layer including the dopant in the semiconductor region.

According to various embodiments, arranging the dopant may include forming a layer comprising the dopant on the semiconductor region, and activating thermally induced diffusion of the dopant from the layer into the semiconductor region.

According to various embodiments, arranging the dopant may include exposing the semiconductor region to a gas including the dopant.

According to various embodiments, activating the dopant may include increasing the conductivity of the doped layer of the semiconductor region.

According to various embodiments, activating the dopant may include at least partially incorporating the dopant into or formed from the lattice structure of the semiconductor region.

According to various embodiments, activating the dopant may include at least partially recrystallizing the semiconductor region (eg, at least a portion of the semiconductor region where the dopant is disposed) or formed therefrom.

According to various embodiments, the semiconductor region is at least partially (eg, at least a surface portion) heated to a temperature less than a melting temperature of the semiconductor region during activation of the dopant.

According to various embodiments, during activation of the dopant, the semiconductor region is at least partially (eg, at least a surface portion) heated to a temperature that is less than the melting temperature of the semiconductor region, such as to at least about 70% of the melting temperature of the semiconductor region. temperature, heated to a temperature of at least about 80% of the melting temperature of the semiconductor region, heated to a temperature of at least about 90% of the melting temperature of the semiconductor region.

According to various embodiments, the semiconductor region is at least partially (eg, at least a surface portion) heated to a temperature of at least about 900° C. (greater than about 900° C.), such as a temperature of at least about 1000° C., such as at least A temperature of about 1100°C, such as a temperature of at least about 1200°C, such as a temperature of at least about 1500°C, such as a temperature of at least about 2000°C.

According to various embodiments, during activation of the dopant, the semiconductor region is at least partially (eg, at least a surface portion) heated to a temperature greater than the melting temperature of the semiconductor region, such as a temperature greater than 110% of the melting temperature of the semiconductor region, such as A temperature greater than 120% of the melting temperature of the semiconductor region, a temperature greater than 140% of the melting temperature of the semiconductor region, a temperature greater than 160% of the melting temperature of the semiconductor region.

According to various embodiments, during activation of the dopant, a surface portion of the semiconductor region having a thickness greater than about 0.4 μm is heated, for example to this temperature.

According to various embodiments, irradiating the radiation absorbing layer may comprise using an optical resonator (for forming electromagnetic radiation), such as a laser source. In other words, electromagnetic radiation may comprise or be formed by laser light.

According to various embodiments, irradiating the radiation absorbing layer may comprise using a plasma source (for forming electromagnetic radiation), such as a gas discharge lamp such as a flash tube. The plasma source can be configured to emit electromagnetic radiation having at least one discrete wavelength or having a continuous spectrum.

According to various embodiments, illuminating the radiation absorbing layer may comprise using a powered solid state light source (for generating electromagnetic radiation), such as a powered light emitting diode (power LED).

According to various embodiments, the plasma source may be driven in a pulsed mode to form electromagnetic radiation.

According to various embodiments, irradiating the radiation absorbing layer may include scanning the radiation absorbing layer with electromagnetic radiation.

According to various embodiments, the electromagnetic radiation may include or be formed by wavelengths ranging from about 250 nm to about 600 nm.

According to various embodiments, the electromagnetic radiation may include or be formed by wavelengths ranging from about 500 nm to about 600 nm.

According to various embodiments, the electromagnetic radiation may include or be formed by wavelengths ranging from about 350 nm to about 500 nm.

According to various embodiments, the electromagnetic radiation may include or be formed by wavelengths ranging from about 250 nm to about 350 nm.

According to various embodiments, the electromagnetic radiation may comprise or be formed from pulsed electromagnetic radiation.

According to various embodiments, irradiating the radiation absorbing layer may include or be formed by laser thermal annealing.

According to various embodiments, the method may further include forming a metallization layer on the semiconductor region after activating the dopant.

According to various embodiments, the method may further include forming at least one transistor in electrical contact with the doped layer. Transistors may be formed on or in the semiconductor region.

According to various embodiments, the method may further comprise forming at least one gate contact pad in electrical contact with the doped layer, eg on the semiconductor region.

According to various embodiments, the method may further comprise forming a plurality of semiconductor circuit elements electrically connected in parallel with each other and in electrical contact with the doped layer.

According to various embodiments, the semiconductor region may include or be formed from a single crystal semiconductor material.

According to various embodiments, the semiconductor region may include or be formed of a polycrystalline semiconductor material.

According to various embodiments, activating the dopant may include forming a doped layer within the semiconductor region. In other words, during activation of the dopant, a doped layer may be formed within the semiconductor region.

According to various embodiments, the doped layer may include a dopant and a material of the semiconductor region.

According to various embodiments, the doped layer may comprise a dopant activated in the material of the semiconductor region.

According to various embodiments, the doped layer may be adjacent to the surface of the semiconductor region, for example adjacent to the surface of the semiconductor region.

According to various embodiments, the radiation absorbing layer may be configured to provide multiple scattering of electromagnetic radiation at or in the radiation absorbing layer.

According to various embodiments, the radiation absorbing layer may be configured to provide multiple scattering of electromagnetic radiation incident on the radiation absorbing layer.

According to various embodiments, the radiation absorbing layer has a reflectivity (reflection coefficient) for a range from about 250 nm to about 600 nm (eg, a range from about 250 nm to about 350 nm, a range from about 350 nm to 500 nm, and/or a range from about 500 nm to 600 nm) and/or less than about 0.5 for electromagnetic radiation incident in a direction along the macroscopic surface normal of the semiconductor region.

According to various embodiments, the reflectance of the radiation absorbing layer may be less than about 0.5, such as less than about 0.4, such as less than about 0.3, such as less than about 0.2, such as less than about 0.1, such as less than about 0.05.

According to various embodiments, a power semiconductor circuit element may comprise or be formed by at least one transistor structure.

According to various embodiments, a power semiconductor circuit element may include or be formed of a vertical structure.

According to various embodiments, the power semiconductor circuit element may comprise at least one gate terminal (in other words, one gate terminal or more terminals).

According to various embodiments, at least one gate terminal may be electrically connected to at least one gate contact pad.

According to various embodiments, the power semiconductor circuit element may comprise or be formed of a plurality of semiconductor circuit elements connected in parallel to each other.

According to various embodiments, a semiconductor region of a semiconductor device may include: a surface; a first portion adjacent to the surface; a plurality of second portions adjacent to the surface and embedded in the first portion, wherein the second portions are separated from each other (for example, arranged in do not intersect each other); wherein the first portion includes dopants that are activated to a different degree (eg, higher or lower) than each of the plurality of second portions such that the first portion and the plurality of second Each of the sections differs by at least the conductivity.

According to various embodiments, a semiconductor region of a semiconductor device may include: a surface; a first portion adjacent to the surface; a plurality of second portions adjacent to the surface and embedded in the first portion separated from each other (eg, arranged not to intersect each other) ; wherein the first portion includes a less activated dopant than each of the plurality of second portions such that the conductivity of the first portion is less than the conductivity of each of the plurality of second portions.

According to various embodiments, a radiation absorbing layer comprising at least one allotrope of carbon (e.g., comprising carbon nanotubes, graphite, carbon nanofoam and/or fullerenes or layers thereof), the wafer can then be irradiated to activate the dopant material in one or more regions of the wafer covered by the radiation absorbing layer (also known as "drive-in"). In one or more embodiments, one or more regions of the wafer constitute a portion of the entire frontside region or backside region of the wafer. In other words, one or more areas on the front or back side of the wafer may still be uncovered by the radiation absorbing layer. In one or more embodiments, irradiating the wafer may include irradiating the entire frontside or backside region of the wafer (either sequentially, such as by scanning such as laser scanning, or simultaneously, such as by exposing), the entire frontside or backside region of the wafer being illuminated. The side or backside regions include one or more regions of the wafer that are covered by the radiation absorbing layer and one or more regions of the wafer that are not covered by the radiation absorbing layer. In one or more embodiments, activation of the dopant material by irradiation occurs substantially only in one or more regions of the wafer covered by the radiation absorbing layer. In one or more embodiments, irradiating the wafer may include irradiating one or more regions of the radiation absorbing layer to activate one or more regions of the wafer covered by the one or more irradiated regions of the radiation absorbing layer. The dopant material in this area (also known as "propelling"). In one or more embodiments, one or more regions of the radiation absorbing layer form part of the overall radiation absorbing layer. In other words, one or more regions of the radiation absorbing layer (eg, on the front or back side of the wafer) may remain unirradiated.

While the invention has been particularly shown and described with reference to particular embodiments, it will be understood by those skilled in the art that the form and scope of the invention may be changed without departing from the spirit and scope of the invention as defined by the appended claims. Various changes were made to the details. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (22)

1. a kind of method, including：

Dopant is arranged in semiconductor regions；

The radiation absorption at least one allotrope for including carbon is formed at least a portion of the semiconductor regions Layer；

The radiation absorption layer is irradiated at least in part by using electromagnetic radiation to be at least partially heated the semiconductor region Domain, to activate the dopant at least in part.

2. according to the method described in claim 1,

Wherein, the electromagnetic radiation has at least one discrete wavelength.

3. according to the method described in claim 1,

Wherein, the semiconductor regions are heated substantially only through the radiation absorption layer.

4. according to the method described in claim 1,

Wherein, the electromagnetic radiation includes at least one in impulse radiation and coherent radiation.

5. according to the method described in claim 1,

Wherein, the semiconductor regions are heated including thermal nonequilibrium to heat.

6. according to the method described in claim 1,

Wherein, the radiation absorption layer is less than the semiconductor regions to the electromagnetism spoke to the reflection characteristic of the electromagnetic radiation The reflection characteristic penetrated.

7. according to the method described in claim 1, in addition to：

In the side relative with a surface of the semiconductor regions of the semiconductor regions, in the semiconductor regions Or/and doped region is formed on the semiconductor regions, wherein the dopant is the institute by the semiconductor regions Surface is stated to be disposed in the semiconductor regions, wherein, the doped region includes the doping different from the dopant Type is to form the power semiconductor circuits element including the dopant and the doped region.

8. according to the method described in claim 1,

Wherein, the radiation absorption layer includes two regions different from each other of the reflection characteristic to the electromagnetic radiation.

9. according to the method described in claim 1,

Wherein, the radiation absorption layer includes making the partially exposed at least one opening of the semiconductor regions.

10. according to the method described in claim 1,

Wherein, the radiation absorption layer includes at least one in the following allotrope of carbon：CNT, graphite, fowler Alkene, carbon nanometer foam.

11. according to the method described in claim 1, wherein, forming the radiation absorption layer includes：

Catalyst layer is formed on the semiconductor regions；And

The catalyst layer is set to be exposed to the gaseous precursors containing carbon, wherein the catalyst layer is configured to make before the gaseous state Body cracking is to form the radiation absorption layer using the carbon.

12. according to the method described in claim 1,

Wherein, space point of the radiation absorption layer including the use of the reflectivity Characteristics for adjusting the radiation absorption layer is formed The mask of cloth.

13. according to the method described in claim 1,

Wherein, during the dopant is activated, the radiation absorption layer is heated to the evaporation less than the semiconductor regions The temperature of temperature.

14. according to the method described in claim 1,

Wherein, irradiate the radiation absorption layer including the use of in optical resonator, Power Solid State light source and plasma source at least One.

15. according to the method described in claim 1, in addition to：

After the dopant is activated, at least one the collector contact pad made electrical contact with the semiconductor regions is formed.

16. according to the method described in claim 1,

Wherein, activate the dopant and be included in formation doped layer in the semiconductor regions.

17. according to the method described in claim 1,

Wherein, for scope from about 250nm to about 600nm electromagnetic radiation, the reflectivity of the radiation absorption layer is less than about 0.5。

18. according to the method described in claim 1, in addition to：

After the dopant is activated, the radiation absorption layer is removed by least one of etching and ashing mode.

19. a kind of method, including：

Dopant is arranged in the semiconductor regions in the first side of semiconductor regions；

In first side of the semiconductor regions, radiation absorption is formed at least a portion of the semiconductor regions Layer；And

Irradiate the radiation absorption layer at least in part by using electromagnetic radiation with heat the semiconductor regions described At least a portion of first side of semiconductor regions, to activate the dopant at least in part；And

In second side relative with first side of the semiconductor regions, in the semiconductor regions or/and described Doped region is formed on semiconductor regions, wherein, the doped region include the doping type different from the dopant with Formation includes the power semiconductor circuits element of the dopant and the doped region.

20. method according to claim 19,

Wherein, the power semiconductor circuits element includes at least one transistor arrangement.

21. method according to claim 19, wherein, the power semiconductor circuits element includes vertical stratification.

22. a kind of semiconductor devices, the semiconductor devices includes semiconductor regions, the semiconductor regions include：

Surface；

The Part I adjacent with the surface；

Multiple Part II in adjacent with the surface and embedded Part I, wherein the Part II divides each other From；

Wherein, with the multiple Part II it is each partly compared with, the Part I includes being activated in various degree Dopant so that the Part I and each part in the multiple Part II are different at least in terms of electrical conductivity.