CN107230630A - The preparation method of gallium nitride field effect transistor - Google Patents

Abstract

An embodiment of the present invention provides a method for manufacturing a gallium nitride field effect transistor. The method firstly manufactures an ohmic contact electrode and a gate of the transistor on the first region of the device, wherein the device includes a substrate and sequentially grown on a GaN buffer layer and an AlGaN barrier layer on the surface of the substrate; and then by depositing a first PETEOS oxide layer on the surface of the device, and etching the device on the second region of the device , until a part of the substrate is etched away to form a through hole, wherein the intersection of the second region and the first region is empty; finally by depositing a metal layer on the surface of the device, and The metal layer is etched to form the gallium nitride field effect transistor, which relieves the electric field between the drain and the gate, reduces the interconnection resistance and parasitic inductance of the source, and improves the gallium nitride field effect transistor. Transistor performance.

Description

GaN Field Effect Transistor Fabrication Method

technical field

Embodiments of the present invention relate to the technical field of manufacturing technology of semiconductor devices, in particular to a method for manufacturing GaN field effect transistors.

Background technique

With the increasing demand for power conversion circuits, power devices with characteristics such as low power consumption and high speed have become the focus of attention in this field. Gallium Nitride (GaN) is the third generation of wide bandgap semiconductor material, due to its large bandgap, high electron saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance and radiation resistance, it can be used in high voltage, high It has strong advantages in high frequency, high temperature, high power and anti-irradiation environmental conditions, and is considered to be the best material for short-wave optoelectronic devices and high-voltage, high-frequency and high-power devices. Moreover, with the deepening of research in recent years, GaN field effect transistors have become a research hotspot in power devices.

However, for the existing GaN field effect transistor manufacturing process, the GaN field effect transistor manufactured by it still has problems such as strong electric field strength between the drain and the gate, and high interconnection resistance and parasitic inductance of the source. , these problems seriously affect the performance of GaN FETs.

Contents of the invention

An embodiment of the present invention provides a method for manufacturing a GaN field effect transistor, so as to improve the performance of the GaN field effect transistor.

The fabrication method of the gallium nitride field effect transistor provided by the embodiment of the present invention includes:

Forming ohmic contact electrodes and gates of transistors on a first region of a device comprising a substrate and a GaN buffer layer and an aluminum gallium nitride (AlGaN) barrier layer sequentially grown on a surface of the substrate ;

depositing a first PETEOS oxide layer on the surface of the device;

Etching the device on the second region of the device until a part of the substrate is etched away to form a through hole, wherein the intersection of the second region and the first region is empty;

A metal layer is deposited on the surface of the device, and the metal layer is etched to form the gallium nitride field effect transistor.

The method for manufacturing a GaN field effect transistor provided by an embodiment of the present invention firstly manufactures an ohmic contact electrode and a gate electrode of the transistor on the first region of the device, wherein the device includes a substrate and sequentially grows on the substrate GaN buffer layer and AlGaN barrier layer on the bottom surface; then by depositing a first PETEOS oxide layer on the surface of the device, and etching the device on the second region of the device until the forming a through hole until part of the substrate is etched away, wherein the intersection of the second region and the first region is empty; finally by depositing a metal layer on the surface of the device, and Layer is etched to form the eGaN field effect transistor, which relieves the electric field between the drain and the gate, reduces the interconnection resistance and parasitic inductance of the source, and improves the performance of the eGaN field effect transistor .

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic flow chart of a method for manufacturing a gallium nitride field effect transistor provided by an embodiment of the present invention;

Fig. 2 is the execution method flowchart of step 101 in the method shown in Fig. 1;

Fig. 3 is the structural representation after depositing silicon nitride passivation layer and the second PETEOS oxide layer in the method shown in Fig. 2;

FIG. 4 is a schematic structural view after forming an ohmic contact hole in the method shown in FIG. 2;

Fig. 5 is the structural representation after forming the ohmic contact electrode in the method shown in Fig. 2;

FIG. 6 is a schematic structural diagram after forming a gate contact hole in the method shown in FIG. 2;

FIG. 7 is a schematic structural diagram after forming a gate in the method shown in FIG. 2;

FIG. 8 is a schematic structural diagram after forming a through hole in the method shown in FIG. 1;

FIG. 9 is a schematic structural diagram of a GaN field effect transistor formed after the method shown in FIG. 1 .

Reference signs:

1-substrate; 2-GaN buffer layer; 3-AlGaN barrier layer;

4-Silicon nitride passivation layer; 5-Second PETEOS oxide layer; 6-Ohm contact hole;

7-ohm contact electrode; 8-gate contact hole; 9-gate;

10 - first PETEOS oxide layer; 11 - through hole; 12 - metal layer.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The terms "comprising" and "having" and any variations thereof in the description and claims of the present invention are intended to cover a non-exclusive inclusion, for example, a process or method comprising a series of steps need not be limited to those explicitly listed Instead, the steps may include other steps not explicitly listed or inherent to the process or method.

FIG. 1 is a schematic flowchart of a method for manufacturing a GaN field effect transistor provided in an embodiment of the present invention. As shown in FIG. 1 , the method for manufacturing a GaN field effect transistor provided in this embodiment includes the following steps:

Step 101, fabricating the ohmic contact electrode and the gate of the transistor on the first region of the device, wherein the device includes a substrate 1 and a GaN buffer layer 2 and an AlGaN barrier layer 3 grown sequentially on the surface of the substrate .

Specifically, FIG. 2 is a flow chart of the execution method of step 101 in the method shown in FIG. 1. As shown in FIG. 2, this step can be implemented through the following execution methods:

Step 1011, using a deposition process to sequentially deposit a silicon nitride passivation layer 4 and a second PETEOS oxide layer 5 on the surface of the AlGaN barrier layer 3 of the device.

Fig. 3 is a schematic diagram of the structure after depositing a silicon nitride passivation layer and a second PETEOS oxide layer in the method shown in Fig. 2, wherein the structure shown in Fig. 3 can be obtained by the following method:

First, a silicon nitride passivation layer 4 is deposited on the surface of the AlGaN barrier layer 3 by a deposition process under low temperature conditions (temperature less than 300 degrees Celsius). After the silicon nitride layer 4 is obtained, a layer of plasma-enhanced tetraethyl orthosilicate (PETEOS) oxidation is deposited on the surface of the silicon nitride passivation layer 4, preferably by chemical vapor deposition. Layer 5 (ie the second PETEOS oxide layer).

Step 1012: Etching the second PETEOS oxide layer 5 and the silicon nitride passivation layer 4 in the third region by using an etching process to form an ohmic contact hole 6, wherein the third region contained in the first region.

Specifically, FIG. 4 is a schematic diagram of the structure after the ohmic contact hole is formed in the method shown in FIG. 2, wherein the structure shown in FIG. 4 can be obtained by the following method:

First, on the surface of the second PETEOS oxide layer 5, apply photoresist on the area outside the preset third area, and after applying the photoresist, under the blocking of the photoresist, the photoresist in the third area The second PETEOS oxide layer 5 is etched until the silicon nitride passivation layer 4 is exposed. After this etching, the second PETEOS oxide layer 5 forms an oxide layer opening (the first oxide layer) at the position in the third region. opening).

After the openings in the first oxide layer are formed, the silicon nitride passivation layer 4 in the openings in the first oxide layer is continuously etched by dry etching until the surface of the AlGaN barrier layer 3 is exposed. And the photoresist is removed after the etching is completed. After the etching, the ohmic contact hole 6 located in the third area is formed.

Step 1013, using a deposition process to deposit an ohmic electrode metal layer on the surface of the device.

In this embodiment, preferably, but not limited to, a magnetron sputtering coating process is used to deposit the ohmic electrode metal layer. Specifically, firstly, a layer of Ti metal layer is deposited on the surface of the device by magnetron sputtering coating process, and then a metal Al layer, a metal Ti layer and a metal TiN layer are sequentially deposited on the Ti metal layer to form an ohmic electrode. metal layer.

Further, in order to form a good ohmic contact electrode metal, before depositing the ohmic electrode metal layer in this embodiment, dilute hydrofluoric acid, standardized first-step cleaning and standardized second-step cleaning can be used sequentially to clean the AlGaN barrier layer. 3. The surface of the surface is cleaned. And after the ohmic electrode metal layer is obtained, the device is annealed for 30 seconds at a temperature of 840 degrees Celsius and a nitrogen atmosphere.

Step 1014 , using an etching process to etch the metal layer of the ohmic electrode to form the ohmic contact electrode 7 .

Specifically, FIG. 5 is a schematic diagram of the structure of the ohmic contact electrode formed in the method shown in FIG. 2, wherein, the manufacturing method of the structure shown in FIG. 5 can be obtained according to the existing ohmic contact electrode manufacturing process, and will not be repeated here.

Step 1015, using an etching process to etch the second PETEOS oxide layer 5, the silicon nitride passivation layer 4 and part of the AlGaN barrier layer in the fourth region to form a gate contact hole 8, wherein the fourth The area is included in the first area, and the intersection with the third area is empty.

Specifically, FIG. 6 is a schematic structural view of the gate contact hole formed in the method shown in FIG. 2. As shown in FIG. 6, the diameter of the gate contact hole 8 is smaller than the diameter of the fourth region, and the gate contact The holes 8 are located away from the positions of the ohmic contact electrodes.

It is worth noting that the etching process used to form the gate contact hole 8 in this step may be any of the existing etching processes, which will not be described in detail here.

Step 1016 , using a deposition process to deposit a gate metal layer on the surface of the device, and etching the gate metal layer through an etching process to form a gate 9 .

Specifically, FIG. 7 is a schematic diagram of the structure of the gate formed in the method shown in FIG. 2. As shown in FIG. 7, the gate metal formed in this step is not in contact with the ohmic electrode metal contact. And it is worth noting that the method for forming the gate 9 in this step is similar to the existing gate fabrication process, and will not be repeated here.

Step 102, depositing a first PETEOS oxide layer 10 on the surface of the device.

Step 103: Etching the device on the second region of the device until part of the substrate is etched away to form a through hole 11, wherein the second region and the first region The intersection is empty.

Specifically, FIG. 8 is a schematic diagram of the structure after the through hole is formed in the method shown in FIG. 1, and the manufacturing method of the structure shown in FIG. 8 is as follows:

Apply photoresist on the area of the device except the second area, and under the blocking of the photoresist, the first PETEOS oxide layer, the second PETEOS oxide layer 5, the silicon nitride passivation layer 4, and the AlGaN barrier layer 3 , the GaN buffer layer 2 and part of the substrate 1 are etched, and after the etching is completed, the photoresist is removed. Among them, the substrate 1 is preferably a silicon substrate.

Step 104 , depositing a metal layer on the surface of the device, and etching the metal layer to form the GaN field effect transistor.

Wherein, FIG. 9 is a schematic structural diagram of a GaN field effect transistor formed after the method shown in FIG. 1 . As shown in FIG. 9 , a metal layer 12 is first deposited on the surface of the device through a deposition process, and after the metal layer 12 is obtained, the metal layer 12 is etched to form a transistor as shown in FIG. 9 . Wherein, the process of depositing the metal layer 12 and the etching process are similar to the corresponding prior art, and will not be repeated here.

The method for manufacturing a GaN field effect transistor provided in this embodiment firstly manufactures an ohmic contact electrode and a gate of the transistor on the first region of the device, wherein the device includes a substrate and sequentially grows on the substrate GaN buffer layer and AlGaN barrier layer on the surface; then by depositing a first PETEOS oxide layer on the surface of the device, and etching the device on the second region of the device until the etching A through hole is formed until part of the substrate is removed, wherein the intersection of the second region and the first region is empty; finally, by depositing a metal layer on the surface of the device, and the metal layer Etching is performed to form the GaN field effect transistor, which eases the electric field between the drain and the gate, reduces the interconnection resistance and parasitic inductance of the source, and improves the performance of the GaN field effect transistor.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (7)

1. A method for manufacturing a gallium nitride field effect transistor, characterized in that, comprising: Fabricating an ohmic contact electrode and a gate of a transistor on a first region of a device, wherein the device includes a substrate and a GaN buffer layer and an AlGaN barrier layer grown sequentially on the surface of the substrate; depositing a first PETEOS oxide layer on the surface of the device; Etching the device on the second region of the device until a part of the substrate is etched away to form a through hole, wherein the intersection of the second region and the first region is empty; A metal layer is deposited on the surface of the device, and the metal layer is etched to form the gallium nitride field effect transistor. 2. The method according to claim 1, wherein said forming the ohmic contact electrode and gate of the transistor on the first region of the device comprises: Depositing a silicon nitride passivation layer and a second PETEOS oxide layer sequentially on the surface of the AlGaN barrier layer of the device by a deposition process; Using an etching process, the second PETEOS oxide layer and the silicon nitride passivation layer located in the third region are etched to form an ohmic contact hole, wherein the third region is included in the first area; Depositing an ohmic electrode metal layer on the surface of the device by using a deposition process; Etching the metal layer of the ohmic electrode by using an etching process to form an ohmic contact electrode; Etching the second PETEOS oxide layer, the silicon nitride passivation layer and part of the AlGaN barrier layer in the fourth region by an etching process to form a gate contact hole, the diameter of the gate contact hole is smaller than the first The diameter of four regions, and the position of the gate contact hole is far away from the position of the ohmic contact electrode, wherein the fourth region is included in the first region and intersects with the third region Is empty; A gate metal layer is deposited on the surface of the device by a deposition process, and the gate metal layer is etched by an etching process to form a gate. 3. The method according to claim 2, wherein the step of depositing a silicon nitride passivation layer and a second PETEOS oxide layer sequentially on the surface of the AlGaN barrier layer of the device using a deposition process comprises: Depositing the silicon nitride passivation layer on the surface of the AlGaN barrier layer under the condition that the temperature is less than 300 degrees Celsius; The second PETEOS oxide layer is deposited on the surface of the silicon nitride passivation layer by chemical vapor deposition. 4. The method according to claim 2, wherein the etching process is used to etch the second PETEOS oxide layer and the silicon nitride passivation layer in the third region to form Ohmic contacts, including: On the surface of the second PETEOS oxide layer, apply a layer of photoresist on the area other than the third area; Etching the second PETEOS oxide layer under the cover of the photoresist until the silicon nitride passivation layer is exposed, forming openings in the first oxide layer; The silicon nitride passivation layer in the opening of the first oxide layer is etched by a dry etching process until the surface of the AlGaN barrier layer is exposed, the ohmic contact hole is formed, and the photolithography is removed. glue. 5. method according to claim 2, is characterized in that, described adopting deposition process, before depositing ohmic electrode metal layer on the surface of described device, also comprises: cleaning the surface of the AlGaN barrier layer located in the ohmic contact hole. 6. The method according to claim 1, wherein said adopting a deposition process to deposit an ohmic electrode metal layer on the surface of said device comprises: A metal Ti layer, a metal Al layer, a metal Ti layer and a metal TiN layer are sequentially deposited on the surface of the device by using a magnetron sputtering coating process. 7. method according to claim 6, is characterized in that, after described employing magnetron sputtering film process to deposit metal Ti layer, metal Al layer, metal Ti layer and metal TiN layer on the surface of device successively, also include: Annealing was performed for 30 seconds at a temperature of 840 degrees Celsius and a nitrogen atmosphere.