CN107275216A - The forming method of fin formula field effect transistor - Google Patents

Abstract

A method for forming a fin field effect transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate is formed with more than two discrete fins arranged in parallel; forming an isolation layer on the surface of the semiconductor substrate, the The surface of the isolation layer is lower than the top surface of the fin and covers part of the sidewall of the fin; a dummy gate structure spanning one or more fins is formed on the surface of the isolation layer, and the dummy gate structure covers the side of the fin wall and top; carry out pocket ion implantation to the fin, and the pocket ion implantation direction is perpendicular to the length direction of the fin; form side walls on the side walls of the dummy gate structure, and then perform the dummy gate structure and the fins on both sides of the side wall Lightly doped ion implantation. The method can improve the shadow effect during pocket ion implantation.

Description

Method for forming fin field effect transistor

technical field

The invention relates to the technical field of semiconductors, in particular to a method for forming a fin field effect transistor.

Background technique

With the continuous development of semiconductor process technology, process nodes are gradually reduced, and gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance. Multi-gate devices have attracted widespread attention as a substitute for conventional devices.

A fin field effect transistor is a common multi-gate device, as shown in FIG. 1 , which is a schematic structural diagram of an existing fin field effect transistor. The fin field effect transistor includes a semiconductor substrate 10; several fins 20 on the substrate 10; an isolation layer 30 located on the surface of the semiconductor substrate 10, the surface of the isolation layer 30 is lower than the top surface of the fins 20 , and cover part of the sidewall of the fin portion 20; the gate structure located on the surface of the isolation layer 30 and across the fin portion 20, the gate structure includes a gate dielectric layer 41 and a gate located on the surface of the gate dielectric layer 41 Pole 42. A source and a drain are also formed in the fins 20 on both sides of the gate structure. In order to increase the channel region area of the FinFET, the gate structure of the FinFET generally spans a plurality of fins 20 .

In the prior art, in the process of forming the fin field effect transistor, pocket ion implantation is generally performed between the channel region under the gate structure and the source and drain regions, and the doping of the pocket ion implantation The ion type is opposite to the type of the fin field effect transistor to be formed, which can increase the punch-through voltage between the source and the drain of the fin field effect transistor to be formed, thereby suppressing the source-drain punch-through effect of the fin field effect transistor and improving Performance of FinFETs.

However, in the prior art, the effect of the pocket ion implantation on the fin field effect transistor is poor, and it is difficult for the dopant ions implanted in the pocket to enter the part close to the source region and the drain region close to the channel region, thereby affecting The improvement of the performance of the fin field effect transistor is limited, and it is necessary to further improve the process of the pocket ion implantation, so as to further improve the performance of the fin field effect transistor.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming a fin field effect transistor and improve the performance of the formed fin field effect transistor.

In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate is formed with more than two discrete fins arranged in parallel; An isolation layer is formed on the bottom surface, and the surface of the isolation layer is lower than the top surface of the fin and covers part of the sidewall of the fin; a dummy gate structure spanning one or more fins is formed on the surface of the isolation layer, and the dummy gate structure is formed on the surface of the isolation layer. The gate structure covers the sidewall and top of the fin; pocket ion implantation is performed on the fin, and the pocket ion implantation direction is perpendicular to the length direction of the fin; sidewalls are formed on the sidewall of the dummy gate structure, and then the dummy gate is The structure and the fins on both sides of the sidewall are implanted with lightly doped ions.

Optionally, the included angle between the pocket ion implantation direction and the normal of the semiconductor substrate is 0°-20°.

Optionally, the pocket ion implantation is divided into two parts, which are respectively performed on two sides of the fin.

Optionally, the ion type of the pocket ion implantation is opposite to the type of the fin field effect transistor to be formed.

Optionally, the pocket ion implantation forms a pocket doping region in the fin, and the pocket doping region is located in the middle of the fin along the width direction.

Optionally, the method further includes: performing supplementary pocket ion implantation on the fin after forming the side wall.

Optionally, the supplementary pocket ion implantation is performed before the lightly doped ion implantation.

Optionally, the supplementary pocket ion implantation is performed after the lightly doped ion implantation.

Optionally, the included angle between the projection of the supplementary pocket ion implantation direction on the substrate surface and the length direction of the fin is less than 90°.

Optionally, there is a hard mask layer on the top of the dummy gate structure.

Optionally, the method for forming the sidewall includes: forming a sidewall material layer covering the isolation layer, the fin, and the hard mask layer.

Optionally, the method further includes: etching the sidewall material layer to form a sidewall on the surface of the sidewall of the dummy gate structure.

Optionally, the material of the sidewall is silicon oxide or silicon nitride.

Optionally, the method further includes: etching the fins on both sides of the dummy gate structure to form a groove, and epitaxially forming a stress layer in the groove as a source and a drain.

Optionally, the material of the stress layer is SiGe, SiC or SiP.

Optionally, the stress layer is doped with N-type or P-type ions during the process of epitaxially forming the stress layer by using an in-situ doping process.

Optionally, the ion energy of the pocket ion implantation is 0KeV˜60KeV, and the dose is 1E13atom/cm ² ˜1E14atom/cm ² .

Optionally, removing the dummy gate structure to form a gate structure across the fin.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, after the dummy gate structure across the fin is formed, pocket ion implantation is performed, and then sidewalls are formed. The pocket ion implantation direction of the pocket ion implantation is parallel to the dummy gate structure and perpendicular to the fin, thereby avoiding the blocking effect on implanted ions in the length direction of the fin and improving the shadow effect of ion implantation. Moreover, since the sidewall of the dummy gate structure does not form a sidewall structure, performing pocket ion implantation parallel to the dummy gate structure can make the distance between the formed pocket doped region and the dummy gate structure very small, and the dummy gate structure can be formed by diffusion. There is a pocket doping region under the gate structure, and compared with the prior art, the ion implantation dose of the pocket can be reduced, thereby reducing the resistance of the formed fin field effect transistor.

Further, by adjusting the ion energy of the pocket ion implantation, the depth of implanted ions can be controlled, so that the pocket doping region is located in the middle of the fin along the width direction, so as to achieve the best anti-puncture effect.

Further, supplementary pocket ion implantation may also be performed after the sidewalls are formed. Since the ion type of the lightly doped ion implantation is opposite to the dopant ion type in the pocket doped region, the concentration of charged ions in the pocket doped region will decrease under the action of diffusion, so supplementary pocket ion implantation can compensate The decrease of the concentration of charged ions strengthens the effect of preventing source-drain punch-through of the pocket doping region.

Description of drawings

Fig. 1 is the structural representation of the fin field effect transistor of prior art of the present invention;

2 to 6 are structural schematic diagrams of the formation process of the fin field effect transistor according to the embodiment of the present invention.

detailed description

As mentioned in the background art, the existing pocket ion implantation for FinFETs has a relatively small ion dose into the source region and the drain region close to the channel region, which has limited improvement on the source-drain punch-through phenomenon.

The study found that due to the existing technology, several adjacent fins are usually formed on the semiconductor substrate, and the gate structure of the fin field effect transistor usually also spans multiple fins at the same time to improve the fin field effect. The area of the channel region of a transistor. Since the integration degree of existing semiconductor chips is relatively high, the distance between adjacent fins is relatively small. In order to improve the short channel effect, pocket ion implantation is usually performed after the sidewalls of the gate structure are formed. The pocket ion implantation needs to implant dopant ions into the fin between the channel region and the source-drain region. Therefore, the implantation direction of the pocket ion implantation is usually between the height direction of the fin and the length direction of the fin. There is a certain angle between them, so as to implant dopant ions into the position of the fin close to the gate structure.

Since the fin is a raised three-dimensional structure, it is necessary to perform ion implantation on both sides of the source electrode and the drain electrode respectively. In the process of performing ion implantation, the clip between the ion implantation direction and the height direction of the fin portion When the angle is fixed, the angle between the projection of the ion implantation direction on the semiconductor substrate and the length direction of the fin is generally 45° or 90°, so that when ion implantation is performed on different positions of the source and drain, It is convenient to adjust the injection angle.

When the included angle is 45°, since the distance between adjacent fins is relatively small, the adjacent fins will have a certain shielding effect on the implanted ion beam during pocket ion implantation, thus preventing the ion Implantation produces a shadow effect, resulting in a reduction in the number of pocket ions implanted near the channel region, which cannot effectively improve the source-drain penetration problem; and when the included angle is 90°, due to the obstruction of the sidewall, it is difficult to make the implantation Ions entering the channel region cannot effectively improve the source-drain punch-through effect.

In the embodiment of the present application, after forming the dummy gate structure across the fin, pocket ion implantation is performed, and the pocket ion implantation direction is perpendicular to the length direction of the fin, which can improve the shadow effect.

In this embodiment, the angle between the direction of pocket ion implantation and the normal of the semiconductor substrate is 0°-20°. In other embodiments of the present invention, The height and the distance between adjacent fins adjust the angle between the pocket ion implantation and the normal of the semiconductor substrate.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Please refer to FIG. 2 , a semiconductor substrate 100 is provided, and more than two separate and parallel fins 101 are formed on the surface of the semiconductor substrate 100; an isolation layer 200 is formed on the surface of the semiconductor substrate 100, and the isolation layer 200 The surface is lower than the top surface of the fins 101 and covers part of the sidewalls of the fins 101; a dummy gate structure 300 is formed on the surface of the isolation layer 200 across one or more fins 101, and the dummy gate structure 300 covers all The sidewall and top of the fin portion 101.

The material of the semiconductor substrate 100 includes silicon, germanium, silicon germanium, gallium arsenide and other semiconductor materials, and the semiconductor substrate 100 may be a bulk material or a composite structure such as silicon-on-insulator. Those skilled in the art can select the type of the semiconductor substrate 100 according to the semiconductor devices formed on the semiconductor substrate 100 , so the type of the semiconductor substrate 100 should not limit the protection scope of the present invention. In this embodiment, the material of the semiconductor substrate 100 is a single crystal silicon wafer.

The fin portion 101 may be formed on the semiconductor substrate 100 by etching the semiconductor substrate 100, or the fin portion 101 may be formed by etching the epitaxial layer after forming the epitaxial layer on the semiconductor substrate 100. .

In this embodiment, five fins 101 are formed on the semiconductor substrate 100 as an example. In other embodiments of the present invention, multiple fins that are separated and arranged in parallel may also be formed on the semiconductor substrate 100. 101.

The material of the isolation layer 200 can be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxycarbide, etc., and the isolation layer 200 serves as an isolation structure between adjacent fins 101, and the gate structure formed subsequently and the semiconductor The isolation structure between the substrates 100.

The method for forming the isolation layer 200 includes: depositing an isolation material on the semiconductor substrate 100, the isolation material covers the fins 101, and fills the grooves between the adjacent fins 101; The top of the fin 101 is used as a grinding stop layer, and the isolation material is planarized by a chemical mechanical polishing process to form an isolation material layer flush with the top surface of the fin 101; then, the isolation material layer is etched back , reducing the surface height of the isolation material layer to form an isolation layer 200 whose surface is lower than the top surface of the fin portion 101 .

After the fin portion 101 is formed, the fin portion 101 may be doped with ions, such as well doping, threshold adjustment doping, and the like.

The dummy gate structure 300 includes: a dummy gate dielectric layer (not shown in the figure) and a dummy gate located on the surface of the dummy gate dielectric layer. The material of the dummy gate dielectric layer is silicon oxide, and the material of the dummy gate is polysilicon. Subsequent gate-last process is adopted to form a metal gate structure to replace the dummy gate structure 300 .

The dummy gate structure also has a hard mask layer, including a silicon nitride layer 401 and a silicon oxide layer 402 on the surface of the silicon nitride layer 401 . Before forming the dummy gate structure 300, the surface of the fin may be oxidized to form an oxide layer as a dummy gate dielectric layer.

The method for forming the dummy gate structure 300 includes: forming a dummy gate dielectric material layer on the surface of the isolation layer 200, the dummy gate dielectric material layer covering the isolation layer 200 and the fin portion 101, and forming a dummy gate dielectric material layer on the surface of the dummy gate dielectric material A layer of dummy gate material is formed on the surface of the dummy gate material layer, and then a hard mask layer is formed on the surface of the dummy gate material layer. With the hard mask layer as a mask, the dummy gate material layer and the dummy gate dielectric material layer are Patterning is performed to form a dummy gate structure 300 across the fin portion 101 .

Referring to FIG. 3 , pocket ion implantation is performed on the fin 101 , the pocket ion implantation direction is perpendicular to the length direction of the fin 101 , and the included angle with the normal of the semiconductor substrate 100 is 0°. ~20°.

The fin 101 on one side of the dummy gate structure 300 is a source or drain region, the pocket ion implantation needs to form a pocket doped region between the channel region and the source or drain region of the transistor, and the The doping ion type of the pocket ion implantation is opposite to that of the fin field effect transistor to be formed, so as to increase the source-drain breakthrough voltage of the transistor.

The pocket ion implantation direction is parallel to the dummy gate structure 300 and perpendicular to the fin 101, thereby avoiding the blocking effect on the implanted ions in the length direction of the fin 101, and, since the side wall of the dummy gate structure 300 does not form a sidewall structure , performing pocket ion implantation parallel to the dummy gate structure 300 can make the distance between the formed pocket doped region and the dummy gate structure 300 very small, and the pocket doped region can be made under the dummy gate structure by diffusion, which is different from the present Compared with the prior art, the dose of the pocket ion implantation can be reduced, thereby reducing the resistance of the formed fin field effect transistor.

The ion energy of the pocket ion implantation is 0KeV-60KeV, and the dose is 1E13atom/cm ² -1E14atom/cm ² .

In this embodiment, the pocket ion implantation is divided into two times, and the two sides of the fin portion 101 are respectively implanted, so that the ion dose of a single implantation can be reduced, thereby reducing the implantation damage to the surface of one side of the fin portion 101. .

In other embodiments of the present invention, the aforementioned pocket ion implantation may also be performed only on one side of the fin portion 101 .

Please refer to FIG. 4 , which is a schematic cross-sectional view along the direction vertical to the fin portion 101 after the pocket doped region 102 is formed.

In this embodiment, by adjusting the ion energy of the pocket ion implantation, the depth of the implanted ions is controlled, so that the pocket doped region 102 is located in the middle of the fin portion 101 along the width direction, so as to achieve the best anti-puncture Effect.

In other embodiments of the present invention, the pocket doped region 102 may also be located in other positions.

Referring to FIG. 5 , spacers 500 are formed on the sidewalls of the dummy gate structure 300 (please refer to FIG. 4 ), and then lightly doped ion implantation is performed on the dummy gate structure and the fins 101 on both sides of the sidewalls 200 .

In this embodiment, the method for forming the sidewall 500 includes: forming a sidewall material layer covering the isolation layer 200 , the fin portion 101 , and the hard mask 401 , 402 . Part of the sidewall material layer located on the sidewall surface of the dummy gate structure 300 is used as the sidewall 500 , and in this embodiment, the sidewall material layer at other positions is reserved.

In other embodiments of the present invention, the sidewall material layer may also be etched, and only the sidewall material layer on the sidewall of the dummy gate structure 300 remains as the sidewall 500 .

The material of the sidewall 500 may be silicon oxide or silicon nitride. In this embodiment, the material of the sidewall 500 is silicon nitride. The sidewall material layer may be formed by using a chemical vapor deposition process.

After the spacer 500 is formed, the dummy gate structure 500 and the fins on both sides of the sidewall 500 on the dummy gate structure 500 and the fins on both sides of the sidewall 500 are implanted with lightly doped ions. The same type of fin field effect transistor is used to improve the short channel effect of the transistor.

By adjusting the thickness of the sidewall 500 , the distance between the formed lightly doped implanted region and the channel region under the dummy gate structure 500 can be limited.

Please refer to FIG. 6 , which is a schematic cross-sectional view along the length direction of the fin after performing the lightly doped ion implantation to form the lightly doped region 103 .

The pocket doped region 101 located between the lightly doped region 103 and the channel region can prevent the source-drain punchthrough problem.

In other embodiments of the present invention, after the sidewall 500 is formed, supplementary pocket ion implantation may be performed on the fin 101 according to actual conditions. The supplementary pocket ion implantation is performed before the lightly doped ion implantation, or after the lightly doped ion implantation.

Since the ion type of the lightly doped ion implantation is opposite to the dopant ion type in the pocket doped region 102, under the action of diffusion, the concentration of charged ions in the pocket doped region 102 will decrease, thereby performing supplementary pocket ion implantation It can make up for the decrease of the concentration of charged ions, and strengthen the effect of preventing source-drain punch-through of the pocket doping region.

The angle between the projection of the supplementary pocket ion implantation direction on the substrate surface and the length direction of the fin is less than 90°, so as to ensure that the ions implanted in the supplementary pocket ion implantation can enter the lightly doped region 103 and the dummy gate structure 300 between the channel regions below.

In this embodiment, the method for forming the FinFET further includes: etching the fins 101 on both sides of the dummy gate structure 300 to form a groove, and epitaxially forming a stress layer in the groove 101 as a source and drain.

The material of the stress layer can be SiGe, SiC or SiP, etc., if the fin field effect transistor to be formed is a P-type field effect transistor, the material of the stress layer can be SiGe, if the fin field effect transistor to be formed The fin field effect transistor is an N-type fin field effect transistor, and the material of the stress layer is SiP.

In the process of epitaxially forming the stress layer, an in-situ doping process can be used to carry out N-type or P-type ion doping to the stress layer, or perform intermediate doping ion implantation to the formed stress layer, so that the stress Layers are either N-type or P-type doped.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (18)

1. a kind of forming method of fin formula field effect transistor, it is characterised in that including：

Semiconductor substrate is provided, it is discrete and arranged in parallel that the semiconductor substrate surface is formed with two or more Fin；

In semiconductor substrate surface formation separation layer, the insulation surface is less than the top table of fin Face and the partial sidewall for covering fin；

The pseudo- grid structure of one or more fins, dummy gate structure are developed across in the insulation surface Cover fin side wall and top；

Pocket ion implanting, length of the pocket ion implanting direction perpendicular to fin are carried out to the fin Spend direction；

In pseudo- grid structure side wall formation side wall, then the fin of pseudo- grid structure and side wall both sides is gently mixed Heteroion injects.

2. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described Angle between the normal of pocket ion implanting direction and the Semiconductor substrate is 0 °~20 °.

3. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described Pocket ion implanting is divided into twice, and the both sides of fin are carried out respectively.

4. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described The ionic type of pocket ion implanting is opposite with the type of fin formula field effect transistor to be formed.

5. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described Pocket ion implanting forms pocket doped region in fin, the pocket doped region be located at fin along width Spend the centre position in direction.

6. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that also wrap Include：After side wall is formed, supplement pocket ion implanting is carried out to fin.

7. the forming method of fin formula field effect transistor according to claim 6, it is characterised in that described Supplement pocket ion implanting is carried out before ion implanting is lightly doped.

8. the forming method of fin formula field effect transistor according to claim 6, it is characterised in that described Supplement pocket ion implanting is carried out after ion implanting is lightly doped.

9. the forming method of the fin formula field effect transistor according to claim 7 or 8, it is characterised in that The direction of the supplement pocket ion implanting is between the projection of substrate surface and the length direction of fin Angle is less than 90 °.

10. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described Pseudo- grid structural top has hard mask layer.

11. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described The forming method of side wall includes：Form the spacer material layer of covering separation layer, fin, hard mask layer.

12. the forming method of fin formula field effect transistor according to claim 11, it is characterised in that also wrap Include：The spacer material layer is etched, the side wall for being located at pseudo- grid structure side wall surface is formed.

13. the forming method of fin formula field effect transistor according to claim 11, it is characterised in that described The material of side wall is silica or silicon nitride.

14. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that also wrap Include：The fin of the pseudo- grid structure both sides of etching, forms groove, stressor layers is epitaxially formed in the groove, It is used as source electrode and drain electrode.

15. the forming method of fin formula field effect transistor according to claim 14, it is characterised in that described The material of stressor layers is SiGe, SiC or SiP.

16. the forming method of fin formula field effect transistor according to claim 14, it is characterised in that use The stressor layers during stressor layers are epitaxially formed, are carried out N-type or P by doping process in situ Type ion doping.

17. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described The ion energy of pocket ion implanting is 0KeV~60KeV, and dosage is 1E13atom/cm²~1E14 atom/cm²。

18. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that also wrap Removal dummy gate structure is included, the grid structure of fin is developed across.