CN107272245A - A kind of preparation method of display base plate, display base plate and display device - Google Patents

Abstract

The present invention provides a method for manufacturing a display substrate, a display substrate and a display device. A source electrode, a drain electrode, an active layer, and a gate insulation layer are fabricated on the substrate substrate, and a gate electrode, a gate electrode, and a gate insulation layer are formed on the gate insulation layer. The first electrode, the passivation layer covering the gate and the first electrode, and the pixel electrode on the passivation layer, the gate and the first electrode are located on the same layer, and the orthographic projection of the first electrode on the base substrate and the pixel electrode are on the same layer. The orthographic projections on the base substrate overlap, so that there is no need to change the mask or add a mask in the process of manufacturing the display substrate, so that there is no gate insulating layer between the first electrode and the pixel electrode, and the distance is reduced, so that The storage capacitance between the first electrode and the pixel electrode can be significantly improved, which can effectively improve the picture flickering defect of the display device, and is beneficial to increase the aperture ratio of the pixel and the transmittance of the display screen.

Description

A method for manufacturing a display substrate, a display substrate, and a display device

technical field

The invention relates to the field of display technology, in particular to a method for manufacturing a display substrate, a display substrate and a display device.

Background technique

The demand for various display devices has increased with the rise of the global information society. Therefore, great efforts have been devoted to the research and development of various flat display devices such as liquid crystal display devices (LCD), plasma display devices (PDP), electroluminescent display devices (ELD), and vacuum fluorescent display devices (VFD). .

Due to its low power consumption, low cost, no radiation, and easy operation, liquid crystal display devices have increasingly entered people's lives and work, and are widely used in various fields, such as homes, public places, and offices. And personal electronic related products, etc. At present, liquid crystal display devices have developed from Twisted Nematic (TN) liquid crystal display devices (Twisted Nematic, TN) which are simple to manufacture, low in cost but small in viewing angle, to in-plane switching liquid crystal display devices (In-Plane Switching, IPS), multi-dimensional An electric field type liquid crystal display device (Advanced Super Dimension Switch, referred to as ADS), and a high aperture ratio HADS type liquid crystal display device proposed based on the ADS mode.

However, whether it is a TN-type liquid crystal display device, an ADS-type liquid crystal display device or other types of liquid crystal display devices, as the PPI of the display device becomes higher and higher, the pixels become smaller and smaller, and subsequently, the pixels in the display device The storage capacitance of the electrodes is also getting smaller and smaller, so it is more and more likely to cause defects such as screen flickering of the display device.

Contents of the invention

Embodiments of the present invention provide a method for manufacturing a display substrate, a display substrate, and a display device, so as to solve the problem that the display device tends to flicker due to low storage capacity.

An embodiment of the present invention provides a method for manufacturing a display substrate, the method comprising:

providing a base substrate;

forming a source electrode, a drain electrode, an active layer and a gate insulating layer on the base substrate;

forming a gate and a first electrode on the gate insulating layer, wherein the gate is correspondingly located above the active layer, and the first electrode is insulated from the gate and arranged at intervals;

A passivation layer covering the gate and the first electrode and a pixel electrode on the passivation layer are sequentially formed, and the orthographic projection of the first electrode on the base substrate is in line with the pixel electrode. The orthographic projections on the base substrate partially overlap.

An embodiment of the present invention also provides a display substrate, which includes a base substrate and a source electrode, a drain electrode, an active layer, a gate insulating layer, a gate electrode, a first electrode, A pixel electrode and a passivation layer, the source and the drain are arranged opposite to each other, and the two ends of the active layer are respectively overlapped on the sides of the source and the drain away from the base substrate, The gate insulating layer covers the source, the drain and the active layer, the gate and the first electrode are insulated and spaced apart and located on the gate insulating layer, the gate The pole is correspondingly located above the active layer, the passivation layer covers the gate, the first electrode and the gate insulating layer, the pixel electrode is located on the passivation layer, and the first electrode is located on the passivation layer. An orthographic projection of an electrode on the base substrate partially overlaps with an orthographic projection of the pixel electrode on the base substrate.

An embodiment of the present invention also provides a display device, the display device includes a display substrate, and the display substrate includes a base substrate and a source electrode, a drain electrode, an active layer, and a gate insulating layer on the base substrate. , a gate, a first electrode, a pixel electrode and a passivation layer, the source and the drain are arranged opposite to each other, and the two ends of the active layer are respectively connected to the source and the drain away from the On the side surface of the base substrate, the gate insulating layer covers the source, the drain and the active layer, the gate and the first electrode are insulated and spaced apart and located on the gate On the electrode insulating layer, the gate is correspondingly located above the active layer, the passivation layer covers the gate, the first electrode and the gate insulating layer, and the pixel electrode is located on the On the passivation layer, the orthographic projection of the first electrode on the base substrate partially overlaps the orthographic projection of the pixel electrode on the base substrate.

The method for fabricating a display substrate, the display substrate, and the display device provided by the embodiments of the present invention include forming a source electrode, a drain electrode, an active layer, and a gate insulating layer on the base substrate, and forming a gate electrode on the gate insulating layer. , the first electrode, the passivation layer covering the gate and the first electrode, and the pixel electrode on the passivation layer, the gate and the first electrode are located on the same layer, and the orthographic projection of the first electrode on the base substrate is the same as that of the pixel electrode The orthographic projections on the base substrate are partially overlapped, so that in the process of manufacturing the display substrate, there is no need to change the photomask or add a photomask, so that there is no gate insulating layer between the first electrode and the pixel electrode, and the distance is reduced , so that the storage capacitance between the first electrode and the pixel electrode can be significantly improved, effectively improving the flickering defect of the display device, and helping to increase the aperture ratio of the pixel and the transmittance of the display screen.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments of the present invention. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a perspective view of a display device provided by a preferred embodiment of the present invention;

Fig. 2 is a partial cross-sectional view of the display panel shown at II-II in Fig. 1;

Figure 3 is a partial plan view of the display substrate shown in Figure 2;

4 is a partial cross-sectional view of a display panel in a display device provided by another embodiment of the present invention;

FIG. 5 is a flow chart of the manufacturing method of the display substrate shown in FIG. 2;

6 to 9 are partial cross-sectional views during the manufacturing process of the display substrate shown in FIG. 2;

FIG. 10 is a partial cross-sectional view during the manufacturing process of the display substrate shown in FIG. 4 .

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Please refer to FIG. 1 . FIG. 1 is a perspective view of a display device provided by a preferred embodiment of the present invention. As shown in FIG. 1, the display device 100 includes a display panel 10 and a backlight module 20, and the display panel 10 and the backlight module 20 are stacked to form a display module of the display device 100 to realize The display function of the display device 100 . The display device 100 also includes a display area 101 and a peripheral area 102 surrounding the display area 101, the display area 101 is mainly used to realize the display output function of the display device 100, and the peripheral area 102 is mainly used for Lines etc.

Please refer to FIG. 2 at the same time. FIG. 2 is a partial cross-sectional view of the display panel shown at II-II in FIG. 1 . As shown in FIG. 2 , the display panel 10 further includes a display substrate 11, an opposite substrate 12 and a liquid crystal layer 13, the display substrate 11 is arranged opposite to the opposite substrate 12, and the liquid crystal layer 13 is sandwiched between the Between the display substrate 11 and the opposite substrate 12 . In this embodiment, the display substrate 11 is a thin film transistor array substrate, and the opposite substrate 12 is a color filter substrate.

The display substrate 11 includes a base substrate 110 , a source 111 , a drain 112 , an active layer 113 , a gate insulating layer 114 , a gate 115 , a first electrode 116 , a pixel electrode 117 and a passivation layer 118 . The source 111, the drain 112, the active layer 113, the gate insulating layer 114, the gate 115, the first electrode 116, the pixel electrode 117 and the passivation Layer 118 is located on the base substrate 110 .

The source electrode 111 and the drain electrode 112 are disposed opposite to each other, and the two ends of the active layer 113 are respectively overlapped with the opposite ends of the source electrode 111 and the drain electrode 112, and are overlapped with the source electrode 111 and the drain 112 are on the side away from the base substrate. Further, the display substrate 11 further includes a first ohmic contact layer 119a and a second ohmic contact layer 119b, the first ohmic contact layer 119a is stacked with the source electrode 111, and is located away from the source electrode 111. One side of the base substrate 110, the second ohmic contact layer 119b is stacked with the drain 112, and is located on the side of the drain 112 away from the base substrate 110, the active layer 113 The two ends of the first ohmic contact layer 119a and the second ohmic contact layer 119b are respectively located above the first ohmic contact layer 119a and the second ohmic contact layer 119b, and are respectively connected to the source through the first ohmic contact layer 119a and the second ohmic contact layer 119b. 111 and the drain 112 are overlapped.

The gate insulating layer 114 covers the source 111, the drain 112, the active layer 113, the first ohmic contact layer 119a and the second ohmic contact layer 119b, and the gate 115 And the first electrode 116 is located on the gate insulating layer 114 , the gate 115 and the first electrode 116 are insulated and spaced apart, and the gate 115 is correspondingly located above the active layer 113 .

The passivation layer 118 covers the gate 115, the first electrode 116 and the gate insulating layer 114, the pixel electrode 117 is located on the passivation layer 118, and the pixel electrode 117 passes through the gate in turn. The first through hole on the passivation layer 118, the second through hole on the gate insulating layer 114 and the third through hole on the first ohmic contact layer 119a are electrically connected to the source 111, so The orthographic projection of the pixel electrode 117 on the base substrate 110 partially overlaps the orthographic projection of the first electrode 116 on the base substrate 110, so that the pixel electrode 117 and the first electrode 116 A storage capacitor is formed between them. Wherein, the first through hole, the second through hole and the third through hole are located above the source electrode 111 and communicate with each other to expose the source electrode 111 .

Further, the display substrate 11 may also include a light blocking pattern 1110 and a protective layer 1111, the light blocking pattern 1110 and the protective layer 1111 are located on the base substrate 110, and the protective layer 1111 covers the blocking layer. The light pattern 1110 and the base substrate 110, the active layer 113 and the gate insulating layer 114 are located on the protective layer 1111, and the light blocking pattern 1110 is correspondingly located below the active layer 113, And the orthographic projection of the active layer 113 on the base substrate 110 is located within the area of the orthographic projection of the light blocking pattern 1110 on the base substrate 110 .

In this embodiment, the first electrode 116 is a light blocking strip. Please also refer to FIG. 3 , which is a partial plan view of the display substrate shown in FIG. 2 . As shown in FIG. 3 , the display substrate 11 is provided with data lines 14 , scanning lines 15 , common electrode lines 16 and light-shielding strips 17 , and the data lines 14 and the scanning lines 15 cross each other to form a pixel region 18 , the source electrode 111, the drain electrode 112, the active layer 113 (shown in FIG. 2 ), the gate insulating layer 114 (shown in FIG. 2 ) and the thin film composed of the gate electrode 115 The transistor and the pixel electrode 117 are located in the pixel region 18, and the drain 112 is electrically connected to the data line 14, the gate 115 is electrically connected to the scanning line 15, and the common electrode line 16 Arranged parallel to the scanning lines 15 , the common electrode lines 16 are electrically connected to the common electrodes of the display panel 10 .

The light blocking strip 17 is arranged parallel to the data line 14 on the display substrate 11, and the light blocking strip 17 is electrically connected to the common electrode line 16 on the display substrate 11, and the light blocking strip 17 The orthographic projection on the base substrate 110 partially overlaps the orthographic projection of the pixel electrode 117 on the base substrate 110, and the orthographic projection of the light blocking strip 17 on the base substrate 110 does not The portion that overlaps with the orthographic projection of the pixel electrode 117 on the base substrate 110 is located between the orthographic projection of the pixel electrode 117 on the base substrate and the data line 14 on the base substrate 110. between the orthographic projections on .

Although in this embodiment, the description is made by taking the first electrode as a light-blocking strip as an example, it is not limited thereto. Please refer to FIG. 4 at the same time. FIG. A partial cross-sectional view of the panel is shown in FIG. 4 . The difference between the embodiment shown in FIG. 4 and the embodiment shown in FIG. 2 is that the first electrode 116 can also be a common electrode of the display panel.

Please refer to FIGS. 5 to 9 at the same time. FIG. 5 is a flow chart of the manufacturing method of the display substrate shown in FIG. 2 , and FIGS. 6 to 9 are partial cross-sectional views during the manufacturing process of the display substrate shown in FIG. 2 . As shown in FIG. 5 to FIG. 9, the manufacturing method of the display substrate provided by the embodiment of the present invention includes:

Step 501 , providing a base substrate.

Wherein, the base substrate 110 can be a rigid inorganic material that is transparent (such as glass, quartz or the like) or opaque (such as a chip, ceramics or the like), or can be made of plastic, rubber, polyester or polyester. Flexible organic materials such as carbonate.

Step 502 , forming a source, a drain, an active layer and a gate insulating layer on the base substrate.

In this step, a metal layer can be formed on the base substrate 110, and the source electrode 111 and the drain electrode 112 oppositely arranged are obtained by patterning the metal layer, and then a semiconductor layer is formed on the base substrate 110. , and pattern the semiconductor layer through exposure, development, etching and other processes to obtain the active layer 113, the two ends of the active layer 113 are respectively connected to the opposite ends of the source electrode 111 and the drain electrode 112 connected, and overlapped on the side of the source 111 and the drain 112 away from the base substrate, and then a gate insulating layer 114 is formed on the base substrate 110, the gate insulating layer 114 covers the source 111 , the drain 112 and the active layer 113 , as shown in FIG. 7 .

Specifically, the source 111 , the drain 112 , the active layer 113 and the gate insulating layer 114 may be located on the protective layer 1111 , and the gate insulating layer 114 covers the source 111 , the drain 112, the active layer 113 and the protective layer 1111, the orthographic projection of the active layer 113 on the base substrate 110 is located in the orthographic projection area of the light blocking pattern 1110 on the base substrate 110 Inside.

Further, after forming the source electrode 111 and the drain electrode 112, and before forming the active layer 113, the method further includes:

Forming a first ohmic contact layer and a second ohmic contact layer on the base substrate, wherein the first ohmic contact layer is correspondingly located on the source, and the second ohmic contact layer is correspondingly located on the drain superior.

In this step, after forming a metal layer on the base substrate 110, a heavily doped semiconductor layer can be continuously formed on the metal layer, and then the heavily doped semiconductor layer and the metal layer are patterned processing to obtain the source electrode 111, the drain electrode 112, the first ohmic contact layer 119a and the second ohmic contact layer 119b, wherein the first ohmic contact layer 119a is located on the source electrode 111, and the second ohmic contact layer Layer 119b is located on the drain 112 as shown in FIG. 7 .

Specifically, after forming a metal layer and a heavily doped semiconductor layer on the base substrate 110, a first photoresist layer is formed on the heavily doped semiconductor layer, and the first photoresist layer is patterned through exposure and development processes. A photoresist layer to obtain the first mask layer, using the first mask layer, and etching the heavily doped semiconductor layer and metal layer by dry etching and wet etching to obtain the source 111 , the drain electrode 112 , the first ohmic contact layer 119 a and the second ohmic contact layer 119 b.

In this embodiment, the source electrode 111, the drain electrode 112, the first ohmic contact layer 119a and the The second ohmic contact layer 119b, but not limited thereto, in other embodiments, after forming the metal layer, patterning the metal layer to obtain the source electrode 111 and the drain electrode 112, and then forming The heavily doped semiconductor layer is patterned to obtain the first ohmic contact layer 119a and the second ohmic contact layer 119b.

Step 503 , forming a gate and a first electrode on the gate insulating layer, wherein the gate is correspondingly located above the active layer, and the first electrode is insulated from the gate and arranged at intervals.

In this step, after the gate insulating layer 114 is formed, a gate 115 and a first electrode 116 can be formed on the gate insulating layer 114, wherein the gate 115 is correspondingly located on the active layer 113 above, the first electrode 116 is insulated from the gate 115 and spaced apart, as shown in FIG. 8 .

In this embodiment, the first electrode 116 is a light blocking strip. Please also refer to FIG. 3 , the display substrate 11 is provided with data lines 14 , scan lines 15 , common electrode lines 16 and light-shielding strips 17 , and the data lines 14 and the scan lines 15 cross each other to form a pixel area 18 , the thin film transistor composed of the source 111 , the drain 112 , the active layer 113 , the gate insulating layer 114 and the gate 115 is located in the pixel region 18 , and the drain 112 is electrically connected to the data line 14, the gate 115 is electrically connected to the scanning line 15, the common electrode line 16 is arranged in parallel with the scanning line 15, and the common electrode line 16 is connected to the display panel 10 is electrically connected to the common electrode.

The light blocking strip 17 is arranged parallel to the data line 14 on the display substrate 11, and the light blocking strip 17 is electrically connected to the common electrode line 16 on the display substrate 11, and the light blocking strip 17 The orthographic projection on the base substrate 110 is located between the orthographic projection of the pixel electrode 117 on the base substrate and the orthographic projection of the data line 14 on the base substrate 110, and the The orthographic projection of the light blocking strip 17 on the base substrate 110 partially overlaps the orthographic projection of the pixel electrode 117 on the base substrate 110 .

Further, step 503 includes:

A first metal layer is formed on the gate insulating layer; the first metal layer is processed by a patterning process to obtain a gate and the first electrode, wherein the gate is correspondingly located on the above the active layer.

In this step, a first metal layer can be formed on the gate insulating layer 114, and a mask plate is used to pattern the first metal layer through a patterning process, so as to obtain The gate 115 and the first electrode 116 on the insulating layer 114, and make the gate 115 and the first electrode 116 insulated and spaced apart, and the gate 115 is correspondingly located above the active layer 113, as shown in Figure 8.

Specifically, after the gate insulating layer 114 is formed, a first metal layer is formed on the gate insulating layer 114, a second photoresist is formed on the first metal layer, and a second photoresist is formed on the first metal layer. The second photoresist layer is patterned in the process to obtain a second mask layer that can be used as a mask, and the second mask layer is used as a mask, and by wet etching, etc., using a patterning process, the The first metal layer is patterned to obtain a gate 115 and a first electrode 116 insulated from the gate 115 and spaced apart, wherein the gate 115 is correspondingly located above the active layer 113 .

Although in this implementation manner, the description is made by taking the first electrode as a light-shielding strip as an example, it is not limited thereto. In other implementation manners, the first electrode may also be a common electrode of the display panel.

When the first electrode 116 is a common electrode, step 503 includes:

Forming a second metal layer on the gate insulating layer and patterning the second metal layer to obtain a gate, wherein the gate is correspondingly located above the active layer; forming a transparent electrode layer covering the gate insulating layer and the gate; an electrode.

In this step, after the gate insulating layer 114 is formed, a second metal layer can be formed on the gate insulating layer 114, and a mask plate is used to pattern the second metal layer to obtain On the gate insulating layer 114, and corresponding to the gate 115 above the active layer 113, a layer of transparent electrode layer is formed on the gate insulating layer 114, so that the transparent electrode layer covers the gate electrode insulating layer 114 and the grid 115, and then pattern the transparent electrode layer to obtain the first electrode 116, the first electrode 116 is set opposite to the grid 115, and is located on the grid On the pole insulating layer 114 , as shown in FIG. 10 , FIG. 10 is a partial cross-sectional view during the fabrication process of the display substrate shown in FIG. 4 .

Step 504, sequentially forming a passivation layer covering the gate and the first electrode and a pixel electrode on the passivation layer, the orthographic projection of the first electrode on the base substrate and the Orthographic projections of the pixel electrodes on the base substrate partially overlap.

In this step, after forming the gate 115 and the first electrode 116, a passivation layer 118 can be formed on the gate insulating layer 114, and the passivation layer 118 covers the gate insulating layer 114 , the gate electrode 115 and the first electrode 116 , and then form the pixel electrode 117 on the passivation layer 118 on the passivation layer 118 to obtain the display substrate 11 as shown in FIG. 9 .

The pixel electrode 117 may sequentially pass through the first through hole on the passivation layer 118, the second through hole on the gate insulating layer 114, and the third through hole on the first ohmic contact layer 119a. The source electrode 111 is electrically connected, and the orthographic projection of the pixel electrode 117 on the base substrate 110 partially overlaps with the orthographic projection of the first electrode 116 on the base substrate 110, so that in the pixel A storage capacitor is formed between the electrode 117 and the first electrode 116 .

Optionally, before step 502, the method includes:

Form a layer of opaque material layer on the base substrate 110; pattern the opaque material layer to obtain a light-blocking pattern 1110, wherein the light-blocking pattern 1110 is correspondingly located on the active layer 113 below, and the orthographic projection of the active layer 113 on the base substrate 110 is located in the area of the orthographic projection of the light blocking pattern 1110 on the base substrate 110; 110 and the protective layer 1111 of the light blocking pattern 1110 .

In this step, after the base substrate 110 is provided, a layer of opaque material layer and a photoresist layer on the opaque material layer can be formed on the base substrate 110, and developed by an exposure machine, etc. process to form a photoresist mask, and use the obtained photoresist mask to pattern the light-impermeable material layer to obtain a light-shielding pattern 1110, so that the light-shielding pattern 1110 is correspondingly located on the Below the active layer 113, a protective layer 1111 can be laid next on the base substrate 110, so that the protective layer 1111 covers the base substrate 110 and the light blocking pattern 1110, as shown in FIG. 6 Show.

Wherein, the orthographic projection of the active layer 113 to be formed later on the base substrate 110 is located within the area of the orthographic projection of the light blocking pattern 1110 on the base substrate 110 .

Further, in other embodiments, in order to save the number and cost of photomasks, the photomasks used to form the light-shielding pattern and the photoresist mask can be the photomasks used to form the active layer and/or form the gate Similarly, the projection of the light blocking pattern formed in this way on the base substrate can coincide with the projection of the active layer and/or gate on the base substrate, and there is no need to add an additional mask during the manufacturing process.

The method for fabricating a display substrate, the display substrate, and the display device provided by the embodiments of the present invention include forming a source electrode, a drain electrode, an active layer, and a gate insulating layer on the base substrate, and forming a gate electrode on the gate insulating layer. , the first electrode, the passivation layer covering the gate and the first electrode, and the pixel electrode on the passivation layer, the gate and the first electrode are located on the same layer, and the orthographic projection of the first electrode on the base substrate is the same as that of the pixel electrode The orthographic projections on the base substrate are partially overlapped, so that in the process of manufacturing the display substrate, there is no need to change the photomask or add a photomask, so that there is no gate insulating layer between the first electrode and the pixel electrode, and the distance is reduced , so that the storage capacitance between the first electrode and the pixel electrode can be significantly improved, effectively improving the flickering defect of the display device, and helping to increase the aperture ratio of the pixel and the transmittance of the display screen.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. a kind of preparation method of display base plate, it is characterised in that methods described includes：

One underlay substrate is provided；

Source electrode, drain electrode, active layer and gate insulator are formed on the underlay substrate；

Grid and first electrode are formed on the gate insulator, wherein, the grid correspondence is positioned at the upper of the active layer Side, the first electrode and the gate insulator and interval setting；

Sequentially form the passivation layer and the pixel electrode on the passivation layer for covering the grid and the first electrode, institute State orthographic projection of the first electrode on the underlay substrate and orthographic projection part of the pixel electrode on the underlay substrate It is overlapping.

2. preparation method as claimed in claim 1, it is characterised in that grid and the first electricity are formed on the gate insulator The step of pole, including：

The first metal layer is formed on the gate insulator；

The first metal layer is handled using a patterning processes, to obtain grid and the first electrode, wherein, institute Grid correspondence is stated positioned at the top of the active layer.

3. preparation method as claimed in claim 2, it is characterised in that the first electrode is shield bars, the shield bars with Data wire on the display base plate is be arranged in parallel, and the shield bars are electrically connected with the public electrode of the display base plate, institute State orthographic projection of orthographic projection of the shield bars on the underlay substrate not with the pixel electrode on the underlay substrate overlapping Part, positioned at orthographic projection of the pixel electrode on the underlay substrate and the data wire on the underlay substrate Between orthographic projection.

4. preparation method as claimed in claim 1, it is characterised in that grid and the first electricity are formed on the gate insulator The step of pole, including：

Second metal layer is formed on the gate insulator and the second metal layer is patterned, to obtain grid, wherein, institute Grid correspondence is stated positioned at the top of the active layer；

A transparent electrode layer for covering the gate insulator and the grid is formed on the gate insulator；

The transparent electrode layer is patterned, to obtain being oppositely arranged with the grid, and the on the gate insulator One electrode.

5. preparation method as claimed in claim 4, it is characterised in that the first electrode is public electrode.

6. preparation method as claimed in claim 1, it is characterised in that source electrode is formed on the underlay substrate, drain electrode, active Before the step of layer and gate insulator, methods described includes：

One layer of light-proof material layer is formed on the underlay substrate；

The light-proof material layer is patterned, to obtain the pattern that is in the light, wherein, the pattern correspondence that is in the light is located at the active layer Lower section, and orthographic projection of the active layer on underlay substrate be located at be in the light pattern in the orthographic projection region on underlay substrate；

Laying covers the protective layer of the underlay substrate and the pattern that is in the light on the underlay substrate.

7. a kind of display base plate, it is characterised in that the display base plate includes underlay substrate and on the underlay substrate Source electrode, drain electrode, active layer, gate insulator, grid, first electrode, pixel electrode and passivation layer, the source electrode and the drain electrode It is oppositely arranged, the two ends of the active layer are overlapped in the side of the source electrode and the drain electrode away from the underlay substrate respectively On, the gate insulator covers the source electrode, the drain electrode and the active layer, the grid and first electrode insulation And be arranged at intervals and be located on the gate insulator, the grid correspondence is positioned at the top of the active layer, the passivation layer Cover the grid, the first electrode and the gate insulator, the pixel electrode is located on the passivation layer, described the Orthographic projection of orthographic projection of one electrode on the underlay substrate with the pixel electrode on the underlay substrate partly overlaps.

8. display base plate as claimed in claim 7, it is characterised in that the first electrode is shield bars, the shield bars with Data wire on the display base plate is be arranged in parallel, and the shield bars are electrically connected with the public electrode of the display base plate, institute Orthographic projection of the shield bars on the underlay substrate is stated positioned at orthographic projection and institute of the pixel electrode on the underlay substrate State between orthographic projection of the data wire on the underlay substrate.

9. display base plate as claimed in claim 7, it is characterised in that the first electrode is public electrode.

10. a kind of display device, it is characterised in that the display device includes display base plate as claimed in claim 8.