CN107331695A - A kind of N traps resistance and its generation method - Google Patents

Abstract

The present application provides an N-well resistor and a method for generating the same. The N-well resistor includes: a first polysilicon portion; a first N+ region located below the first polysilicon portion; and the first polysilicon portion. a second polysilicon portion spaced apart from the crystal silicon portion; a second N+ region located below the second polysilicon portion; an N well region; the first N+ region is located in one end of the N well region, and The N well region is connected; the second N+ region is located in the other end of the N well region and is connected to the N well region; the polysilicon part is a hollow structure inside, and is implanted through the hollow structure Impurities form the corresponding N+ regions. The N-well resistance can improve the precision of the N-well resistance value in the heat treatment process. The method for generating the N-well resistor can generate an N-well resistor that maintains a high-precision resistance value during heat treatment.

Description

A kind of N well resistance and its production method

technical field

The present application relates to the technical field of circuit design, in particular to an N-well resistor and a method for generating the same.

Background technique

N-well resistors are often used in analog circuit design. Figure 1 is a schematic structural diagram of an existing N-well resistor. As shown in Figure 1, the N-well resistor of the prior art includes an N-well region and an N+ region, wherein the region formed by the dotted line frame is the N-well region, and the thick solid line The frame is an N+ region, and N+ regions are respectively placed at both ends of the N well region. The N well region is generally lightly doped (low doping concentration), and N+ is heavily doped (high doping concentration). Generally, the length of the N well resistor is determined by the distance between the center points of the two N+ regions. In the integrated circuit process, the N-well area and the N+ area will change due to the heat treatment process in the subsequent process, so the defined length precision deviation is relatively large. Doping impurities in the N well region and the N+ region will be diffused during the subsequent heat treatment process. Diffusion is greatly affected by temperature changes. The inaccurate control of the heat treatment process leads to large deviations between chips in mass production.

The formula for the resistor value is:

Among them, R is the resistance value, ρ is the resistivity, L is the length of the resistor, and A is the cross-sectional area of the resistor.

It can be seen that the resistance value is proportional to the length of the resistance, and the inaccurate control of the heat treatment process leads to large deviations between chips in mass production, that is, the length accuracy of the N-well resistance is affected by temperature, thus directly affecting the accuracy of the N-well resistance value .

Contents of the invention

The embodiment of the present application proposes an N-well resistor and a method for generating the same, to overcome the inaccurate control of the existing heat treatment process that affects the accuracy of the N-well resistor value.

The embodiment of the present application provides an N-well resistor, including:

the first polysilicon division;

a first N+ region under the first polysilicon portion;

a second polysilicon portion spaced apart from the first polysilicon portion;

a second N+ region under the second polysilicon portion;

N well region;

The first N+ region is located in one end of the N well region and is connected to the N well region; the second N+ region is located in the other end of the N well region and is connected to the N well region ;

The polysilicon part is a hollow structure inside, and impurities are implanted through the hollow structure to form corresponding N+ regions.

The N well resistor provided by the embodiment of the present application includes a first polysilicon portion; a first N+ region located below the first polysilicon portion; a second polysilicon region separated from the first polysilicon portion a crystalline silicon part; a second N+ region located below the second polysilicon part; an N well region; the first N+ region is located in one end of the N well region and is connected to the N well region; The second N+ region is located in the other end of the N well region and is connected to the N well region; the polysilicon part is a hollow structure with a hollow inside, and the hollow structure includes an inner side and an outer side, and the hollow structure The inner side is used to control the formation of the N+ region; the distance from the center of the first N+ region to the corresponding N well region at the center of the second N+ region is the length of the N well resistor. , the formation of the N+ region can be accurately controlled based on the polysilicon portion, thereby precisely controlling the length of the N well resistance and improving the accuracy of the N well resistance value during the heat treatment process.

The embodiment of the present application also provides a method for generating the above-mentioned N-well resistor, including the following steps:

Forming an N well region;

forming a polysilicon portion, the polysilicon portion includes a first polysilicon portion and a second polysilicon portion, the first polysilicon portion and the second polysilicon portion are respectively located above the two ends of the N well region , the polysilicon portion is a hollow structure with a hollow interior, the hollow structure includes an inner side and an outer side, and the inner side of the hollow structure is used to control the formation of the N+ region;

Implanting high-concentration N-type impurities into the silicon body region through the hollow structure of the polysilicon portion to form the N+ region, the N+ region includes a first N+ region and a second N+ region, and the first N+ region and the second N+ region The two N+ regions are respectively located at two ends of the N well region and connected with the N well region.

The method for generating the above-mentioned N-well resistance provided by the embodiment of the present application includes forming an N-well region; forming a polysilicon portion, and the polysilicon portion includes a first polysilicon portion and a second polysilicon portion, and the first polysilicon portion part and the second polysilicon part are respectively located above the two ends of the N well region, the polysilicon part is a hollow structure with a hollow inside, the hollow structure includes an inner side and an outer side, and the inner side of the hollow structure is used to control Formation of the N+ region: implanting high-concentration N-type impurities into the silicon body region through the hollow structure of the polysilicon portion to form the N+ region, the N+ region includes a first N+ region and a second N+ region, the first N+ region An N+ region and the second N+ region are respectively located in the two ends of the N well region and connected to the N well region, and can generate an N well resistance that maintains a high precision resistance value during heat treatment.

Description of drawings

Specific embodiments of the application will be described below with reference to the accompanying drawings,

FIG. 1 is a schematic structural diagram of an existing N-well resistor, wherein the dotted-line frame is the N-well region, and the thick solid-line frame is the N+ region;

Figure 2 is a schematic structural diagram of the N well resistor provided by the embodiment of the present application, wherein (a) is a schematic top view structure diagram of the N well resistor provided by the embodiment of the present application, and (b) is a schematic diagram of the N well resistor provided by the embodiment of the present application Schematic diagram of the cross-sectional structure, in which the square filled area is the metal contact part, the oblique line filled area is the polysilicon part, the dotted line frame is the N well area, and the thick solid line frame is the N+ area;

FIG. 3 is a schematic flowchart of a method for generating an N-well resistor provided in an embodiment of the present application.

detailed description

In order to make the technical solutions and advantages of the present application clearer, the exemplary embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all implementations. Exhaustive list of examples. And in the case of no conflict, the embodiments in this specification and the features in the embodiments can be combined with each other.

In the process of implementing the present application, the inventors found that in the integrated circuit process of the N-well resistor, the N-well region and the N+ region will change due to the heat treatment process in the subsequent process, so the defined length accuracy has a large deviation. The doping impurities in the N well region and the N+ region will diffuse during the heat treatment in the subsequent process, and the temperature change has a great influence on the diffusion. The inaccurate control of the heat treatment process leads to large deviations between chips in mass production. The inaccurate control of the heat treatment process leads to large deviations between chips in mass production, that is, the length accuracy of the N-well resistance is affected by temperature, thus directly affecting the accuracy of the N-well resistance value.

In response to the above problems, an N-well resistor is provided in the embodiment of the present application. FIG. 2 is a schematic structural diagram of the N-well resistor provided in the embodiment of the present application, wherein (a) is a top view of the N-well resistor provided in the embodiment of the present application Schematic diagram of the structure, (b) is a schematic diagram of the cross-sectional structure of the N-well resistor provided by the embodiment of the present application. As shown in Figure 2, the N-well resistor can include:

the first polysilicon division;

a first N+ region under the first polysilicon portion;

a second polysilicon portion spaced apart from the first polysilicon portion;

a second N+ region under the second polysilicon portion;

N well region;

The first N+ region is located in one end of the N well region and is connected to the N well region; the second N+ region is located in the other end of the N well region and is connected to the N well region ;

The polysilicon part is a hollow structure inside, and impurities are implanted through the hollow structure to form corresponding N+ regions.

In specific implementation, the purpose of the N+ region is to provide an ohmic contact, that is, the contact resistance is small, and it is used to connect the N well resistor to other components of the chip. Only heavy doping can form a low-impedance ohmic contact. The function of the N well region is to form a certain resistance value.

A first polysilicon portion and a second polysilicon portion are respectively disposed above specific regions of the N-well region near the two ends (this specific region can be determined by those skilled in the art according to actual needs, and is not specifically limited here). The first N+ region and the second N+ region are respectively located in two ends of the N well region and connected with the N well region.

By adding a polysilicon portion to the existing N-well resistor structure, the shape and size of the N+ region can be precisely controlled, thereby precisely controlling the length of the N-well resistor.

In implementation, the resistance value of the N well resistor may be determined based on the first N+ region, the second N+ region and the N well region

In specific implementation, since the N+ region is heavily doped, its resistance is relatively small compared to the resistance of the N well region. Therefore, the resistance value of the N+ region can be approximately ignored when calculating the resistance value of the N well resistance. Those skilled in the art are calculating When determining the resistance value of the N well resistor, the resistance value of the N+ region may not be ignored. In practice, the width of the N well region in the cross-sectional structure of the N well resistor may be smaller than the width of the N+ region.

In specific implementation, the width of the N+ region (that is, the width of the inner region of the polysilicon) can be greater than the width of the N well region, and the width of the N well region of the existing N well resistor shown in Figure 1 is greater than the width of the N+ region, which will cause N+ The N well area outside the area changes with the change of the N+ area, and there is also a certain N well resistance in this part. The resistance value of this part of the N well resistance will change with the change of the N+ area, and it will also affect the entire N well resistance. resistance. And when the width of the N-well region in the cross-sectional structure of the N-well resistor can be smaller than the width of the N+ region, the resistance variation of the N-well resistor due to temperature changes can be effectively reduced.

In practice, the outer side of the silicon body region for forming the N+ region located under the polysilicon portion may be located between the inner side and the outer side of the hollow structure of the polysilicon portion.

In a specific implementation, the positional relationship between the outside of the silicon body region used to form the N+ region and the inside and outside of the polysilicon portion under the polysilicon portion will affect the precise control effect of the N+ active region. The thermal stability of the N-well resistor is critical.

Only when the outside of the silicon body region for forming the N+ region under the polysilicon portion is located between the inside and outside of the hollow structure of the polysilicon portion, can the N+ region be accurately controlled not to exceed the inner edge of the polysilicon portion.

In practice, the polysilicon portion may be polysilicon formed into a gate of a MOS transistor or polysilicon formed into a polysilicon resistor.

In the specific implementation, the polysilicon portion used to define the gate of the MOS transistor in the MOS integrated circuit process generally has the highest precision. On the one hand, the photolithography mask will use the highest precision mask plate, and on the other hand, the polysilicon portion is located above the silicon body. The size of its region is not determined by doping like the N well region or N+ region. Therefore, this layer is not affected by the heat treatment process, so its precision is higher.

The N-well resistor structure provided by the embodiment of the present application is shown in FIG. 2 , which includes an N-well region, an N+ region, and a polysilicon portion. There are multiple polysilicon parts in the process, for example, the first polysilicon part is the polysilicon that forms the gate of the MOS transistor, and the second polysilicon part is the polysilicon that forms the polysilicon resistor. The polysilicon portion in the embodiment of the present application preferably adopts the first polysilicon, because the first polysilicon generally has higher mask precision. Although the second polysilicon used to form the polysilicon resistor can also be used in the embodiment of the present application, which can reduce the influence of heat treatment, but generally the precision of the mask plate is low, which will also reduce the effect of the present invention.

To sum up, those skilled in the art can flexibly select the material of the polysilicon part according to specific application scenarios.

In practice, the thickness of the N well region in the cross-sectional structure of the N well resistor may be greater than the thickness of the N+ region.

In practice, the inside and outside of the polysilicon portion may be rectangular, and the outside of the N+ region may be rectangular.

In a specific implementation, the inside and outside of the polysilicon portion may be rectangular, and the outside of the N+ region may be rectangular. Similarly, the inside and outside of the polysilicon portion, and the outside of the N+ region can also be square, elliptical, etc., as long as the size of the N+ region and the length of the N well resistance can be precisely controlled. Here, it is only an exemplary description, and no specific limitation is made.

In implementation, the N-well resistor may further include: an oxide layer, and the oxide layer in the cross-sectional structure of the N-well resistor is located between the polysilicon portion and the N-well region.

In practice, the N well resistor may further include: a first metal contact portion and a second metal contact portion, the first N+ region is connected to the first metal contact portion, wherein the first metal contact portion passes through the The hollow structure of the first polysilicon portion;

The second N+ region is connected to the second metal contact portion, wherein the second metal contact portion passes through the hollow structure of the second polysilicon portion.

In specific implementation, considering that the N-well resistor is to be connected with other components and circuits, the N-well resistor may also include a metal contact portion of a hollow structure electrically connected to the N+ region and passing through the polysilicon portion.

The N well resistor provided by the embodiment of the present application includes a first polysilicon portion; a first N+ region located below the first polysilicon portion; a second polysilicon region separated from the first polysilicon portion a crystalline silicon part; a second N+ region located below the second polysilicon part; an N well region; the first N+ region is located in one end of the N well region and is connected to the N well region; The second N+ region is located at the other end of the N well region and is connected to the N well region; the polysilicon part is a hollow structure inside, and impurities are implanted through the hollow structure to form a corresponding N+ region, which can The formation of the N+ region is accurately controlled based on the polysilicon portion, thereby accurately controlling the length of the N well resistance and improving the precision of the N well resistance value during the heat treatment process.

Based on the concept of the same application, an embodiment of the present application also provides a method for generating an N-well resistor.

FIG. 3 is a schematic flow chart of a method for generating an N-well resistance provided in an embodiment of the present application. As shown in FIG. 3 , the method for generating the N-well resistance may include the following steps:

Step 301: forming an N well region;

Step 302: Form a polysilicon portion, the polysilicon portion includes a first polysilicon portion and a second polysilicon portion, the first polysilicon portion and the second polysilicon portion are respectively located in the N well region Above both ends, the polysilicon part is a hollow structure with a hollow interior, the hollow structure includes an inner side and an outer side, and the inner side of the hollow structure is used to control the formation of the N+ region;

Step 303: Implanting high-concentration N-type impurities into the silicon body region through the hollow structure of the polysilicon portion to form the N+ region, the N+ region includes a first N+ region and a second N+ region, and the first N+ region and the second N+ region are respectively located in two ends of the N well region and connected to the N well region.

In practice, forming the polysilicon part may specifically include:

Oxide layer and polysilicon layer are formed by oxidation and deposition;

Photolithography and etching the polysilicon layer and the oxide layer to form a polysilicon portion with a hollow structure on the polysilicon layer and the oxide layer.

In specific implementation, the N well region is generally formed first, the N well implantation region is etched out through the N well region mask, and then N-type impurities with a lower concentration than the N+ region are implanted into the N well implantation region to form the N well region.

After the N well region is formed, a polysilicon layer and an oxide layer are formed by oxidation and deposition, and then the polysilicon layer and the oxide layer are photolithographically etched away to form the polysilicon part of the required hollow structure. The polysilicon portion includes a first polysilicon portion and a second polysilicon portion respectively located above both ends of the N well region, the polysilicon portion is a hollow structure including an inner side and an outer side, and the inner side of the hollow structure is used for for controlling the formation of the N+ region.

Finally, the N+ implantation region is formed through the N+ mask plate, and high-concentration N-type impurities are implanted into the N+ implantation region through the hollow structure of the polysilicon part to form the required N+ region.

The polysilicon portion is formed before the N+ region is formed to ensure that the size of the N+ region is precisely controlled during the formation of the polysilicon in the N+ region, so as to generate an N well resistor that maintains a high-precision resistance value during heat treatment.

The method for generating the above-mentioned N-well resistance provided by the embodiment of the present application includes forming an N-well region; forming a polysilicon portion, and the polysilicon portion includes a first polysilicon portion and a second polysilicon portion, and the first polysilicon portion part and the second polysilicon part are respectively located above the two ends of the N well region, the polysilicon part is a hollow structure with a hollow inside, the hollow structure includes an inner side and an outer side, and the inner side of the hollow structure is used to control Formation of the N+ region: implanting high-concentration N-type impurities into the silicon body region through the hollow structure of the polysilicon portion to form the N+ region, the N+ region includes a first N+ region and a second N+ region, the The first N+ region and the second N+ region are respectively located in two ends of the N well region and connected to the N well region, and can generate an N well resistance that maintains a high precision resistance value during heat treatment.

Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims (10)

1. a kind of N traps resistance, it is characterised in that including：

First polysilicon portion；

The first N+ regions below the first polysilicon portion；

With the second polysilicon portion at the first polysilicon portion interval；

The 2nd N+ regions below the second polysilicon portion；

N well regions；The first N+ regions are located in one end of the N well regions, and are connected with the N well regions；The 2nd N+ areas Domain is located in the other end of the N well regions, and is connected with the N well regions；

The polysilicon portion is the hollow-core construction of inner hollow, and corresponding N+ areas are formed by the hollow-core construction implanted dopant Domain.

2. N traps resistance as claimed in claim 1, it is characterised in that the resistance of the N traps resistance is to be based on the first N+ areas What domain, the 2nd N+ regions and the N well regions were determined.

3. N traps resistance as claimed in claim 1, it is characterised in that the N traps in the cross-sectional structure of the N traps resistance The width in area is less than the width in the N+ regions.

4. N traps resistance as claimed in claim 1, it is characterised in that being used for below the polysilicon portion forms the N The outside in the Gui Ti areas in+region is located between the inner side and outer side of polysilicon portion hollow-core construction.

5. N traps resistance as claimed in claim 1, it is characterised in that the polysilicon portion is using the polycrystalline for generating metal-oxide-semiconductor grid Silicon or the polysilicon for generating polysilicon resistance.

6. N traps resistance as claimed in claim 1, it is characterised in that the N traps in the cross-sectional structure of the N traps resistance The thickness in area is more than the thickness in the N+ regions.

7. N traps resistance as claimed in claim 1, it is characterised in that also include：Oxide layer, the cross section knot of the N traps resistance The oxide layer in structure is located between the polysilicon portion and the N well regions.

8. N traps resistance as claimed in claim 1, it is characterised in that also include：First Metal contacts and the contact of the second metal Portion, the first N+ regions are connected with first Metal contacts, wherein, first Metal contacts pass through described first The hollow-core construction in polysilicon portion；

The 2nd N+ regions are connected with second Metal contacts, wherein second Metal contacts pass through described second The hollow-core construction in polysilicon portion.

9. the generation method of a kind of N trap resistance as described in claim 1-8, it is characterised in that comprise the following steps：

Form N well regions；

Polysilicon portion is formed, the polysilicon portion includes the first polysilicon portion and the second polysilicon portion, the first polysilicon portion With second polysilicon segment not Wei Yu the N well regions two ends top, the polysilicon portion be inner hollow hollow knot Structure, the hollow-core construction includes inner side and outer side, and the inner side of the hollow-core construction is used for the formation for controlling the N+ regions；

The N-type impurity of high concentration is injected to Gui Ti areas by the hollow-core construction in the polysilicon portion, the N+ regions are formed, it is described N+ regions include the first N+ regions and the 2nd N+ regions, and the first N+ regions and the 2nd N+ regions are located at the N respectively It is connected in the two ends of well region and with the N well regions.

10. the generation method of N traps resistance as claimed in claim 9, it is characterised in that form polysilicon portion, specifically include：

Oxide layer and polysilicon layer are formed by oxidation, deposit；

Photoetching, etch the polysilicon layer and the oxide layer to form hollow knot on the polysilicon layer and the oxide layer The polysilicon portion of structure.