CN107370351A - Charge discharging resisting circuit - Google Patents
Charge discharging resisting circuit Download PDFInfo
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- CN107370351A CN107370351A CN201610318329.1A CN201610318329A CN107370351A CN 107370351 A CN107370351 A CN 107370351A CN 201610318329 A CN201610318329 A CN 201610318329A CN 107370351 A CN107370351 A CN 107370351A
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- 238000007599 discharging Methods 0.000 title claims abstract description 38
- 238000001514 detection method Methods 0.000 claims abstract description 35
- 230000007423 decrease Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 12
- 230000005611 electricity Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/322—Means for rapidly discharging a capacitor of the converter for protecting electrical components or for preventing electrical shock
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of charge discharging resisting circuit, including：First vent unit, one first power end of connection, a second source end and a control signal, when control signal controls the first vent unit opening, the electric charge of the first power end is released to second source end, and the first vent unit has a first node；Second vent unit, the first power end and one the 3rd power end are connected, and be connected to first node；Voltage detection unit, is connected to first node, and for detecting the voltage of first node, when the voltage of first node drops to safety value, the second vent unit is opened, and the electric charge of the first power end is released to the 3rd power end.In the present invention, voltage detection unit causes the electric charge of the first power end to be released to release backward 3rd power end of a period of time of second source end, the first power end is controlled to second source end and the process of releasing of the 3rd power end, and voltage detection unit is closed over time, in the absence of quiescent dissipation.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of charge discharging resisting circuit.
Background technology
The characteristics of electrically erasable read-only memory (EPROM) is due to low-voltage and low-power dissipation as storage medium and
Widely use, for example, applying among radio-frequency recognition system (RFID) system.Worked based on EEPROM
Principle, it is necessary to be provided to EEPROM during the memory cell in EEPROM is wiped
High pressure, however, it is necessary to first enter line number to EEPROM before EEPROM is programmed or wiped
According to buffer operation, during data buffering operation, typically using normal operating voltage, therefore, EEPROM
Voltage must switch between erasing high pressure and operating voltage, in order to avoid affected by high data buffering operation,
In the prior art generally after erase process, erasing high voltage relief is fallen, is re-filled with operating voltage, such as will
Erasing high pressure is directly released to operating voltage end.However, due to the particularity of RFID power supplys, power supply voltage stabilizing electricity
Hold and only have 1nf even more small, in the case that EEPROM capacity is increasing, released after having wiped
Electric charge to operating voltage is also more.Therefore operating voltage may be caused too high and puncture transistor.
The content of the invention
It is an object of the present invention to provide a kind of charge discharging resisting circuit, solves erasing high pressure in the prior art and lets out
Let off the uncontrollable technical problem of journey.
In order to solve the above technical problems, the present invention provides a kind of charge discharging resisting circuit, including：
First vent unit, one first power end of connection, a second source end and a control signal are described
When control signal controls the first vent unit opening, the electric charge of first power end is electric to described second
Source is released, and first vent unit has a first node；
Second vent unit, first power end and one the 3rd power end are connected, and be connected to described first
Node；
Voltage detection unit, the first node is connected to, for detecting the voltage of the first node, when
When the voltage of the first node drops to safety value, second vent unit is opened, first power supply
The electric charge at end is released to the 3rd power end.
Optionally, first vent unit includes：
The first transistor, source electrode connect first power end, and drain electrode connects the first node, and grid connects
Connect the voltage detection unit；
Second transistor, drain electrode connect the first node, and grid connects the 3rd power end；
First phase inverter, input connect the control signal, and output end connects the source of the second transistor
Pole.
Optionally, first phase inverter includes third transistor and the 4th transistor, the third transistor
Source electrode connect the 3rd power end, drain electrode connects the source electrode of the second transistor, described in grid connection
Control signal, the source electrode of the 4th transistor connect the second source end, and drain electrode connection described second is brilliant
The source electrode of body pipe, grid connect the control signal.
Optionally, first vent unit also includes first resistor, and the first resistor is connected to described
Between the drain electrode of one transistor and the drain electrode of the second transistor.
Optionally, the first transistor is PMOS transistor, and the second transistor is NMOS crystal
Pipe.
Optionally, second vent unit includes the 5th transistor, the source electrode connection of the 5th transistor
First power end, drain electrode connect the 3rd power end, and grid is connected to the first node.
Optionally, to be connected with second in turn between the grid of the first node and the 5th transistor anti-phase
Device and the 3rd phase inverter.
Optionally, the 5th transistor is PMOS transistor.
Optionally, the voltage detection unit includes：
6th transistor, source electrode connect the 3rd power end, and drain electrode connects first vent unit, grid
Pole is connected to section point；
7th transistor, source electrode connect the 3rd power end, and drain electrode connects the section point, and grid connects
It is connected to the first node；
Second resistance, it is connected between drain electrode and the section point of the 6th transistor；
8th transistor, drain electrode connect the section point, and grid connects the control signal；
9th transistor, source electrode connect the second source end, and drain electrode connects the drain electrode of the 8th transistor,
Grid is connected to the first node.
Optionally, the 6th transistor and the 7th transistor are PMOS transistor, and the described 8th is brilliant
Body pipe and the 9th transistor are nmos pass transistor.
Optionally, when the control signal rises to high potential, the 8th transistor is opened, the electricity
Detecting voltage is pressed to open, the current potential of the 6th transistor declines, and first vent unit is opened, described
The electric charge of first power end is released to the second source end, and the current potential of the first node declines, and declines
During to the safety value, second leadage circuit is opened, and the electric charge of first power end is to the described 3rd
Power end is released, and the current potential of the first node drops to low potential, and the 9th transistor is closed, described
Voltage detection unit is closed.
Optionally, the charge discharging resisting circuit also includes the 4th power end, the 4th power end and described the
The tenth transistor is connected between one power supply, the source electrode of the tenth transistor connects the 4th power end, leakage
Pole connects first power end, and grid connects the 3rd power end.
Optionally, the charge discharging resisting circuit also includes the 11st transistor, and source electrode connects the first node,
Drain electrode connects the 4th power end, and grid connects the 3rd power end.
In the charge discharging resisting circuit of the present invention, including the first vent unit, the second vent unit and voltage detection
Unit, control signal cause voltage detection unit to open, and the first vent unit are opened, the first power end
Electric charge second source end is released to by the first vent unit.The current potential of first node is with the first power end
Release and decline, when dropping to safety value so that the second vent unit open, now, the first power end
Electric charge by the second vent unit to the 3rd power end, also, voltage detection unit is accordingly turned off.This hair
In bright, it is for a period of time backward that voltage detection unit make it that the electric charge of the first power end is released to second source end
3rd power end is released, so as to control the first power end to second source end and the process of releasing of the 3rd power end,
Also, voltage detection unit is closed over time, so as to which quiescent dissipation be not present.
Brief description of the drawings
Fig. 1 is the schematic diagram of charge discharging resisting circuit of the prior art；
Fig. 2 is the analogous diagram of charge discharging resisting process of the prior art；
Fig. 3 is the schematic diagram of the charge discharging resisting circuit in one embodiment of the invention；
Fig. 4 is the analogous diagram of the charge discharging resisting process in one embodiment of the invention.
Embodiment
In order to solve the problems, such as to wipe high voltage relief in the prior art, inventor is studied, can also first by
Wipe high voltage relief and arrive ground terminal, through after a period of time, then high voltage relief will be wiped to operating voltage end.Ginseng
Examining shown in Fig. 1, power end VPP provides erasing high pressure in erase process, after erasing operation is completed,
Power end VPP charge discharging resisting is fallen, its course of work is with reference to shown in figure 2, when control terminal DISC's
When current potential VDISC rises to high potential, transistor N2 is opened so that power end VPP voltage is along crystal
Pipe P2, transistor N1 and transistor N2 are released to ground terminal VSS.As power end VPP releases one
Partial charge, power end VPP voltage declines, also, power end VPUMP voltage declines simultaneously,
So that transistor P1 is opened, power end VPP electric charge is then released on operating voltage VDD.Due to power supply
The process that end VPP is released to operating voltage VDD is uncontrollable so that power end VPP VSS on the ground
Discharge time process, operating voltage VDD voltage is too small, less than the operating voltage of needs,
In order to solve the above-mentioned technical problem, inventor is by further research, it is proposed that technology of the invention
Scheme, in charge discharging resisting circuit provided by the invention, including the first vent unit, the second vent unit and electricity
Probe unit is pressed, control signal causes voltage detection unit to open, and the first vent unit is opened, first
The electric charge of power end is released to second source end by the first vent unit.The current potential of first node is with first
Releasing for power end and decline, when dropping to safety value so that the second vent unit open, now, first
The electric charge of power end is by the second vent unit to the 3rd power end, also, voltage detection unit is accordingly turned off.
In the present invention, voltage detection unit causes the electric charge of the first power end to be released a period of time to second source end
Backward 3rd power end is released, so as to control the first power end releasing to second source end and the 3rd power end
Process, also, voltage detection unit is closed over time, so as to which quiescent dissipation be not present.
The charge discharging resisting circuit of the present invention is described in detail below in conjunction with Fig. 3~Fig. 4, Fig. 3 is electric charge
The schematic diagram of leadage circuit, Fig. 4 are the simulation result figure of charge discharging resisting process.
With reference to shown in figure 3, charge discharging resisting circuit of the invention includes the first vent unit 10, second released list
Member 30 and voltage detection unit 20, control signal DISC cause voltage detection unit 20 to open, and voltage is visited
Surveying after unit 20 is opened causes the first vent unit 10 to open, and the first power end VPP electric charge passes through first
Vent unit 10 is released to second source end VSS.First node S1 current potential is with the first power end VPP
Release and decline, when dropping to safety value so that the second vent unit 30 is opened, the present invention in safety value
Refer to the safe voltage of the second vent unit 30.Now, the first power end VPP electric charge is let out by second
Unit 30 is put to the 3rd power end VDD, also, voltage detection unit 20 is accordingly turned off.
With continued reference to shown in Fig. 3, in the present embodiment, the first vent unit 10 connect the first power end VPP,
Second source end VSS and control signal DISC.Specifically, first vent unit 10 includes：
The first transistor P1, the first transistor P1 source electrode connect the first power end VPP, and drain electrode connects
Meet the first node S1, grid connects the voltage detection unit 20, and in the present embodiment, described first is brilliant
Body pipe P1 is PMOS transistor；
Second transistor P2, second transistor P2 drain electrode connect the first node S1, grid connection institute
State the 3rd power end VDD, substrate connects the second source end VSS, and in the present embodiment, described second is brilliant
Body pipe P2 is nmos pass transistor；
First phase inverter 11, the input of the first phase inverter 11 connect the control signal DISC, output end
Connect the source electrode of the second transistor P2.First phase inverter 11 includes third transistor P3 and the 4th
Transistor P4, the third transistor P3 source electrode connect the 3rd power end VDD, drain electrode connection institute
Second transistor P2 source electrode is stated, grid connects the control signal DISC, the 4th transistor P4's
Source electrode connects the second source end VSS, and drain electrode connects the source electrode of the second transistor P2, grid connection
The control signal DISC.
In addition, first vent unit 10 is also connected to including first resistor R1, the first resistor R1
Between the drain electrode of the first transistor P1 and the drain electrode of the second transistor P2.
In the present invention, when the control signal DISC control voltages probe unit 20 is opened so that first is brilliant
Body pipe P1 grid voltage (VA) declines so that the first transistor P1 is opened, so as to which described first releases
Unit 10 is opened, and the electric charge of the first power end VPP is released to the second source end VSS.
With continued reference to shown in Fig. 3, in the present invention, the second vent unit 30 connects the first power end VPP
With the 3rd power end VDD, and the first node S1 of first vent unit 10 is connected to.Specifically,
Second vent unit 30 includes the 5th transistor M5, the source electrode connection institute of the 5th transistor M5
The first power end VPP is stated, drain electrode connects the 3rd power end VDD, and grid is connected to the first node
S1, also, the 5th transistor P5 is PMOS transistor.In addition, the first node S1 and institute
State and be connected with the second phase inverter 40 and the 3rd phase inverter 50 in turn between the 5th transistor M5 grid, it is described
Second phase inverter 40 includes the tenth two-transistor M12 and the 13rd transistor M13, the tenth two-transistor M12
Source electrode connect the first power end VPP, the 13rd transistor M13 of drain electrode connection drain electrode, grid connects
Connect the first node, the 13rd transistor M13 source electrode connection second source end VSS, grid connection the
One node S1, the 3rd phase inverter 50 include the 14th transistor M14 and the 15th transistor M15, and the tenth
Four transistor M14 source electrode connects the first power end, the 5th transistor M5 of drain electrode connection grid, grid
The 13rd transistor M13 drain electrode is connected, the 15th transistor M15 source electrode connects the first power end VPP,
The 5th transistor M5 of drain electrode connection grid, grid connect the 13rd transistor M13 drain electrode.
With continued reference to shown in Fig. 3, in the present invention, voltage detection unit 20 is connected to the first node S1,
For detecting the voltage of the first node S1, specifically, the voltage detection unit 20 includes：
6th transistor M6, the 6th transistor M6 source electrode connect the 3rd power end VDD, drain electrode
First vent unit 10 is connected, grid is connected to section point S2, the 6th transistor M6 and is
PMOS transistor；
7th transistor M7, the 7th transistor M7 source electrode connect the 3rd power end VDD, drain electrode
The section point S2 is connected, grid is connected to the first node S1, and the 7th transistor M7 is
PMOS transistor；
Second resistance R2, second resistance R2 are connected to the drain electrode and described second of the 6th transistor M6
Between node S2；
8th transistor M8, the 8th transistor M8 drain electrode connect the section point S2, grid connection institute
It is nmos pass transistor to state control signal DISC, the 8th transistor M8；
9th transistor M9, the 9th transistor M9 source electrode connect the second source end VSS, and drain electrode connects
The drain electrode of the 8th transistor M8 is connect, grid is connected to the first node S1, the 9th transistor
M9 is nmos pass transistor.
When the process that the first power end VPP electric charge is released by the first vent unit 10 to second source end
In, first node S1 voltage constantly declines, when the voltage of the first node S1 drops to safety value,
I.e. the 5th transistor M5 safe voltage when, the 5th transistor M5 open so that second vent unit
30 open, and the electric charge of the first power end VPP is by the 5th transistor M5 to the 3rd power end
VDD releases.
In addition, the charge discharging resisting circuit also includes the 4th power end VPUMP, the 4th power end
The tenth transistor M10, the tenth transistor M10 are connected between VPUMP and the first power end VPP
Source electrode connect the 4th power end VPUMP, drain electrode connects the first power end VPP, grid connection
The 3rd power end VDD.Also, the charge discharging resisting circuit also includes the 11st transistor M11, source
Pole connects the first node S1, and drain electrode connects the 4th power end VPUMP, grid connection described the
Three power end VDD, for by the 4th power end VPUMP charge discharging resisting to second source end VSS.
With reference to shown in Fig. 3 and Fig. 4, the course of work of voltage leadage circuit is further detailed, its
The course of work is as follows：
In the T1 periods, when the control signal be DISC be low potential, the first power end VPP be erasing
When high pressure, the 3rd power end VDD are operating voltage, the 8th transistor M8 is closed, the first transistor M1
Grid voltage VA be high potential, the first transistor M1 is closed so that the first vent unit 10 is closed,
First power end VPP, the 3rd power end VDD, the 4th power end VPUMP voltage are constant；
In the T2 periods, when the control signal DISC rises to high potential, the 8th transistor
M8 is opened, so as to the 6th transistor M6, the 7th transistor M7, the 8th transistor M8 and the 9th crystal
Pipe M9 is opened so that the voltage detection circuit 20 is opened, the drain electrode electricity of the 6th transistor M6
Position declines therewith, and the first transistor M1 grid voltage VA declines, then the first transistor M1 is opened, from
And first vent unit 10 is opened, the electric charge of the first power end VPP passes through the first transistor M1
To be released with second transistor M2 to the second source end VSS, the first power end VPP voltage declines,
In addition, the 4th power end VPUMP electric charge is released with the 11st transistor M11 and second transistor M2
To second source end VSS, the 4th power end VPUMP voltage is also with decline；
In the T3 periods, released with the first power end VPP electric charge to second source end VSS, it is described
First node S1 current potential Vdet declines, and when dropping to the safety value, i.e. the 5th transistor M5 peace
Full voltage so that the 5th transistor M5 is opened, so as to which second leadage circuit 30 is opened, described first
Power end VPP electric charge is released by the 5th transistor M5 to the 3rd power end VDD, the 3rd power supply
VDD voltage is held to rise.Now, the current potential Vdet of the first node S1 drops to low potential, described
9th transistor M9 is closed, so that the voltage detection unit 20 is closed, so as to voltage detection circuit
20 are not present quiescent dissipation during charge discharging resisting afterwards.
It should be noted that first node S1 voltage Vdet is mainly brilliant by the first transistor M1 and second
The electric current decision that body pipe M2 flows through, wherein,
The first transistor M1 electric current is：
Wherein, Cox is the electric capacity of the first transistor M1 grid oxygen, and WM1/LM1 is the first transistor M1
Breadth length ratio, Vthp be the first transistor M1 threshold voltage.
Second transistor M2 electric current is：
Wherein, Cox is the electric capacity of second transistor M2 I grid oxygens, and WM2/LM2 is second transistor M2
Breadth length ratio, Vthn be second transistor M2 threshold voltage.
In the present invention, when second transistor M2 electric current IM2 is less than the first transistor M1 electric current IM1
When, first node S1 voltage is close to the first power end VPP, then electric charge is mainly from the first power end VPP
The 3rd power end VSS is flowed to, conversely, first node S1 voltage is close to second source end VSS, then electric charge
The 3rd power end VDD mainly is flowed to from the first power end VPP, so as to by controlling the first transistor
M1 and second transistor M2 current control the first power end VPP's releases.Further, it is assumed thatThen first power end VPP=Tx × VDD+VA-Tx × Vthn+Vthp, the 6th transistor
M6 grid voltage VA=VGSM6-IM6 × R2.Electricity of the VGSM6 between the 6th transistor M6 grid source
Pressure, IM6 are the 6th transistor M6 electric current, so that can be by controlling the first transistor M1 in the present invention
With second transistor M2 breadth length ratio, the opening time of the second leadage circuit 30 is controlled, controls the first power supply
The time that end VPP releases to the 3rd power end VDD, make the first power end VPP voltage electric close to the 3rd
The safe voltage that source VDD releases.Ensure excessively to arrive to the 3rd in safety of releasing to second source end VSS
Power end VDD releases, and can effectively suppress the 3rd power end VDD saltus step.Also, specific first
Transistor M1 and second transistor M2 breadth length ratio can be set according to the needs of actual circuit.
In summary, in the charge discharging resisting circuit of offer of the invention, including the first vent unit, second let out
Put unit and voltage detection unit, control signal causes voltage detection unit to open, and by the first vent unit
Open, the electric charge of the first power end is released to second source end by the first vent unit.The electricity of first node
Position declines with the first releasing for power end, when dropping to safety value so that and the second vent unit is opened,
Now, the electric charge of the first power end is by the second vent unit to the 3rd power end, also, voltage detection list
Member is accordingly turned off.In the present invention, voltage detection unit causes the electric charge of the first power end to be let out to second source end
Backward 3rd power end for putting a period of time is released, so as to control the first power end to second source end and the 3rd
The process of releasing of power end, also, voltage detection unit is closed over time, so as in the absence of static state
Power consumption.
Obviously, those skilled in the art can carry out various changes and modification without departing from this hair to the present invention
Bright spirit and scope.So, if the present invention these modifications and variations belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprising including these changes and modification.
Claims (13)
- A kind of 1. charge discharging resisting circuit, it is characterised in that including：First vent unit, one first power end of connection, a second source end and a control signal are described When control signal controls the first vent unit opening, the electric charge of first power end is electric to described second Source is released, and first vent unit has a first node；Second vent unit, first power end and one the 3rd power end are connected, and be connected to described first Node；Voltage detection unit, the first node is connected to, for detecting the voltage of the first node, when When the voltage of the first node drops to safety value, second vent unit is opened, first power supply The electric charge at end is released to the 3rd power end.
- 2. charge discharging resisting circuit as claimed in claim 1, it is characterised in that the first vent unit bag Include：The first transistor, source electrode connect first power end, and drain electrode connects the first node, and grid connects Connect the voltage detection unit；Second transistor, drain electrode connect the first node, and grid connects the 3rd power end；First phase inverter, input connect the control signal, and output end connects the source of the second transistor Pole.
- 3. charge discharging resisting circuit as claimed in claim 2, it is characterised in that first phase inverter includes Third transistor and the 4th transistor, the source electrode of the third transistor connect the 3rd power end, drain electrode The source electrode of the second transistor is connected, grid connects the control signal, the source electrode of the 4th transistor The second source end is connected, drain electrode connects the source electrode of the second transistor, the grid connection control letter Number.
- 4. charge discharging resisting circuit as claimed in claim 2, it is characterised in that first vent unit is also Including first resistor, the first resistor is connected to the drain electrode of the first transistor and the second transistor Drain electrode between.
- 5. charge discharging resisting circuit as claimed in claim 2, it is characterised in that the first transistor is PMOS transistor, the second transistor are nmos pass transistor.
- 6. charge discharging resisting circuit as claimed in claim 1, it is characterised in that the second vent unit bag Include the 5th transistor, the source electrode of the 5th transistor connects first power end, drain electrode connection described the Three power ends, grid are connected to the first node.
- 7. charge discharging resisting circuit as claimed in claim 6, it is characterised in that the first node with it is described The second phase inverter and the 3rd phase inverter are connected with turn between the grid of 5th transistor.
- 8. charge discharging resisting circuit as claimed in claim 6, it is characterised in that the 5th transistor is PMOS transistor.
- 9. charge discharging resisting circuit as claimed in claim 1, it is characterised in that the voltage detection unit bag Include：6th transistor, source electrode connect the 3rd power end, and drain electrode connects first vent unit, grid Pole is connected to section point；7th transistor, source electrode connect the 3rd power end, and drain electrode connects the section point, and grid connects It is connected to the first node；Second resistance, it is connected between drain electrode and the section point of the 6th transistor；8th transistor, drain electrode connect the section point, and grid connects the control signal；9th transistor, source electrode connect the second source end, and drain electrode connects the drain electrode of the 8th transistor, Grid is connected to the first node.
- 10. charge discharging resisting circuit as claimed in claim 9, it is characterised in that the 6th transistor and institute It is PMOS transistor to state the 7th transistor, and the 8th transistor and the 9th transistor are NMOS brilliant Body pipe.
- 11. charge discharging resisting circuit as claimed in claim 9, it is characterised in that when the control signal rises For high potential when, the 8th transistor is opened, and the voltage detection voltage is opened, the 6th transistor Current potential decline, first vent unit is opened, and the electric charge of first power end is to the second source End is released, and the current potential of the first node declines, and when dropping to the safety value, second vent discharge Road is opened, and the electric charge of first power end is released to the 3rd power end, the current potential of the first node Low potential is dropped to, the 9th transistor is closed, and the voltage detection unit is closed.
- 12. charge discharging resisting circuit as claimed in claim 1, it is characterised in that the charge discharging resisting circuit is also Including the 4th power end, the tenth transistor is connected between the 4th power end and first power supply, it is described The source electrode of tenth transistor connects the 4th power end, and drain electrode connects first power end, grid connection 3rd power end.
- 13. charge discharging resisting circuit as claimed in claim 8, it is characterised in that the charge discharging resisting circuit is also Including the 11st transistor, source electrode connects the first node, and drain electrode connects the 4th power end, grid Connect the 3rd power end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610318329.1A CN107370351B (en) | 2016-05-13 | 2016-05-13 | Charge bleeding circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610318329.1A CN107370351B (en) | 2016-05-13 | 2016-05-13 | Charge bleeding circuit |
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| Publication Number | Publication Date |
|---|---|
| CN107370351A true CN107370351A (en) | 2017-11-21 |
| CN107370351B CN107370351B (en) | 2019-12-27 |
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| CN201610318329.1A Active CN107370351B (en) | 2016-05-13 | 2016-05-13 | Charge bleeding circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108574480A (en) * | 2018-07-04 | 2018-09-25 | 中国电子技术标准化研究院 | Frequency detection start reset circuit and method |
| CN113364257A (en) * | 2021-05-11 | 2021-09-07 | 中天恒星(上海)科技有限公司 | Bleeder circuit, power conversion circuit, electronic device and bleeder method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1497730A (en) * | 2002-09-26 | 2004-05-19 | ��ʽ���綫֥ | non-volatile semiconductor memory |
| CN101034591A (en) * | 2006-03-06 | 2007-09-12 | 晶豪科技股份有限公司 | Method for erasing flash memory unit and flash memory device using the method |
| US20090161440A1 (en) * | 2007-12-19 | 2009-06-25 | Tseng Te-Chang | Integrated circuits and discharge circuits |
| CN102832799A (en) * | 2012-08-31 | 2012-12-19 | 苏州永健光电科技有限公司 | Switch circuit capable of quickly discharging transistor parasitic capacitance charge and charge discharging method thereof |
-
2016
- 2016-05-13 CN CN201610318329.1A patent/CN107370351B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1497730A (en) * | 2002-09-26 | 2004-05-19 | ��ʽ���綫֥ | non-volatile semiconductor memory |
| CN101034591A (en) * | 2006-03-06 | 2007-09-12 | 晶豪科技股份有限公司 | Method for erasing flash memory unit and flash memory device using the method |
| US20090161440A1 (en) * | 2007-12-19 | 2009-06-25 | Tseng Te-Chang | Integrated circuits and discharge circuits |
| TWI358067B (en) * | 2007-12-19 | 2012-02-11 | Powerchip Technology Corp | Integrated circuits and discharge circuits |
| CN102832799A (en) * | 2012-08-31 | 2012-12-19 | 苏州永健光电科技有限公司 | Switch circuit capable of quickly discharging transistor parasitic capacitance charge and charge discharging method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108574480A (en) * | 2018-07-04 | 2018-09-25 | 中国电子技术标准化研究院 | Frequency detection start reset circuit and method |
| CN108574480B (en) * | 2018-07-04 | 2024-05-03 | 中国电子技术标准化研究院 | Frequency detection starting reset circuit and method |
| CN113364257A (en) * | 2021-05-11 | 2021-09-07 | 中天恒星(上海)科技有限公司 | Bleeder circuit, power conversion circuit, electronic device and bleeder method |
| CN113364257B (en) * | 2021-05-11 | 2022-06-03 | 中天恒星(上海)科技有限公司 | Bleeder circuit, power conversion circuit, electronic device and bleeder method |
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| CN107370351B (en) | 2019-12-27 |
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