CN107396008B - CMOS image sensor low-noise reading circuit and reading method thereof - Google Patents

Abstract

The invention discloses a low-noise readout circuit of a CMOS image sensor and a readout method thereof. The readout circuit comprises a signal multiple sampling module, a signal integration module and a signal averaging module. Two ends of the signal integration module are respectively connected to the A signal multiple sampling module and a signal averaging module, the other end of the signal integration module is a signal input end, the other end of the signal averaging module is a signal output end, and the signal multiple sampling module performs multiple sampling of the signal to be processed Process and transmit it to the signal integration module for integration and summation, then transmit the integration and summation signal to the signal averaging module for averaging, and finally output the average value signal through the signal output terminal. The invention provides a low-noise readout circuit for a CMOS image sensor, which can effectively reduce the PIXEL equivalent input noise, is especially suitable for low-light environments, can effectively improve image quality, and is suitable for popularization.

Description

A low-noise readout circuit of a CMOS image sensor and a readout method thereof

technical field

The invention relates to the field of image sensors, in particular to a low-noise readout circuit of a CMOS image sensor and a readout method thereof.

Background technique

In the field of image sensors, improving image quality is an eternal theme. The photosensitive signal of the image sensor will be affected by various noise sources during transmission, making it difficult to improve the signal-to-noise ratio. Noise can cause various FPN (solid-state noise) and various random bright or dark spots in the image. Especially in low light conditions, due to the relatively small photo-generated current, the signal is easily submerged in noise, and the image quality is particularly poor in low light conditions.

The method used for noise processing in the prior art is CDS technology, that is, correlated double sampling technology. This method is widely used in the field of CMOS image sensors. This technology can reduce the FPN and source follower noise of pixel units. The effect is limited in the environment and cannot improve the image quality problem in low light environment.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a low-noise readout circuit of a CMOS image sensor and a readout method thereof. The low-noise readout circuit can effectively reduce the PIXEL equivalent input noise, and is especially suitable for low-light environments and can effectively Improve image quality, suitable for popular use.

In order to achieve the above object, the present invention adopts the following technical scheme: a low-noise readout circuit of a CMOS image sensor, which includes a signal multiple sampling module, a signal integration module and a signal averaging module, and the two ends of the signal integration module are respectively connected to the The signal multi-sampling module and the signal averaging module, the other end of the signal multi-sampling module is the signal input end, the other end of the signal averaging module is the signal output end, and the signal multi-sampling module performs signal processing on the signal to be processed. M times of sampling processing, where M is an integer greater than 1.

Further, the signal integration module integrates and sums the signals after M times of sampling, and outputs an integration and summation signal.

Further, the signal averaging module averages the integral summation signal, and outputs an average value signal.

Further, the signal multiple sampling module includes a first switch, a second switch, a third switch, a fourth switch and a first capacitor, wherein the signal input terminal is connected to one end of the first switch, and the first switch is connected to the first switch. The other end of the switch is connected to one end of the first capacitor and one end of the second switch, the other end of the second switch is connected to the reference voltage, and the other end of the first capacitor is connected to the third, One end of the fourth switch is connected to each other, the other end of the third switch is connected to the signal integration module, and the other end of the fourth switch is connected to the ground level.

Further, the signal integration module includes an operational amplifier, a fifth switch and a second capacitor; wherein, the negative input end of the operational amplifier, the other end of the third switch, one end of the fifth switch and the One end of the second capacitor is connected to each other; the forward input end of the operational amplifier is connected to the ground level, and the output end of the operational amplifier is connected to the other end of the fifth switch and the other end of the second capacitor.

Further, the signal averaging module includes a sixth switch, a seventh switch, an eighth switch, a third capacitor and a fourth capacitor; wherein, one end of the sixth switch is connected to the output end of the operational amplifier, and the other One end is connected to one end of the third capacitor and one end of the seventh switch, the other end of the third capacitor is connected to the ground level, and the other end of the seventh switch is connected to one end of the eighth switch and one end of the fourth capacitor is connected to each other, and the other end of the eighth switch and the other end of the fourth capacitor are both connected to the ground level.

Further, the capacitance value of the fourth capacitor is M-1 times the capacitance value of the third capacitor.

A readout method for a low-noise readout circuit of a CMOS image sensor, the steps are as follows:

S01: input the signal to be processed through the signal input terminal, the signal multiple sampling module performs M sampling processing on the to-be-processed signal and transmits the sampled signal to the signal integration module, where M is an integer greater than 1;

S02: the signal integration module integrates and sums the sampled signals, and outputs the integration and summation signal to the signal averaging module;

S03: The signal averaging module averages the integral summation signal, and outputs the average value signal through the signal output terminal.

其中，

为待处理信号经过M次采样后的平均电压，V_REF为参考电压。Further, when the signal to be processed is a voltage signal, the integral summation signal is

in,

is the average voltage of the signal to be processed after sampling M times, and V _REF is the reference voltage.

其中，

为待处理信号经过M次采样后的平均电压，V_REF为参考电压。Further, when the signal to be processed is a voltage signal, the average value signal is

in,

is the average voltage of the signal to be processed after sampling M times, and V _REF is the reference voltage.

The beneficial effects of the present invention are as follows: the low-noise readout circuit of a CMOS image sensor provided by the present invention processes the pixel signal by means of multiple sampling, integrating, summing and then averaging, which can effectively reduce the PIXEL equivalent input noise , especially suitable for low light environment, can effectively improve the image quality, suitable for promotion.

Description of drawings

FIG. 1 is a schematic structural diagram of a low-noise readout circuit of a CMOS image sensor according to the present invention.

FIG. 2 is a circuit diagram corresponding to Embodiment 1 of the patent.

FIG. 3 is a timing diagram corresponding to Embodiment 1 of the patent.

In the figure, 1 signal multiple sampling module, 2 signal integration module, 3 signal averaging module.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

As shown in FIG. 1 , a low-noise readout circuit of a CMOS image sensor provided by the present invention includes a signal multi-sampling module 1, a signal integration module 2 and a signal averaging module 3. The two ends of the signal integration module are respectively connected to the signal multi-sampling module. Module and signal averaging module, the other end of the signal integration module is the signal input end, the other end of the signal averaging module is the signal output end, the signal to be processed enters the signal multi-sampling module through the signal input end, and the signal multi-sampling module is the signal to be processed. Perform M times of sampling processing and transmit the sampled signal to the signal integration module, the signal integration module integrates and sums the signal after M sampling, and transmits the integrated and summed signal to the signal averaging module, and the signal averaging module calculates the integral The sum signal is averaged, and the averaged signal is output through the signal output terminal, where M is an integer greater than 1.

The present invention provides a readout method for a low-noise readout circuit of a CMOS image sensor. When the signal to be processed is a voltage, the steps are as follows:

S01: Input a signal to be processed through a signal input terminal, the signal multiple sampling module performs M sampling processing on the to-be-processed signal and transmits it to the signal integration module, where M is an integer greater than 1.

至信号平均模块，其中，M为信号多次采样模块中进行采样的次数，

为待处理信号经过M次采样后的平均电压，V_REF为参考电压。S02: The signal integration module integrates and sums the collected and processed signals, and outputs the integrated and summed voltage signal

to the signal averaging module, where M is the number of times of sampling in the signal multiple sampling module,

is the average voltage of the signal to be processed after sampling M times, and V _REF is the reference voltage.

S03: The signal averaging module is used to average the above integral summation voltage, and output the average voltage signal through the signal output terminal, wherein,

As shown in FIG. 1 , the signal multi-sampling module 1 includes a first switch SW1 , a second switch SW2 , a third switch SW3 , a fourth switch SW4 and a first capacitor C1 . The signal input end PIXEL_IN is connected to one end of the first switch SW1, and the other end of the first switch SW1 is connected to one end of the first capacitor C1 and one end of the second switch SW2. The other end of the second switch SW2 is connected to the reference voltage V _REF . The other end of the first capacitor C1 is connected to one end of the third switch SW3 and the fourth switch SW4. The other end of the third switch SW3 is connected to the signal integration module 2 . The other end of the fourth switch SW4 is connected to the ground level VSS.

The signal integration module 2 includes an operational amplifier OPA1, a fifth switch SW5, and a second capacitor C2. The negative input end of the operational amplifier OPA1 is connected to the other end of the third switch SW3, the end of the fifth switch SW5 and the end of the second capacitor C2. The forward input end of the operational amplifier OPA1 is connected to the ground level VSS, and the output end thereof is connected to the other end of the fifth switch SW5 and the other end of the second capacitor C2.

The signal averaging module includes a sixth switch SW6, a seventh switch SW7, an eighth switch SW8, a third capacitor C3 and a fourth capacitor C4. The capacitance value of the fourth capacitor C4 is M-1 times that of the third capacitor C3, where M is the number of times of sampling in the signal multiple sampling module. One end of the sixth switch SW6 is connected to the output end of the operational amplifier OPA1, and the other end of the sixth switch SW6 is connected to one end of the third capacitor C3 and one end of the seventh switch SW7. The other end of the third capacitor C3 is connected to the ground level VSS. The other end of the seventh switch SW7, one end of the eighth switch SW8 and one end of the fourth capacitor C4 are connected to each other and serve as the signal output end of the readout circuit of the present invention. The other end of the eighth switch SW8 and the other end of the fourth capacitor C4 are both connected to the ground level VSS.

A low-noise readout circuit of a CMOS image sensor and a readout method thereof provided by the present invention can be directed to voltage signals, current signals or other signals transmitted in the circuit.

The present invention provides a readout method for a low-noise readout circuit of a CMOS image sensor. Taking a voltage signal as an example, the steps are as follows:

S01: First control the first switch SW1 and the fourth switch SW4 to open, the voltage of one end of the first capacitor C1 connected to the first switch SW1 becomes V, and the other end is the ground level 0; then control the second switch SW2 and the third switch SW3 is turned on, one end of the first capacitor C1 connected to the second switch SW2 becomes the reference voltage V _REF , and the other end is connected to the negative input end of the operational amplifier, thereby realizing the first sampling of the voltage signal to be processed. This cycle is performed M times to complete M times of correlation sampling of the voltage signal to be processed.

其中，M为信号多次采样模块中进行采样的次数，

为待处理信号经过M次采样后的平均电压，V_REF为参考电压。S02: Integrate and sum up the signals processed by the above multiple sampling, and the output voltage of the operational amplifier is:

Among them, M is the number of times of sampling in the signal multi-sampling module,

is the average voltage of the signal to be processed after sampling M times, and V _REF is the reference voltage.

此时，VOUT输出待处理电压信号的M次相关采样的平均值，之后交给模数转换器ADC对待处理信号进行模数转换；S03: Control the sixth switch SW6 and the eighth switch SW8 to turn off, then the third capacitor C3 is connected in parallel with the fourth capacitor C4, and the charge on C3 is evenly distributed with C4. Since C4=(M-1)*C3, the average The value voltage signal is:

At this time, VOUT outputs the average value of M correlation samples of the voltage signal to be processed, and then sends it to the analog-to-digital converter ADC for analog-to-digital conversion of the signal to be processed;

In order to make the protection scope of the present invention clearer, the following example will specifically describe the process method of reading the RESET signal and the SIGNAL signal of the PIXEL by the readout circuit of the present invention.

Example 1

As shown in Figure 2 and Figure 3, the readout circuit proposed by the present invention is connected to a standard 4T PIXEL, and the MOS tubes connected to the photodiode are M1, M2, M3 and M4, wherein the TX signal is added to M1, and the external signal to M2 is added. RST signal, RS signal is applied to M4, Φ1 signal is applied to SW1 and SW4, Φ2 signal is applied to SW2 and SW3, ΦR signal is applied to SW5, Φ3 signal is applied to SW6 and SW8, and Φ4 signal is applied to SW7. The specific readout method Proceed as follows:

Step 1: After the photosensitive diode PD is exposed, RST changes from low level to high level, and then from high level to low level. During this time interval, a high pulse appears in ΦR, and then remains low. Φ3 changes from low level to high level, so that the sixth switch SW6 and the eighth switch SW8 are turned on.

Step 2: RS changes from low level to high level, and the RESET signal is output through the source of M4.

Step 3: The control signals Φ1 and Φ2 are a pair of two-phase non-overlapping clocks. The high pulse of Φ1 arrives first, opening the first switch SW1 and the fourth switch SW4, and the voltage at one end of the first capacitor C1 connected to the first switch SW1 becomes V _RESET1 , the other end is the ground level 0; then the high pulse of Φ2 arrives, Φ1 keeps the low level, the second switch SW2 and the third switch SW3 are turned on, and one end of the first capacitor C1 connected to the second switch SW2 becomes the reference voltage The other end of V _REF is connected to the negative input end of the operational amplifier, thereby realizing the first correlated sampling of the RESET signal. This cycle is carried out M times to complete the M correlation sampling and integral summation of the RESET signal;

When both Φ1 and Φ2 are kept low, the integral summation voltage signal at the output of OPA1 is:

为RESET信号经过M次采样后的平均电压。In formula 1

is the average voltage of the RESET signal after sampling M times.

Step 4: Then Φ3 changes from high level to low level, the sixth switch SW6 and the eighth switch SW8 are turned off, then Φ4 changes from low level to high level, and the third capacitor C3 and the fourth capacitor C4 are connected in parallel. The charge on C3 is evenly distributed with C4. Since C4=(M-1)*C3, the average voltage signal is:

At this time, VOUT ₁ outputs the average value of M correlation samples of the RESET signal, and then sends it to the analog-to-digital converter ADC to perform analog-to-digital conversion on the RESET signal.

Step 5: A high pulse appears in ΦR, and then remains low, Φ3 changes from low level to high level, so that the sixth switch SW6 and the eighth switch SW8 are turned on, and Φ4 changes from the previous high level to low level level, the TX signal changes from low level to high level, and PIXEL outputs SIGNAL signal.

Step 6: The control signals Φ1 and Φ2 are a pair of two-phase non-overlapping clocks. The high pulse of Φ1 arrives first, opening the first switch SW1 and the fourth switch SW4, and the voltage at one end of the first capacitor C1 connected to the first switch SW1 becomes V _SIGNAL1 , the other end is ground level 0; then the high pulse of Φ2 arrives, Φ1 remains low, the second switch SW2 and the third switch SW3 are turned on, and one end of the first capacitor C1 connected to the second switch SW2 becomes the reference voltage The other end of V _REF is connected to the negative input end of the operational amplifier, thereby realizing the first correlated sampling of the SIGNAL signal. This cycle is performed M times to complete M times of correlation sampling and integral summation of the SIGNAL signal.

When both Φ1 and Φ2 are kept low, the integral summation voltage signal output by OPA1 is:

为SIGNAL信号经过M次采样后的平均电压。In formula 3

is the average voltage of the SIGNAL signal after sampling M times.

Step 7: Then Φ3 changes from high level to low level, the sixth switch SW6 and the eighth switch SW8 are turned off, then Φ4 changes from low level to high level, and the third capacitor C3 and the fourth capacitor C4 are connected in parallel. The charge on C3 is evenly distributed with C4. Since C4=(M-1)*C3, the average voltage signal is:

At this time, VOUT ₂ outputs the average value of M correlation samples of the SIGNAL signal, and then sends it to the analog-to-digital converter ADC to perform analog-to-digital conversion on the SIGNAL signal.

Step 8: Calculate the difference between the digital values after the analog-to-digital conversion of VOUT ₁ and VOUT ₂ to obtain a low-noise light signal conversion value.

The above descriptions are only preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made by using the contents of the description and drawings of the present invention shall be similarly included in the The invention is within the scope of protection of the appended claims.

Claims (8)

1. A low-noise readout circuit of a CMOS image sensor, characterized in that it comprises a signal multiple sampling module, a signal integration module and a signal averaging module, and the two ends of the signal integration module are respectively connected to the signal multiple sampling module and the signal averaging module. In the signal averaging module, the other end of the signal multiple sampling module is a signal input end, the other end of the signal averaging module is a signal output end, and the signal multiple sampling module samples the signal to be processed M times, where M is an integer greater than 1; The signal multiple sampling module includes a first switch, a second switch, a third switch, a fourth switch and a first capacitor, wherein the signal input terminal is connected to the pixel signal, and the signal input terminal is connected to one end of the first switch , the other end of the first switch is connected to one end of the first capacitor and one end of the second switch, the other end of the second switch is connected to the reference voltage, and the other end of the first capacitor is connected to One ends of the third and fourth switches are connected to each other, the other end of the third switch is connected to the signal integration module, and the other end of the fourth switch is connected to the ground level; The signal averaging module includes a sixth switch, a seventh switch, an eighth switch, a third capacitor and a fourth capacitor; wherein, one end of the sixth switch is connected to the output end of the operational amplifier, and the other end thereof is connected to the first One end of the three capacitors and one end of the seventh switch are connected to each other, the other end of the third capacitor is connected to the ground level, and the other end of the seventh switch is connected to one end of the eighth switch and the fourth switch. One end of the capacitor is connected to each other, and the other end of the eighth switch and the other end of the fourth capacitor are both connected to the ground level. 2 . The low-noise readout circuit of a CMOS image sensor according to claim 1 , wherein the signal integration module integrates and sums the signals sampled for M times, and outputs an integrated and summed signal. 3 . 3 . The low-noise readout circuit of a CMOS image sensor according to claim 2 , wherein the signal averaging module averages the integral summation signal, and outputs an average value signal. 4 . 4 . The low-noise readout circuit of a CMOS image sensor according to claim 1 , wherein the signal integration module comprises an operational amplifier, a fifth switch and a second capacitor; wherein the negative of the operational amplifier The forward input end is connected to the other end of the third switch, one end of the fifth switch and one end of the second capacitor; the forward input end of the operational amplifier is connected to the ground level, and its output end is connected to the ground level. The other end of the fifth switch and the other end of the second capacitor are connected to each other. 5 . The low-noise readout circuit of a CMOS image sensor according to claim 1 , wherein the capacitance value of the fourth capacitor is M−1 times the capacitance value of the third capacitor. 6 . 6. A readout method for a low-noise readout circuit of a CMOS image sensor according to claim 1, wherein the steps are as follows: S01: input the signal to be processed through the signal input terminal, the signal multiple sampling module performs M sampling processing on the to-be-processed signal and transmits the sampled signal to the signal integration module, where M is an integer greater than 1; S02: the signal integration module integrates and sums the sampled signals, and outputs the integration and summation signal to the signal averaging module; S03: The signal averaging module averages the integral summation signal, and outputs the average value signal through the signal output terminal. 7 . The readout method for a low-noise readout circuit of a CMOS image sensor according to claim 6 , wherein when the signal to be processed is a voltage signal, the integral summation signal is: 8 .

in,

is the average voltage of the signal to be processed after sampling M times, and V _REF is the reference voltage. 8 . The readout method for a low-noise readout circuit of a CMOS image sensor according to claim 6 , wherein when the signal to be processed is a voltage signal, the average value signal is

in,

is the average voltage of the signal to be processed after sampling M times, and V _REF is the reference voltage.

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