CN107424969A - Semiconductor package device and method of manufacturing the same - Google Patents

Abstract

According to one or more embodiments of the present invention, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer has a first surface and a second surface opposite the first surface. The conductive pad is located on the first surface of the redistribution layer. A dielectric layer is on the first surface of the redistribution layer to cover the first portion of the conductive pad and expose the second portion of the conductive pad. The silicon layer is located on the dielectric layer. The silicon layer has a recess to expose a second portion of the conductive pad. A conductive contact is disposed on the silicon layer and extends into the recess of the silicon layer.

Description

Semiconductor packaging device and manufacturing method thereof

technical field

The present invention relates to a semiconductor packaging device and a manufacturing method thereof, and more particularly, relates to a semiconductor packaging device with a stack structure and a manufacturing method thereof.

Background technique

In a traditional three-dimensional semiconductor package, one or more semiconductor devices (such as a processing unit or memory) can be bonded to a substrate (ball grid array (BGA) substrate) through an interposer, wherein Through-silicon vias (TSVs) provide electrical connections between semiconductor devices and substrates. However, using TSV interposers increases the overall thickness or height of the semiconductor package.

Contents of the invention

This case claims priority to U.S. Provisional Patent Application (No. 62/326,678, which was filed on April 22, 2016), the contents of which are incorporated herein by reference for the disclosure of this case. This case is a continuation-in-part of U.S. Patent Application No. 15/404,093, filed January 11, 2017, and claims priority to said U.S. Patent Application, the contents of which are incorporated by reference as The disclosure of this case.

According to an embodiment of the present invention, the interposer includes: a redistribution layer, a conductive pad, and a dielectric layer. The redistribution layer has a first surface and a second surface opposite to the first surface. A conductive pad is on the first surface of the redistribution layer. The conductive pad includes a first part and a second part. A dielectric layer is on the first surface of the redistribution layer to cover the first portion of the conductive pad and expose the second portion of the conductive pad. A surface of the second portion of the conductive pad is substantially coplanar with a surface of the dielectric layer.

According to an embodiment of the present invention, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and conductive contacts. The redistribution layer has a first surface and a second surface opposite to the first surface. A conductive pad is on the first surface of the redistribution layer. A dielectric layer is on the first surface of the redistribution layer to cover the first portion of the conductive pad and expose the second portion of the conductive pad. A silicon layer is on the dielectric layer. The silicon layer has a recess to expose the second portion of the conductive pad. Conductive contacts are placed on the silicon layer and extend into grooves in the silicon layer.

According to an embodiment of the present invention, a method of manufacturing a semiconductor package includes: providing a silicon carrier; placing a dielectric layer on the silicon carrier, the dielectric layer including conductive pads; placing a redistribution layer on the dielectric layer electrically connecting to the conductive pad; connecting the die to the redistribution layer; removing a portion of the silicon carrier and the dielectric layer to expose the conductive pad; and placing a conductive contact to contact the conductive pad.

Description of drawings

1A illustrates a cross-sectional view of a semiconductor package according to an embodiment of the invention.

FIG. 1B illustrates an enlarged view of a portion of the semiconductor package of FIG. 1A in accordance with an embodiment of the invention.

1C illustrates an enlarged view of a portion of the semiconductor package of FIG. 1A in accordance with an embodiment of the invention.

2A, 2B, 2C, 2D and 2E illustrate a method of manufacturing a semiconductor package according to an embodiment of the invention.

3A, 3B and 3C illustrate a method of manufacturing a semiconductor package according to an embodiment of the invention.

Common reference numbers are used throughout the drawings and detailed description to refer to the same or similar components. The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.

detailed description

FIG. 1A illustrates a cross-sectional view of a semiconductor package 100 in accordance with some embodiments of the present invention. The semiconductor packaging device 100 includes a semiconductor packaging device 1 , an interposer 10 and a substrate 13 .

Depending on the specific application, the substrate 13 can be a flexible substrate or a rigid substrate. In some embodiments, the substrate 13 includes a plurality of conductive wires. In some embodiments, an external contact layer may also be formed or placed on the substrate 13 . In some embodiments, the external contact layer includes a ball grid array (BGA). In other embodiments, the external contact layer includes, but is not limited to, an array such as a land grid array (LGA) or an array of pins (PGA). In some embodiments, the external contact layer includes solder balls 13b, which may or may not include wires (such as an alloy of gold and tin solder or an alloy of silver and tin solder).

The semiconductor package device 1 is placed on the substrate 13 . The semiconductor package device 1 includes electronic components 11 a , 11 b and a package body 12 . Each electronic component 11a, 11b includes a plurality of semiconductor devices, such as (but not limited to) transistors, capacitors, and resistors, which are interconnected to form functional circuits through die interconnection structures to form an integrated circuit. As can be appreciated by those skilled in the art, a semiconductor die includes an active portion, which has integrated circuits and interconnect structures. The electronic devices 11a, 11b may be any suitable integrated circuit devices, which may include, but not limited to, microprocessors (single-core or multi-core), memory devices, chipsets, display devices or ASICs according to different embodiments.

The package 12 is positioned to cover or encase the electronic components 11a, 11b. In some embodiments, package body 12 comprises epoxy resin, molding compound (such as epoxy resin molding compound or other molding compound), polyimide, phenolic compound having filler (filler) dispersed therein. objects or materials, materials with polysiloxane, or combinations thereof.

The interposer 10 is placed between the semiconductor package device 1 and the substrate 13 to provide an electrical connection between the semiconductor package device 1 and the substrate 13 . The electronic components 11a, 11b are electrically connected to conductive contacts (such as micropads) 10b on the interposer 10 . The interposer 10 is electrically connected to the substrate 13 through a conductive contact (such as a controlled collapse chip connection pad, C4) 10b2. In some embodiments, the conductive contacts 10b1, 10b2 may be covered or encapsulated by an underfill.

FIG. 1B illustrates an enlarged view of a portion enclosed by a box A in the semiconductor package 100 of FIG. 1A according to an embodiment of the present invention. The interposer 10 includes a redistribution layer (redistribution layer, RDL), dielectric layers 10d, 10n, a silicon layer 10s, a passivation layer 10g, and a conductive pad 10p.

In some embodiments, the redistribution layer 10r includes stacked interlayer dielectrics (interlayer dielectrics, ILD) 10r1, 10r2 and conductive layers 10m1, 10m2 (such as metal layers). The conductive layers 10m1, 10m2 are integrated into the interlayer dielectrics 10r1, 10r2 and separated from each other. The conductive layers 10m1, 10m2 are wrapped or covered by interlayer dielectrics 10r1, 10r2, respectively. The conductive layers 10m1 and 10m2 are electrically connected to each other by a conductive interconnection structure (such as a via) 10v1. In some embodiments, the conductive layers 10m1 and 10m2 are sprayed on the surface by melting (or heating) metal by thermal spraying technology. In some embodiments, the redistribution layer 10r may include any number of interlayer dielectric and conductive layers according to different embodiments. For example, the redistribution layer 10r may include N interlayer dielectric and conductive layers, where N is an integer. In some embodiments, the interlayer dielectric 10r2 includes a plurality of openings to expose a portion of the conductive layer 10m2. The conductive contact 10b1 is disposed on the surface (eg, the second surface) 10r2 of the redistribution layer 10r and extends into the opening to make electrical contact with the exposed portion of the conductive layer 10m2.

The conductive pad 10p is placed on the surface (such as the first surface) 101r of the redistribution layer 10r, and is electrically connected to the conductive layer 10m1 through a conductive interconnection structure (such as a via hole) 10v2. In some embodiments, the height of the conductive interconnect structure 10v2 is less than about 1 micron (μm). The conductive pad 10p includes a first portion 10p1 placed on the surface 101r of the redistribution layer 10r and a second portion 10p2 in contact with the first portion 10p1. The width D1 of the first portion 10p1 is greater than the width D2 of the second portion 10p2.

The dielectric layer 10d is placed on the surface 101r of the redistribution layer 10r to cover or cover a portion of the sidewalls of the first portion 10p1 of the conductive pad 10p and the second portion 10p2 of the conductive pad 10p. In some embodiments, the dielectric layer 10d may include molding compound, pre-preg composite material (such as pre-preg, pre-preg), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride , silicon oxynitride, undoped silicon glass (UndopedSilicate Glass, USG) or any combination. In some embodiments, the molding compound may include, but is not limited to, an epoxy resin having a filler dispersed therein. In some embodiments, the prepreg may include (but is not limited to) a multilayer structure formed by stacking or laminating a plurality of prepregs/sheets.

The dielectric layer 10n is placed on the dielectric layer 10d to cover or cover the portion of the sidewall of the second portion 10p2 of the conductive pad 10p not covered by the dielectric layer 10d. In some embodiments, the surface 10n1 of the dielectric layer 10n is substantially coplanar with the surface 10p21 of the second portion 10p2 of the conductive pad 10p. In some embodiments, the dielectric layer 10n and the dielectric layer 10d are composed of different materials. For example, the dielectric layer 10n may be formed of silicon nitride, and the dielectric layer 10d may be formed of silicon oxide. In other embodiments, the dielectric layer 10n and the dielectric layer 10d may be composed of the same material.

The silicon layer 10s is disposed on the surface 10n1 of the dielectric layer 10n. The silicon layer 10s includes an opening to expose the surface 10p21 of the second portion 10p2 of the conductive pad 10p. In some embodiments, the thickness of the silicon layer 10s is about 10 μm to 30 μm.

A passivation layer 10g is disposed on the silicon layer 10s and extends into the opening of the silicon layer 10s to cover a portion of the surface 10p21 of the second portion 10p2 of the conductive pad 10p. In some embodiments, the passivation layer 10g includes silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide.

A conductive layer (such as under bump metallurgy, UBM) 10u is placed on the passivation layer 10g and extends into the opening of the silicon layer 10s to contact the surface 10p21 of the second portion 10p2 of the conductive pad 10p which is not passivated. 10g covered portion. For example, the conductive layer 10u is in contact with the sidewall 10g1 of the passivation layer 10g and the surface 10p21 of the second portion 10p2 of the conductive pad 10p.

A conductive contact (such as a C4 pad) 10b2 is placed on the conductive layer 10u and extends into the groove defined by the conductive layer 10u. In some embodiments, the conductive contact 10b2 is in electrical contact with the sidewall 10u1 and the bottom surface 10u2 of the groove defined by the conductive layer 10u.

As mentioned above, conventional TSV interposers increase the overall thickness of the semiconductor device. According to some embodiments of the present disclosure, the conductive contact 10b2 and the conductive contact 10b1 are electrically connected to each other through the conductive layer 10u, 10m1, 10m2, the conductive pad 10p and the conductive interconnection structure 10v1, 10v2, so as to provide the semiconductor package device 1 and the substrate. The electrical connection between the bottom 13. Therefore, the overall thickness of the semiconductor package 100 will be reduced.

FIG. 1C illustrates an enlarged view of a portion surrounded by a box A in the semiconductor package 100 of FIG. 1A according to another embodiment of the present invention. The interposer 10 ′ of FIG. 1C is similar to the interposer 10 of FIG. 1B , the difference is that the interposer 10 ′ does not have the silicon layer 10 s. In some embodiments, the passivation layer 10g is disposed on the surface 10n1 of the dielectric layer 10n. The passivation layer 10g includes an opening to expose a portion of the surface 10p21 of the second portion 10p2 of the conductive pad 10p.

2A , 2B, 2C, 2D and 2E are cross-sectional views of semiconductor structure fabrication methods at different stages according to some embodiments of the present disclosure. Some drawings are simplified to help better understand the embodiments of the present disclosure.

Referring to FIG. 2A , a substrate 20 is provided. Substrate 20 includes a silicon carbide (SiC) substrate, a sapphire substrate, or a silicon substrate. The interconnect structure 21 is formed or placed on the surface (eg, the first surface) 201 of the substrate 20 . In some embodiments, the interconnection structure 21 may include a redistribution layer 10r, a conductive pad 10p, dielectric layers 10d and 10n, and a conductive contact 10b1 as shown in FIG. 1B.

Referring to FIG. 2B , the electronic components 22 a, 22 b are formed or placed on the interconnection structure 21 and are electrically connected to the conductive contacts 10 b 1 of the interconnection structure 21 . Each electronic component 22a, 22b includes a plurality of semiconductor devices, such as (but not limited to) transistors, capacitors, and resistors, which are interconnected to form functional circuits through die interconnection structures to form an integrated circuit. As can be appreciated by those skilled in the art, the device side of a semiconductor die includes the active portion, which has integrated circuits and interconnect structures. Electronic devices 22a, 22b may be any suitable integrated circuit device, which may include, but is not limited to, a microprocessor (single-core or multi-core), memory device, chipset, display device, or ASIC according to various embodiments.

The underfill 22f is formed or placed to cover or encase the active sides of the electronic components 22a , 22b and the conductive contacts 10b1 of the interconnect structure 21 . Then a reflow process can be performed. Encapsulation 23 is then formed or placed to cover or encase electronic components 22a, 22b. In some embodiments, package body 23 comprises epoxy resin, molding compound (such as epoxy resin molding compound or other molding compound), polyimide, phenolic compound or material, a material with polysiloxane, or a combination thereof.

Referring to FIG. 2C , the semiconductor structure of FIG. 2B is turned over, and a part of the substrate 20 is removed by applying a polishing process on the surface (eg, the second surface) 202 of the substrate 20 to reduce the thickness of the substrate 20 . In some embodiments, the remaining portion of substrate 20 has a thickness of about 10 μm to 30 μm. The remaining portion of the substrate 20 can provide structural reinforcement to reduce structural bowing caused by subsequent processes.

The opening 20h is formed at one or more predetermined positions of the substrate 20 to expose the surface 10p21 of the second portion 10p2 of the conductive pad 10p. The opening 20h can be formed by etching or other suitable processes. In some embodiments, the conductive pad 10p is completely covered by the dielectric layer. Since the substrate 20 and the dielectric layer are composed of different materials, two different etching processes must be performed to remove the substrate 20 and the dielectric layer respectively, which increases manufacturing cost, time and difficulty. According to some embodiments of the present disclosure, since the surface 10p21 of the second portion 10p2 of the conductive pad 10p is not covered by the dielectric layer 10n, only a single etching process is performed on the substrate 20 to expose the conductive pad 10p. In some embodiments, the substrate 20 can be completely removed to expose the surface 10p21 of the second portion 10p2 of the conductive pad 10p.

Referring to FIG. 2D , a conductive layer 20u (such as a UBM) is formed or placed in the opening 20h to contact the surface 10p21 of the second portion 10p2 of the conductive pad 10p. Next, a conductive contact 20b (such as a C4 pad) is formed or placed on the conductive layer 20u and extends into the opening 20h to form the semiconductor package device 2 .

Referring to FIG. 2E , the semiconductor structure of FIG. 2D is connected to a substrate 24 (such as a BGA substrate). After the underfill is formed or placed to cover or encase the conductive contacts 20b, a reflow process may then be performed. Support structures 24p are formed or placed along the edge of substrate 24 to prevent cracking of semiconductor structure device 2 due to other objects placed thereon. In some embodiments, the process shown in FIGS. 2A-2E may be referred to as a "chip-first" process.

3A , 3B and 3C are cross-sectional views of a semiconductor structure fabrication method at different stages according to some embodiments of the present disclosure. Some drawings are simplified to help better understand the embodiments of the present disclosure. In some embodiments, the operation in FIG. 3A is performed after the operation in FIG. 2A .

Referring to FIG. 3A , the semiconductor structure shown in FIG. 2A is turned over, and the interconnection structure 21 is placed on the substrate 30 . The substrate 30 may be a glass substrate. The thickness of the substrate 20 is reduced by removing a portion of the substrate 20 by, for example, applying a grinding process on the surface of the substrate 20 . In some embodiments, the remaining portion of substrate 20 has a thickness of about 10 μm to 30 μm. The remaining portion of the substrate 20 can provide structural reinforcement to reduce structural bowing caused by subsequent processes.

The opening 20h is formed at one or more predetermined positions of the substrate 20 to expose the surface 10p21 of the second portion 10p2 of the conductive pad 10p. The opening 20h can be formed by etching or other suitable processes. As mentioned above, since the surface 10p21 of the second portion 10p2 of the conductive pad 10p is not covered by the dielectric layer 10n, only a single etching process is performed on the substrate 20 to expose the conductive pad 10p. In some embodiments, the substrate 20 can be completely removed to expose the surface 10p21 of the second portion 10p2 of the conductive pad 10p.

Referring to FIG. 3B , the semiconductor structure of FIG. 3A is turned over and the substrate 30 is removed from the interconnection structure 21 . A conductive layer 20u (such as a UBM) is formed or disposed within the opening 20h to contact the surface 10p21 of the second portion 10p2 of the conductive pad 10p. Next, a conductive contact 20b (such as a C4 pad) is formed or placed on the conductive layer 20u and extends into the opening 20h.

Referring to FIG. 3C , the semiconductor structure in FIG. 3B is turned over. The electronic components 22a, 22b are formed or placed on the interconnection structure 21 and are electrically connected to the conductive contacts 10b1 of the interconnection structure 21 . Each electronic component 22a, 22b includes a plurality of semiconductor devices, such as (but not limited to) transistors, capacitors, and resistors, which are interconnected to form functional circuits through die interconnection structures to form an integrated circuit. As can be appreciated by those skilled in the art, the device side of a semiconductor die includes the active portion, which has integrated circuits and interconnect structures. Electronic devices 22a, 22b may be any suitable integrated circuit device, which may include, but is not limited to, a microprocessor (single-core or multi-core), memory device, chipset, display device, or ASIC according to various embodiments.

The underfill 22f is formed or placed to cover or encase the active sides of the electronic components 22a , 22b and the conductive contacts 10b1 of the interconnect structure 21 . Then a reflow process can be performed. The package body 23 is then formed or placed to cover or wrap the electronic components 22a, 22b to form the semiconductor package device 2 as shown in FIG. 3C. In some embodiments, package body 23 comprises epoxy resin, molding compound (such as epoxy resin molding compound or other molding compound), polyimide, phenolic compound or material, a material with polysiloxane, or a combination thereof. In some embodiments, the process shown in FIGS. 3A-3C may be referred to as a "chip-last" process.

As used herein, the terms "substantially", "substantial", "about" and "approximately" are used to describe and take into account small variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance expressly occurred as well as instances where the event or circumstance occurred in close proximity. For example, the term may refer to less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1% %, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces along the same plane having a difference within microns, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm or within 1 μm. When the terms "substantially", "about", and "approximately" are used for an event or situation, it may mean that the event or the situation occurs exactly, or it may mean that the event or the situation is close to an approximation.

Two surfaces may be considered coplanar or substantially coplanar if the displacement of the two planes is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, "conduction" and "electrical contact" can be considered as the ability to transmit electric current. Conductive material usually means that it will not hinder the flow of electric current or cause a small resistance. One unit of conductivity is Siemens per meter (S/m). Typically the conductive material has a conductivity greater than 10 ⁴ S/m, such as at least 10 ⁵ S/m or at least 10 ⁶ S/m. The electrical conductivity of materials sometimes changes with temperature. Unless otherwise specified in this disclosure, the electrical conductivity of the material is measured at room temperature.

In the description of some embodiments, a component is located "on" another component may include that the component is directly on another component (such as physical contact), and may also mean that there are other components between the component and another component. components.

While the invention has been described and illustrated with reference to particular embodiments of the invention, these descriptions and illustrations do not limit the invention. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, differences may exist between the artist's reproduction in this invention and the actual device. There may be other embodiments of the invention not specifically described. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the invention. All such modifications are intended to come within the scope of the claims appended hereto. Although methods disclosed herein have been described with reference to certain operations performed in a particular order, it should be understood that such operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Thus, unless otherwise indicated herein, the order and grouping of operations is not a limitation of the invention.

Claims (13)

1. a kind of intermediary layer (ineterposer), it includes：

Layer (redistribution layer) is redistributed, it has first surface and relative with the first surface second Surface；

Conductive welding disk, its positioned at it is described redistribution layer the first surface on, the conductive welding disk include Part I and Part II；And

Dielectric layer, it is located on the first surface of the redistribution layer to cover the Part I of the conductive welding disk simultaneously The Part II of the exposure conductive welding disk, wherein the surface of the Part II of the conductive welding disk and the surface of the dielectric layer Substantial copline.

2. according to the intermediary layer as described in claim 1, wherein the width of the Part I of the conductive welding disk is more than the conduction The width of the Part II of pad.

3. according to the intermediary layer as described in claim 1, wherein

The dielectric layer further comprises oxide skin(coating) and nitride layer, institute of the oxide skin(coating) positioned at the redistribution layer State on first surface and the nitride layer is located in the oxide layer；And

The surface of the Part II of the conductive welding disk and the substantial copline in surface of the nitride layer.

4. according to the intermediary layer as described in claim 1, wherein the redistribution layer includes the first interconnection layer, described first interconnects Layer includes the through hole (via) electrically connected with the conductive welding disk.

5. according to the intermediary layer as described in claim 4, wherein the height of the through hole is less than 1 micron (μm).

6. according to the intermediary layer as described in claim 4, it further comprises the first conductive contact, and it is located at the redistribution layer Second surface on and electrically connect with first interconnection layer.

7. according to the intermediary layer as described in claim 1, it further comprises

Passivation layer, it is located on the surface of the dielectric layer, and the passivation layer has groove with the of the exposure conductive welding disk The surface of two parts；And

Second conductive contact, it is located on the passivation layer and extended into the groove of the passivation layer.

8. according to the intermediary layer as described in claim 7, it further comprises conductive layer, and it is located at the side wall of the groove and described On the surface of the Part II of conductive welding disk, wherein second conductive contact is by the conductive layer and conductive welding disk electricity Connection.

9. according to the intermediary layer as described in claim 1, it further comprises silicon layer, and it is located at the passivation layer and the dielectric layer Between, wherein disconnected from each other on the direction on the surface of the silicon layer dielectric layer substantially parallel with the conductive layer.

10. semiconductor packages, it includes：

Layer is redistributed, it has first surface and the second surface relative with the first surface；

Conductive welding disk, it is on the first surface of the redistribution layer；

Dielectric layer, it is located on the first surface of the redistribution layer to cover the Part I of the conductive welding disk and exposure The Part II of the conductive welding disk；And

Silicon layer, it is located on the dielectric layer, and the silicon layer has groove with the Part II of the exposure conductive welding disk；And

Conductive contact, it is positioned on the silicon layer and extended into the groove of the silicon layer.

11. according to the semiconductor packages as described in claim 10, it further includes passivation layer, and the passivation layer is located at the silicon On layer and the groove is extended into cover a part for the Part II of the side wall of the groove and the conductive welding disk.

12. according to the semiconductor packages as described in claim 10, wherein the width of the Part I of the conductive welding disk is more than institute State the width of the Part II of conductive welding disk.

13. according to the semiconductor packages as described in claim 10, wherein the surface of the Part II of the conductive welding disk with it is described The substantial copline in surface of dielectric layer.