CN107507821A - The encapsulating structure and method for packing of integrated image sensor chip and logic chip - Google Patents

Abstract

The present invention provides a packaging structure and packaging method for an integrated image sensor chip and a logic chip, comprising: a rewiring layer, a transparent cover, packaged on the first surface of the rewiring layer; a metal lead structure protruding from the The second surface of the rewiring layer; the image sensor chip and the logic chip are arranged on the second surface of the rewiring layer, and the image sensor chip, the logic chip and the metal lead structure pass through the The rewiring layer implements mutual electrical connection; the encapsulation material is formed on the second surface of the rewiring layer. The present invention can integrate the image sensor chip and the logic chip in the same package cavity, and has the advantages of small package volume and high reliability of the device; the present invention realizes the electrical lead-out of the rewiring layer through prefabricated metal pillars, and does not need silicon Processes such as perforation can greatly save process costs.

Description

Packaging structure and packaging method of integrated image sensor chip and logic chip

technical field

The invention belongs to the field of semiconductor packaging, in particular to a packaging structure and packaging method for an integrated image sensor chip and a logic chip.

Background technique

With the increasingly powerful functions of integrated circuits, higher performance and higher integration, and the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and in the value of the entire electronic system The proportion is increasing. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors are developing towards higher density and higher clock frequency, and packaging is also developing towards higher density.

Due to the advantages of miniaturization, low cost and high integration, as well as better performance and higher energy efficiency, fan-out wafer-level packaging (fowlp) technology has become a An important packaging method for high-demand mobile/wireless network and other electronic equipment is one of the most promising packaging technologies at present.

Existing image sensor chip packages usually have many disadvantages such as thicker thickness, higher cost of TSV process, easy breakage of metal wires, and lower overall yield rate.

In addition, image sensor chips, such as face recognition chips, usually need to be integrated with a logic chip. The existing manufacturing method is to electrically connect a separately packaged image sensor chip to the logic chip through external wiring. This packaging method makes the volume of the device larger, the assembly process is more complicated, and the stability of the structure is greatly reduced due to the need for external wiring, which seriously affects the yield of the final device structure.

Based on the above, it is necessary to provide a packaging structure and packaging method that can effectively integrate image sensor chips and logic chips, effectively reduce the packaging structure volume and device stability, and have high yield.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a packaging structure and packaging method for an integrated image sensor chip and logic chip, which is used to solve the problem of the large packaging volume of the image sensor chip and logic chip in the prior art. , low device stability and low product yield.

In order to achieve the above object and other related objects, the present invention provides a packaging structure integrating image sensor chips and logic chips, the packaging structure includes: a rewiring layer, including a first surface and a second surface opposite to the first surface surface; a transparent cover plate, packaged on the first surface of the rewiring layer; a metal lead structure, protruded on the second surface of the rewiring layer; an image sensor chip and a logic chip, arranged on the rewiring layer The second surface of the layer, and the image sensor chip, the logic chip and the metal lead structure are electrically connected to each other through the rewiring layer; and the packaging material is formed on the rewiring layer The second surface covers the image sensor chip, the logic chip and the metal lead structure, wherein the metal lead structure is exposed from the packaging material.

Preferably, the metal lead structure includes one of metal pillars, solder balls, and stacks of metal pillars and solder bumps.

Preferably, the height of the metal lead structure is greater than the thickness of the image sensor chip and the logic chip.

Preferably, the metal pillars include one of copper pillars, silver pillars, gold pillars, aluminum pillars, and tungsten pillars, and the solder balls or solder bumps include one of tin solder, silver solder, and gold-tin alloy solder. kind.

Preferably, the image sensor chip includes a substrate, an image recognition area formed on the substrate, and a pad formed on an edge area of the substrate, the pad is electrically connected to the image recognition area, and the image The identification area is completely exposed from the redistribution layer.

Preferably, the packaging material includes one of polyimide, silica gel and epoxy resin.

Preferably, the rewiring layer includes a patterned dielectric layer and a patterned metal wiring layer.

Preferably, the material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phospho-silicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes One or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

Preferably, the transparent cover is packaged on the rewiring layer based on a gold-tin bonding layer, and the transparent cover, the rewiring layer and packaging materials form a packaging cavity for the image sensor chip and the logic chip.

The present invention also provides a packaging method for an integrated image sensor chip and a logic chip, the packaging method comprising: 1) providing a support substrate, forming a separation layer on the surface of the support substrate; 2) forming a separation layer on the separation layer Forming a metal lead structure; 3) providing an image sensor chip and a logic chip, and adhering the image sensor chip and the logic chip on the separation layer, wherein the side of the image sensor chip and the logic chip having an electrical lead-out structure faces The separation layer; 4) packaging the image sensor chip and the logic chip with a packaging material; 5) separating the packaging material and the support substrate based on the separation layer; 6) using the packaging material, image Making a rewiring layer on the sensor chip and the logic chip to realize the electrical connection between the image sensor chip, the logic chip and the metal lead structure; and 7) encapsulating a transparent cover on the rewiring layer; Wherein, the manufacturing method further includes the step of exposing the metal lead structure to the packaging material.

Preferably, the supporting substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate; the separation layer includes one of an adhesive tape and a polymer layer, so The polymer layer is first coated on the surface of the support substrate by a spin-coating process, and then cured and shaped by an ultraviolet curing or thermal curing process.

Preferably, the metal lead structure includes one of metal pillars, solder balls, and stacks of metal pillars and solder bumps.

Preferably, the height of the metal lead structure is greater than the thickness of the image sensor chip and the logic chip.

Preferably, the image sensor chip includes a substrate, an image recognition area formed on the substrate, and a pad formed on an edge area of the substrate, the pad is electrically connected to the image recognition area, and the image The identification area is completely exposed from the redistribution layer.

Preferably, in step 6), the photoresist is covered before the image recognition area of the image sensor chip, and then the rewiring layer is fabricated.

Preferably, step 4) the method of packaging the image sensor chip and the logic chip with packaging materials includes one of compression molding, transfer molding, liquid seal molding, vacuum lamination and spin coating, and the packaging materials include poly One of imide, silicone and epoxy.

Preferably, step 6) making the rewiring layer is alternately performing the following steps: using a chemical vapor deposition process or a physical vapor deposition process to form a dielectric layer on the plane of the image sensor chip, logic chip and packaging material, and The dielectric layer is etched to form a patterned dielectric layer; a metal layer is formed on the surface of the patterned dielectric layer by using a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or an electroless plating process, and the metal layer is Etching is performed to form a patterned metal wiring layer.

Preferably, the material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phospho-silicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes One or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

Preferably, the transparent cover is packaged on the rewiring layer based on a gold-tin bonding layer, and the transparent cover, the rewiring layer and packaging materials form a packaging cavity for the image sensor chip and the logic chip.

Preferably, the method for exposing the metal lead structure to the packaging material is to thin the packaging material in step 4), step 5), step 6) or step 7).

As mentioned above, the packaging structure and packaging method of the integrated image sensor chip and logic chip of the present invention have the following beneficial effects:

1) The present invention adopts the method of rewiring layer to realize the electrical connection between the image sensor chip, the logic chip and the metal lead structure, and the image sensor chip and the logic chip can be integrated in the same package cavity, with the package The advantages of small size and high device reliability;

2) The present invention realizes the electrical lead-out of the rewiring layer through prefabricated metal pillars, and does not need to carry out processes such as through-silicon vias, which can greatly save process costs;

3) The process of the present invention is simple, can effectively improve the packaging performance of image sensor chips and logic chips, and has broad application prospects in the field of semiconductor packaging.

Description of drawings

1 to 10 are schematic structural diagrams of each step of the packaging method of the integrated image sensor chip and logic chip of the present invention.

Component designation description

101 Supporting substrate

102 separation layer

103 metal lead structure

104 image sensor chips

1041 Image recognition area

105 logic chips

106 Packaging material

107 rewiring layer

108 transparent cover

109 gold tin bonding layer

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 1 to Figure 10. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

As shown in FIGS. 1 to 10 , this embodiment provides a packaging method for integrating an image sensor chip 104 and a logic chip 105. The packaging method includes:

As shown in FIG. 1 to FIG. 2 , step 1) is firstly performed to provide a support substrate 101 , and a separation layer 102 is formed on the surface of the support substrate.

As an example, the supporting substrate 101 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate. In this embodiment, the support substrate 101 is selected as a glass substrate. The glass substrate is relatively low in cost, easy to form the separation layer 102 on its surface, and can reduce the difficulty of the subsequent peeling process.

As an example, the separation layer 102 includes one of an adhesive tape and a polymer layer. The polymer layer is first coated on the surface of the support substrate 101 by a spin-coating process, and then made by an ultraviolet curing or thermal curing process. Curing and forming.

In this embodiment, the separation layer 102 is selected as an adhesive tape, the cost of the adhesive tape is relatively low, and it only needs to be lifted by applying a force in the subsequent separation process, and the adhesion and separation processes are relatively simple. The cost of the whole process can be greatly saved.

As shown in FIG. 3 , step 2) is then performed to form a metal lead structure 103 on the separation layer 102 .

As an example, the metal lead structure 103 includes one of metal pillars, solder balls, and stacks of metal pillars and solder bumps. The shape of the metal leads can be adjusted according to the design of the subsequent rewiring layer 107, and finally the image sensor chip 104 and the logic chip 105 are electrically drawn out to the surface of the packaging material 106 through the rewiring layer 107 without using Expensive through-silicon via technology can realize electrical extraction.

As an example, the height of the metal lead structure 103 is greater than the thickness of the image sensor chip 104 and the logic chip 105 , so as to facilitate subsequent exposure of the metal lead structure 103 to the packaging material 106 .

In this embodiment, the metal lead structure 103 is selected as a copper column with good electrical conductivity, so as to further save the process cost.

As shown in Figure 4, then proceed to step 3), provide an image sensor chip 104 and a logic chip 105, and adhere the image sensor chip 104 and the logic chip 105 on the separation layer 102, wherein the image sensor chip 104 and the logic chip 105 have a side with an electrical lead-out structure facing the separation layer 102 .

As an example, the image sensor chip 104 includes a fingerprint recognition chip and the like.

As an example, the image sensor chip 104 includes a substrate, an image recognition region 1041 formed on the substrate, and a pad formed on an edge region of the substrate, and the pad is electrically connected to the image recognition region 1041 .

The number of the image sensor chip 104 can be one or two or more, the number of the logic chip 105 can also be one or two or more, the number of the image sensor chip 104 and the logic chip 105 They may be the same or different, and the actual functions of the image sensor and the logic chip 105 may be selected according to the performance requirements of the devices.

As shown in FIG. 5 , proceed to step 4) to package the image sensor chip 104 and the logic chip 105 with the packaging material 106 .

As an example, the method of packaging the image sensor chip 104 and the logic chip 105 with the packaging material 106 includes one of compression molding, transfer molding, liquid seal molding, vacuum lamination and spin coating, and the packaging material 106 includes One of polyimide, silicone and epoxy.

As an example, the thickness of the packaging material 106 is at least greater than the thickness of the image sensor chip 104 and the logic chip 105 , and in this embodiment, the thickness of the packaging material 106 is greater than the thickness of the metal lead structure 103 .

As shown in FIG. 6 to FIG. 7 , step 5) is followed to separate the packaging material 106 and the support substrate 101 based on the separation layer 102 .

As an example, separation may be achieved by applying a force to lift the encapsulation material 106 away from the separation layer 102 .

As shown in FIG. 7 , as an example, after the separation, a step of thinning the backside of the packaging material 106 to expose the metal lead structure 103 to the packaging material 106 is also included.

As shown in Figure 8, then proceed to step 6), first cover the photoresist on the image recognition area 1041 of the image sensor chip 104, and then make rewiring on the packaging material 106, the image sensor chip 104 and the logic chip 105 Layer 107 to realize the electrical connection between the image sensor chip 104, the logic chip 105 and the metal lead structure 103, and then remove the photoresist so that the image recognition area 1041 is completely exposed to the re- wiring layer 107.

Specifically, making the rewiring layer 107 includes:

Step a), using a chemical vapor deposition process or a physical vapor deposition process to form a dielectric layer on the packaging material 106 , the image sensor chip 104 and the logic chip 105 , and etching the dielectric layer to form a patterned dielectric layer.

As an example, the material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass. In this embodiment, the dielectric layer is selected as silicon oxide.

Step b), forming a metal layer on the surface of the patterned dielectric layer by using a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or an electroless plating process, and etching the metal layer to form a patterned metal layer wiring layer.

As an example, the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. In this embodiment, the material of the metal wiring layer is selected as copper.

It should be noted that the rewiring layer 107 may include a plurality of dielectric layers and a plurality of metal wiring layers stacked in sequence. According to the wiring requirements, the metal wiring layers of each layer may be realized by patterning each dielectric layer or making through holes. The interconnection between them is to realize the connection requirements of different functions.

As shown in FIG. 9 , step 7) is finally performed, encapsulating the transparent cover 108 on the redistribution layer 107 .

As an example, the transparent cover plate 108 is packaged on the rewiring layer 107 based on the gold-tin bonding layer 109, and the transparent cover plate 108, the rewiring layer 107 and the packaging material 106 form the image sensor chip 104 and logic The package cavity of the chip 105 .

In this embodiment, the transparent cover 108 is selected as a glass cover.

It should be noted that the method of exposing the metal lead structure 103 to the packaging material 106 can be realized by thinning the packaging material 106 in step 4), step 5), step 6) or step 7). .

In addition, the metal lead structure 103 can also be selected as a solder ball, and the final structure is shown in FIG. 10 .

As shown in FIG. 9 , this embodiment also provides a packaging structure for integrating an image sensor chip 104 and a logic chip 105. The packaging structure includes: a rewiring layer 107, including a first surface and a layer opposite to the first surface. The second surface; the transparent cover plate 108, packaged on the first surface of the rewiring layer 107; the metal lead structure 103, protruding from the second surface of the rewiring layer 107; the image sensor chip 104 and the logic chip 105, disposed on the second surface of the rewiring layer 107, and the image sensor chip 104, the logic chip 105, and the metal lead structure 103 are electrically connected to each other through the rewiring layer 107 and packaging material 106, formed on the second surface of the rewiring layer 107, and covering the image sensor chip 104, the logic chip 105 and the metal lead structure 103, wherein the metal lead The structure 103 is exposed from the encapsulation material 106 .

As an example, the metal lead structure 103 includes one of metal pillars, solder balls, and stacks of metal pillars and solder bumps.

As an example, the metal pillars include one of copper pillars, silver pillars, gold pillars, aluminum pillars and tungsten pillars, and the solder balls or solder bumps include one of tin solder, silver solder and gold-tin alloy solder. kind.

As an example, the image sensor chip 104 includes a substrate, an image recognition region 1041 formed on the substrate, and a pad formed on an edge region of the substrate, the pad is electrically connected to the image recognition region 1041, The image recognition area 1041 is completely exposed from the redistribution layer 107 .

As an example, the packaging material 106 includes one of polyimide, silicone and epoxy resin.

As an example, the rewiring layer 107 includes a patterned dielectric layer and a patterned metal wiring layer.

As an example, the material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes One or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

As an example, the transparent cover plate 108 is packaged on the rewiring layer 107 based on the gold-tin bonding layer 109, and the transparent cover plate 108, the rewiring layer 107 and the packaging material 106 form the image sensor chip 104 and logic The package cavity of the chip 105 .

In addition, the metal lead structure 103 can also be selected as a solder ball, and the final structure is shown in FIG. 10 .

As mentioned above, the packaging structure and packaging method of the integrated image sensor chip 104 and logic chip 105 of the present invention have the following beneficial effects:

1) The present invention adopts the method of rewiring layer 107 to realize the electrical connection between the image sensor chip 104, the logic chip 105 and the metal lead structure 103, and the image sensor chip 104 and the The logic chip 105 has the advantages of small packaging volume and high device reliability;

2) The present invention realizes the electrical lead-out of the rewiring layer 107 through prefabricated metal pillars, and does not need to carry out processes such as through-silicon vias, which can greatly save process costs;

3) The process of the present invention is simple, can effectively improve the packaging performance of the image sensor chip 104 and the logic chip 105, and has broad application prospects in the field of semiconductor packaging.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (20)

1. the encapsulating structure of a kind of integrated image sensor chip and logic chip, it is characterised in that the encapsulating structure includes：

Re-wiring layer, including the first face and second face relative with first face；

Transparent cover plate, it is packaged on the first face of the re-wiring layer；

Metal lead wire structure, it is convexly equipped on the second face of the re-wiring layer；

Image sensor chip and logic chip, it is arranged on the second face of the re-wiring layer, and described image sensor Chip, the logic chip and the metal lead wire structure realize mutual electrical connection by the re-wiring layer；With And

Encapsulating material, it is formed on the second face of the re-wiring layer, and is coated on described image sensor chip, described patrols Chip and the metal lead wire structure are collected, wherein, the metal lead wire structure is exposed to the encapsulating material.

2. the encapsulating structure of integrated image sensor chip according to claim 1 and logic chip, it is characterised in that：Institute State one kind in the lamination that metal lead wire structure is formed including metal column, solder ball and metal column with solder bump.

3. the encapsulating structure of integrated image sensor chip according to claim 2 and logic chip, it is characterised in that：Institute Stating metal column includes one kind in copper post, silver-colored post, principal column, aluminium post and tungsten post, and the solder ball or solder bump include soldering One kind in material, silver solder and gold-tin eutectic solder.

4. the encapsulating structure of integrated image sensor chip according to claim 1 and logic chip, it is characterised in that：Institute The height for stating metal lead wire structure is more than the thickness of described image sensor chip and logic chip.

5. the encapsulating structure of integrated image sensor chip according to claim 1 and logic chip, it is characterised in that：Institute Stating image sensor chip includes substrate, the image recognition region that is formed in the substrate and is formed at the basal edge The pad in region, the pad are electrically connected with described image identification region, and described image identification region is completely exposed in described Re-wiring layer.

6. the encapsulating structure of integrated image sensor chip according to claim 1 and logic chip, it is characterised in that：Institute Stating encapsulating material includes one kind in polyimides, silica gel and epoxy resin.

7. the encapsulating structure of integrated image sensor chip according to claim 1 and logic chip, it is characterised in that：Institute Stating re-wiring layer includes patterned dielectric layer and patterned metal wiring layer.

8. the encapsulating structure of integrated image sensor chip according to claim 7 and logic chip, it is characterised in that：Institute Stating the material of dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one kind in fluorine-containing glass or Two or more combinations, the material of the metal wiring layer include one or both of copper, aluminium, nickel, gold, silver, titanium combination of the above.

9. the encapsulating structure of integrated image sensor chip according to claim 1 and logic chip, it is characterised in that：Institute Transparent cover plate is stated to be packaged on the re-wiring layer based on golden tin bonded layer, the transparent cover plate, the re-wiring layer with Encapsulating material forms the package cavity of described image sensor chip and logic chip.

A kind of 10. method for packing of integrated image sensor chip and logic chip, it is characterised in that the method for packing bag Include：

1) support substrate is provided, separating layer is formed in the support substrate surface；

2) in formation metal lead wire structure in the separating layer；

3) image sensor chip and logic chip are provided, described image sensor chip and logic chip are adhered to described point On absciss layer, wherein, described image sensor chip and logic chip have the one of electric deriving structure facing to the separating layer；

4) described image sensor chip and logic chip are packaged using encapsulating material；

5) encapsulating material and the support substrate are separated based on the separating layer；

6) in making re-wiring layer on the encapsulating material, image sensor chip and logic chip, to realize described image Electrical connection between sensor chip, the logic chip and the metal lead wire structure；And

7) in encapsulating transparent cover plate on the re-wiring layer；

Wherein, the step of preparation method also includes making the metal lead wire structure be exposed to the encapsulating material.

11. the method for packing of integrated image sensor chip according to claim 10 and logic chip, it is characterised in that： The support substrate includes one kind in glass substrate, metal substrate, Semiconductor substrate, polymer substrate and ceramic substrate；Institute Stating separating layer includes one kind in adhesive tape and polymeric layer, and the polymeric layer is coated on the support using spin coating proceeding first Substrate surface, its curing molding is then made using ultra-violet curing or heat curing process.

12. the method for packing of integrated image sensor chip according to claim 10 and logic chip, it is characterised in that： The metal lead wire structure includes one kind in the lamination that metal column, solder ball and metal column are formed with solder bump.

13. the method for packing of integrated image sensor chip according to claim 10 and logic chip, it is characterised in that： The height of the metal lead wire structure is more than the thickness of described image sensor chip and logic chip.

14. the method for packing of integrated image sensor chip according to claim 10 and logic chip, it is characterised in that： Described image sensor chip includes substrate, the image recognition region that is formed in the substrate and is formed at the substrate side The pad in edge region, the pad are electrically connected with described image identification region, and described image identification region is completely exposed in institute State re-wiring layer.

15. the method for packing of integrated image sensor chip according to claim 14 and logic chip, it is characterised in that： In step 6), prior to the image recognition region overlay photoresist of described image sensor chip, the cloth again is then made again Line layer.

16. the method for packing of integrated image sensor chip according to claim 10 and logic chip, it is characterised in that： Step 4) includes compression forming, transfer modling using the method for encapsulating material encapsulation described image sensor chip and logic chip One kind in shaping, fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material include polyimides, silica gel and asphalt mixtures modified by epoxy resin One kind in fat.

17. the method for packing of integrated image sensor chip according to claim 10 and logic chip, it is characterised in that： Step 6) makes the re-wiring layer as alternately following steps：

Using chemical vapor deposition method or physical gas-phase deposition in described image sensor chip, logic chip and encapsulation The plane of material forms dielectric layer, and the dielectric layer is performed etching to form patterned dielectric layer；

Using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process in graphical Jie Matter layer surface forms metal level, and the metal level is performed etching to form patterned metal wiring layer.

18. the method for packing of integrated image sensor chip according to claim 17 and logic chip, it is characterised in that： The material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one kind in fluorine-containing glass Or two or more combinations, the material of the metal wiring layer include one or both of copper, aluminium, nickel, gold, silver, titanium above group Close.

19. the method for packing of integrated image sensor chip according to claim 10 and logic chip, it is characterised in that： The transparent cover plate is packaged on the re-wiring layer based on golden tin bonded layer, the transparent cover plate, the re-wiring layer The package cavity of described image sensor chip and logic chip is formed with encapsulating material.

20. the method for packing of integrated image sensor chip according to claim 10 and logic chip, it is characterised in that： The metal lead wire structure is set to be exposed to the method for the encapsulating material as in step 4), step 5), step 6) or step 7) The encapsulating material is thinned.