CN107508590A - Level shift circuit - Google Patents

Abstract

The present invention relates to a kind of level shift circuit, including：Control signal generation module, first order level shift circuit, second level level shift circuit, wherein, the first order level shift circuit includes resistance (R1), first switch pipe (M1)；The second level level shift circuit includes second switch pipe (M2), the 3rd switching tube (M3)；The number of circuit elements that the embodiment of the present invention uses is few, and circuit structure is simple, can effectively reduce circuit volume；The DC channel from supply voltage to ground is not present in second level level shift circuit, and circuit power consumption is low, is adapted to the level shift application of high-power high-frequency circuit prime.

Description

level shift circuit

technical field

The invention belongs to the technical field of electronic technology, and in particular relates to a level shift circuit.

Background technique

In the design of high-power high-voltage device drive circuits, it is usually necessary to use a charge pump circuit to provide sufficient current and power for the power main circuit, so the input pulse signal of the charge pump needs to provide sufficient power. However, the amplitude of the pulse signal used for the charge pump drive generated by the control circuit that usually constitutes the entire system with the power circuit cannot meet the actual application requirements of the circuit. The signal is converted into a high-voltage control signal to realize the control of the low-voltage logic on the output of the high-voltage power stage, thereby realizing the driving of high-voltage and high-power devices. Therefore, the previous level shifting circuit should provide enough power to drive the high-power charge pump circuit of the latter stage.

AU Optronics Co., Ltd. discloses a low power consumption level shift circuit in its patent application document "a low power consumption level shift circuit" (application publication number CN 104348477 A, application number 201410631274.0, application date 2014.11.11). A translation shift circuit, the circuit includes a first switch tube to a fifth switch tube. Respective first ends of the first switch tube and the second switch tube are coupled to the first voltage. The first end of the third switch transistor is coupled to the second end of the first switch transistor and its control end receives a clock input signal. The first end of the fourth switch transistor is coupled to the second end of the third switch transistor and the second end is electrically coupled to a ground voltage. The first end of the fifth switch transistor is coupled to the control end of the first switch transistor and the second end of the second switch transistor, and the second end of the fifth switch transistor is used for receiving the clock input signal. In this circuit, the first to third switch tubes are set as P-type MOS tubes, and the fourth and fifth switch tubes are set as N-type MOS tubes. By matching the level of the clock input signal and the second voltage, the power During the operation of the translational bit circuit, no direct current conduction loop will appear, so the power loss of the circuit can be effectively reduced. The shortcomings of this circuit are: the circuit uses five switching tubes and one resistor, the number of components is large, the structure is complex, and the power consumption of the circuit is large. At the same time, the circuit uses two potential levels, so the number of power sources in the circuit is large. Therefore, two power supplies need to be added, and the circuit structure is complicated.

Shanghai Shuming Semiconductor Co., Ltd. discloses a level shift circuit in its patent application document "a level shift circuit" (application publication number CN105634461A, application number 20151100519.3, application date 2015.12.28). The circuit includes a narrow pulse generator, which outputs the first narrow pulse signal according to the rising edge of the low-voltage duty ratio signal and outputs the second narrow pulse signal according to the falling edge of the input low-voltage duty ratio signal; the level shift module converts the first The narrow pulse signal is reversed and the potential is raised to the positive-ground of the floating power supply to obtain the first high-level reverse signal, and the second narrow pulse signal is reversed and the potential is raised to the positive-ground of the floating power supply to obtain the second high level Flat reverse signal; signal latch, output high-voltage duty ratio signal according to the first high-level reverse signal and second high-level reverse signal; driver stage circuit, control the opening and closing of the power tube according to the high-voltage duty ratio signal , the input end of the driver stage circuit is connected to the high-voltage duty ratio signal, and the output end is connected to the grid of the power transistor. The short pulse driving capability of the circuit is large, the level shift can be realized quickly, the time of level shift is shortened, and the power consumption is saved. The disadvantages of this circuit are: the circuit needs two high-voltage MOS tubes and two clamp field-effect MOS tubes or triodes, and the second stage of the level shift is composed of a resistor and a high-voltage MOS tube. In the range of 1KΩ to 10KΩ, due to the large resistance value of the resistor, there are the following disadvantages: 1. If the resistance value of the resistor is too small, a high-power resistor is required, and the volume of the resistor is too large, and the circuit volume is too large; 2. If a large resistance is used value resistance, it cannot provide a large enough current for the subsequent circuit.

Wang Xia, Zhou Zekun, Wang Zhuo, Zhang Bo et al. proposed a level shifting circuit in the paper "A New Type of High Speed and Low Power Consumption Level Shifting Circuit" (Microelectronics and Computers, 2015.11: 1-3). The level shifting circuit includes a fast response circuit and a low power consumption level shifting circuit. The circuit generates a narrow pulse to drive the establishment of the output signal level through the fast response circuit's fast response to the input low-voltage control signal; then maintains the output signal level through the low power consumption level maintenance circuit after the narrow pulse ends. The problems of the circuit disclosed in this paper are: the circuit contains 38 transistors, 3 diodes and 6 inverters, the circuit structure is complex, the number of components is large, the power consumption is large, and the circuit is suitable for integrated circuit applications, not It is suitable for high-power applications in the field of power electronics technology.

Therefore, developing a level shift circuit with simple circuit structure and low power consumption has become an urgent problem to be solved.

Contents of the invention

In order to solve the above problems in the prior art, the present invention provides a level shift circuit.

An embodiment of the present invention provides a level shift circuit, including: a control signal generation module, a first-stage level shift circuit, a second-stage level shift circuit, and an output terminal VOUT, wherein,

The first-level level shift circuit includes a resistor R1 and a first switch tube M1, the resistor R1 and the first switch tube M1 are connected in series between the power supply terminal VDD and the ground terminal GND, and the first switch tube The control terminal of M1 is electrically connected to the first output terminal VOUT1 of the control signal generating module;

The second stage level shifting circuit includes a second switching tube M2 and a third switching tube M3, the second switching tube M2 and the third switching tube M3 are connected in series between the power supply terminal VDD and the ground terminal Between GND, the control terminal of the second switching tube M2 is electrically connected to the node A formed by connecting the resistor R1 and the first switching tube M1 in series, and the control terminal of the third switching tube M3 is electrically connected to the The second output terminal VOUT2 of the control signal generating module; the output terminal VOUT is electrically connected to the node B formed by connecting the second switching tube M2 and the third switching tube M3 in series.

In an embodiment of the present invention, the control signal generating module includes: a pulse signal generating unit 101, a first delayed signal generating unit 102, a second delayed signal generating unit 103, and a NOR gate, wherein,

The first end of the pulse signal generation unit 101 is electrically connected to the ground terminal GND, and the second end of the pulse signal generation unit 101 is electrically connected to the input end of the first delay signal generation unit 102 and the The first input end of the NOR gate NOR; the output end of the first delay signal generation unit 102 is electrically connected to the input end of the second delay signal generation unit 103 and the first output end of the control signal generation module respectively VOUT1, the output end of the second delayed signal generating unit 103 is electrically connected to the second input end of the NOR gate NOR, and the output end of the NOR gate NOR is electrically connected to the second input end of the control signal generating module. output terminal VOUT2.

In one embodiment of the present invention, the first delayed signal generation unit 102 includes a first inverter D1, a second inverter D2, a third inverter D3, and a fourth inverter D4 connected in series in sequence. ; The input end of the first inverter D1 is electrically connected to the second end of the pulse signal generation unit 101, and the output end of the fourth inverter D4 is electrically connected to the second delay signal generation unit 103 input terminal.

In an embodiment of the present invention, the second delayed signal generating unit 103 includes a fifth inverter D5, a sixth inverter D6, a seventh inverter D7, and an eighth inverter D8 connected in series in sequence. ; The input end of the fifth inverter D5 is electrically connected to the output end of the first delay signal generating unit 102, and the output end of the eighth inverter D8 is electrically connected to the first NOR gate NOR an input terminal.

In an embodiment of the present invention, the first switch M1 , the second switch M2 and the third switch M3 are all MOS transistors.

In an embodiment of the present invention, the first switch M1 and the third switch M3 are NMOS transistors.

In one embodiment of the present invention, the second switch M2 is a PMOS transistor.

In an embodiment of the present invention, the output waveform of the pulse signal generating unit 101 is a rectangular pulse wave with an amplitude of 5V.

In an embodiment of the present invention, the value of the resistor R1 is 1KΩ.

In an embodiment of the present invention, the model of the first switch M1 and the third switch M3 is BSS138, and the model of the second switch M2 is BSS83P.

The embodiment of the present invention adopts a small number of circuit elements and a simple circuit structure, which can effectively reduce the circuit volume; the second-level level shift circuit does not have a DC path from the power supply voltage to the ground, and the circuit consumes low power, which is suitable for high-power high-frequency circuits Level-shifting application of pre-stage.

Description of drawings

FIG. 1 is a schematic structural diagram of a level shift circuit provided by an embodiment of the present invention;

FIG. 2 is a schematic circuit structure diagram of a level shift circuit control signal generation module provided by an embodiment of the present invention;

FIG. 3 is a schematic timing diagram of main control signals of a level shift circuit provided by an embodiment of the present invention;

4a to 4f are working principle diagrams of a level shift circuit provided by an embodiment of the present invention.

detailed description

The present invention will be described in further detail below in conjunction with specific examples, but the embodiments of the present invention are not limited thereto.

Embodiment one

Please refer to Figure 1 and Figure 2, Figure 1 is a schematic structural diagram of a level shift circuit provided by an embodiment of the present invention; Figure 2 is a schematic structural diagram of a level shift circuit control signal generation module provided by an embodiment of the present invention ; Wherein, the level shift circuit includes: a control signal generation module, a first level shift circuit, a second level shift circuit and an output terminal VOUT, wherein,

The first-level level shift circuit includes a resistor R1 and a first switch tube M1, the resistor R1 and the first switch tube M1 are connected in series between the power supply terminal VDD and the ground terminal GND, and the first switch tube The control terminal of M1 is electrically connected to the first output terminal VOUT1 of the control signal generating module;

The second stage level shifting circuit includes a second switching tube M2 and a third switching tube M3, the second switching tube M2 and the third switching tube M3 are connected in series between the power supply terminal VDD and the ground terminal Between GND, the control terminal of the second switching tube M2 is electrically connected to the node A formed by connecting the resistor R1 and the first switching tube M1 in series, and the control terminal of the third switching tube M3 is electrically connected to the The second output terminal VOUT2 of the control signal generating module; the output terminal VOUT is electrically connected to the node B formed by connecting the second switching tube M2 and the third switching tube M3 in series.

Wherein, the control signal generating module includes: a pulse signal generating unit 101, a first delayed signal generating unit 102, a second delayed signal generating unit 103, and a NOR gate, wherein,

The first end of the pulse signal generation unit 101 is electrically connected to the ground terminal GND, and the second end of the pulse signal generation unit 101 is electrically connected to the input end of the first delay signal generation unit 102 and the The first input end of the NOR gate NOR; the output end of the first delay signal generation unit 102 is electrically connected to the input end of the second delay signal generation unit 103 and the first output end of the control signal generation module respectively VOUT1, the output end of the second delayed signal generating unit 103 is electrically connected to the second input end of the NOR gate NOR, and the output end of the NOR gate NOR is electrically connected to the second input end of the control signal generating module. output terminal VOUT2.

Wherein, the first delayed signal generating unit 102 includes a first inverter D1, a second inverter D2, a third inverter D3, and a fourth inverter D4 connected in series in sequence; the first inverter The input end of the inverter D1 is electrically connected to the second end of the pulse signal generating unit 101 , and the output end of the fourth inverter D4 is electrically connected to the input end of the second delay signal generating unit 103 .

Wherein, the second delayed signal generating unit 103 includes a fifth inverter D5, a sixth inverter D6, a seventh inverter D7, and an eighth inverter D8 connected in series in sequence; the fifth inverter The input end of the eighth inverter D5 is electrically connected to the output end of the first delay signal generating unit 102, and the output end of the eighth inverter D8 is electrically connected to the first input end of the NOR gate NOR.

Wherein, the first switching tube M1, the second switching tube M2, and the third switching tube M3 are all MOS transistors.

Wherein, the first switch M1 and the third switch M3 are NMOS transistors.

Wherein, the second switch tube M2 is a PMOS transistor.

Wherein, the output waveform of the pulse signal generating unit 101 is a rectangular pulse wave with an amplitude of 5V.

Wherein, the value of the resistor R1 is 1KΩ.

Preferably, the models of the first switch M1 and the third switch M3 are BSS138, and the model of the second switch M2 is BSS83P.

Preferably, the eight inverters of the first delayed signal generating unit 102 and the second delayed signal generating unit 103 are realized by using two 74HC04 chips. The model of the NOR gate is 74HC02, and the signal of the pulse signal generating unit 101 can be generated by the previous stage control circuit.

Please refer to FIG. 3 . FIG. 3 is a timing diagram of main control signals of a level shift circuit provided by an embodiment of the present invention; the pulse signal CLK output by the pulse signal generating unit 101 of the present invention is a rectangular pulse wave with an amplitude of 5V. The output signal IN1 of the first output terminal VOUT1 of the control signal generation module is the output signal after the CLK signal is delayed by four inverters of the first delay signal generation unit 102, and the output signal IN0 of the output terminal of the second delay signal generation unit 103 is the output signal of the signal IN1 after being delayed by the four inverters of the second delay signal generating unit 103, and the output signal IN2 at the node A formed by the series connection of the resistor R1 and the first switching tube M1 is the signal IN1 passing through the resistor The output signal after inversion of the first stage level shift circuit composed of R1 and the first switch tube M1, the output signal IN3 of the second output terminal VOUT2 of the control signal generation module is the pulse signal CLK and the signal IN0 through the NOR gate NOR after the output signal. The pulse signal CLK, the signal IN0, the signal IN2 and the signal IN3 are all rectangular pulse waves with an amplitude of 5V.

Please refer to FIG. 4a-FIG. 4f. FIG. 4a-FIG. 4f are working principle diagrams of a level shift circuit provided by an embodiment of the present invention. The level shift circuit includes 6 working modes in one pulse signal CLK period.

When the level shift circuit starts to work, the circuit is in the first working mode, as shown in Figure 4a, the signal IN1 is at a low potential level, and the signal IN2 is at a high potential level, so the first switching tube M1 and the second switching tube M2 is in the off state, and the signal IN3 is at a low potential level, so the third switch tube M3 is in the on state, the resistor R1 and the first switch tube M1 will not generate a path from the power supply terminal VDD to the ground terminal GND, and the second switch tube M2 and the third switching tube M3 do not generate a path from the power supply terminal VDD to the ground terminal GND, which reduces power consumption of the circuit. At this moment, the output signal of the output terminal VOUT is low level.

When the circuit is in the second working mode, please refer to FIG. 4b, the signal IN1 is at a high potential level, so the first switch tube M1 is in an on state, and there is a voltage between the resistor R1 and the first switch tube M1 from the power supply terminal VDD to the ground terminal GND. At this time, the signal IN2 is at a high potential level, and the signal IN3 is at a low potential level, so the second light switch M2 and the third light switch M3 are in the off state, and the second light switch M2 and the third light switch M3 will not A path is generated from the power supply terminal VDD to the ground terminal GND to reduce circuit power consumption. At this time, the output signal of the output terminal VOUT is at a low level.

When the circuit is in the third working mode, as shown in Figure 4c, the signal IN1 is at a high potential level, the signal IN2 is at a low potential level, and the signal IN3 is at a low potential level, so the first switch tube M1 is in an on state, and the resistor R1 There is a path from the power supply terminal VDD to the ground terminal GND with the first light switching tube M1; at this time, the second light switching tube M2 is in the open state, and there is a DC path from the power supply terminal VDD to the output terminal VOUT; the third light switching tube M3 is in the In the off state, the second switching tube M2 and the third switching tube M3 do not generate a path from the power supply terminal VDD to the ground terminal GND, which reduces power consumption of the circuit. At this time, the output signal of the output terminal VOUT is at a high level.

When the circuit is in the fourth working mode, as shown in FIG. 4d, the signal IN1 is at a low potential level, and the signal IN2 is at a low potential level, so the first switching tube M1 is in an off state, and the second switching tube M2 is in an on state. The signal IN3 is at a low potential level, so the third switch tube M3 is in the off state, the resistor R1 and the first switch tube M1 will not generate a path from the power supply terminal VDD to the ground terminal GND, and there is a path from the power supply terminal VDD through the second switch tube M1. The path from the switch tube M2 to the output terminal Vout, the second switch tube M2 and the third switch tube M3 will not generate a path from the power supply terminal VDD to the ground terminal GND, which reduces the power consumption of the circuit; at this time, the output signal of the output terminal VOUT is high level.

When the circuit is in the fifth working mode, as shown in FIG. 4e, the signal IN1 is at a low potential level, and the signal IN2 is at a high potential level, so the first switching tube M1 and the second switching tube M2 are in an off state, and the signal IN3 is low potential level, so the third switch tube M3 is in the off state, the resistor R1 and the first switch tube M1 will not generate a path from the power supply terminal VDD to the ground terminal GND, and the second switch tube M2 and the third switch tube M3 will not A path will be generated from the power supply terminal VDD to the ground terminal GND to reduce circuit power consumption. At this time, the output signal of the output terminal VOUT is at a high level.

When the circuit is in the sixth working mode, as shown in FIG. 4f, the signal IN1 is at a low potential level, the signal IN2 is at a high potential level, and the signal IN3 is at a high potential level, so the first switching tube M1 and the second switching tube M2 In the off state, the third switch tube M3 is in the on state, the resistor R1 and the first switch tube M1 will not generate a path from the power supply terminal VDD to the ground terminal GND, and the second switch tube M2 and the third switch tube M3 will not generate The path from the power supply terminal VDD to the ground terminal GND reduces circuit power consumption. At this time, the output signal of the output terminal VOUT is at a low level.

After the sixth working mode ends, the circuit restarts to work from the first working mode.

In this embodiment, the control signal generating module is used to generate two channels of rectangular pulse waves with a certain delay characteristic to respectively control the first level shifting circuit in the level shifting circuit and the _first switching tube M1 in the second level shifting circuit. and the switching state of the _third switch tube M3, so the second switch tube _M2 and the _third switch tube M3 of the second level shift circuit will not be turned on at the same time, and there is no connection from the power supply terminal VDD to the ground terminal GND DC path to reduce circuit power consumption. The second switch tube of the second stage level shift circuit is a PMOS tube and the third switch tube is an NMOS tube. Since the on-resistance of the PMOS tube is at the milliohm level, it can provide a large current and high power for the subsequent circuit, and is suitable for application The driving pre-stage of high-power circuits in the field of power electronics. Two NMOS tubes and one PMOS tube, two inverter chips and one NOR gate NOR are used to realize high-frequency and low-power level shifting, which effectively reduces the circuit volume, reduces circuit power consumption, and simplifies the circuit structure . This level shift circuit can expand the first delay signal generation unit 102 and the second delay signal generation unit 103 of the control signal generation module into a delay chip with a longer delay time, which is suitable for the level shift of the front stage of high-power and high-frequency circuits application.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. A kind of 1. level shift circuit, it is characterised in that including：Control signal generation module, first order level shift circuit, Two level level shift circuit and output end (VOUT), wherein,

   The first order level shift circuit includes resistance (R1), first switch pipe (M1), the resistance (R1) and described first Switching tube (M1) is serially connected between power end (VDD) and earth terminal (GND), the control terminal electrical connection of the first switch pipe (M1) To the first output end (VOUT1) of the control signal generation module；

   The second level level shift circuit includes second switch pipe (M2), the 3rd switching tube (M3), the second switch pipe (M2) it is serially connected with the 3rd switching tube (M3) between the power end (VDD) and the earth terminal (GND), described second opens The control terminal for closing pipe (M2) is electrically connected to the node (A) that the resistance (R1) concatenates formation with the first switch pipe (M1), institute The control terminal for stating the 3rd switching tube (M3) is electrically connected to the second output end (VOUT2) of the control signal generation module；It is described Output end (VOUT) is electrically connected to the second switch pipe (M2) and the node (B) formed is concatenated with the 3rd switching tube (M3).
2. 2. level shift circuit according to claim 1, it is characterised in that the control signal generation module includes：Arteries and veins Rush signal generation unit (101), the first postpones signal generation unit (102), the second postpones signal generation unit (103) or non- Door (NOR), wherein,

   The first end of the pulse signal generation unit (101) is electrically connected to the earth terminal (GND), and the pulse signal produces Second end of unit (101) is respectively electrically connected to the input of the first postpones signal generation unit (102) and described or non- The first input end of door (NOR)；The output end of the first postpones signal generation unit (102) is respectively electrically connected to described second The first output end (VOUT1) of the input of postpones signal generation unit (103) and the control signal generation module, described The output end of two postpones signal generation units (103) is electrically connected to the second input of the nor gate (NOR), the nor gate (NOR) output end is electrically connected to the second output end (VOUT2) of the control signal generation module.
3. 3. level shift circuit according to claim 2, it is characterised in that the first postpones signal generation unit (102) the first phase inverter (D1), the second phase inverter (D2), the 3rd phase inverter (D3), the 4th phase inverter being sequentially connected in series are included (D4)；The input of first phase inverter (D1) is electrically connected to the second end of the pulse signal generation unit (101), described The output end of 4th phase inverter (D4) is electrically connected to the input of the second postpones signal generation unit (103).
4. 4. level shift circuit according to claim 2, it is characterised in that the second postpones signal generation unit (103) the 5th phase inverter (D5), hex inverter (D6), the 7th phase inverter (D7), the 8th phase inverter being sequentially connected in series are included (D8)；The input of 5th phase inverter (D5) is electrically connected to the output end of the first postpones signal generation unit (102), The output end of 8th phase inverter (D8) is electrically connected to the nor gate (NOR) first input end.
5. 5. level shift circuit according to claim 1, it is characterised in that the first switch pipe (M1), described second Switching tube (M2), the 3rd switching tube (M3) are MOS transistor.
6. 6. level shift circuit according to claim 1, it is characterised in that the first switch pipe (M1), the described 3rd Switching tube (M3) is nmos pass transistor.
7. 7. level shift circuit according to claim 1, it is characterised in that the second switch pipe (M2) is PMOS crystal Pipe.
8. 8. level shift circuit according to claim 1, it is characterised in that the pulse signal generation unit (101) Output waveform is rectangular wave pulse, and its amplitude is 5V.
9. 9. level shift circuit according to claim 1, it is characterised in that the value of the resistance (R1) is 1K Ω.
10. 10. level shift circuit according to claim 1, it is characterised in that the first switch pipe (M1) and described The model BSS138, the model BSS83P of the second switch pipe (M2) of three switching tubes (M3).