CN107527641A - Memory cell and memory - Google Patents
Memory cell and memory Download PDFInfo
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- CN107527641A CN107527641A CN201610485907.0A CN201610485907A CN107527641A CN 107527641 A CN107527641 A CN 107527641A CN 201610485907 A CN201610485907 A CN 201610485907A CN 107527641 A CN107527641 A CN 107527641A
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- 230000015654 memory Effects 0.000 title claims abstract description 155
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 26
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- 238000010586 diagram Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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Abstract
The present invention provides a kind of memory cell and memory, including：First sub- memory cell, including the first transistor and second transistor, the grid connection selection grid polar curve of the first transistor, source electrode connects the drain electrode of the second transistor, drain electrode connects first bit line, and the grid of the second transistor connects the first wordline, source electrode connection source electrode line；Second sub- memory cell, including third transistor and the 4th transistor, the grid of the third transistor connects the selection grid polar curve, source electrode connects the drain electrode of the 4th transistor, drain electrode connects second bit line, the grid of 4th transistor connects the second wordline, and source electrode connects the source electrode line；Wherein, the logic state of the described first sub- memory cell and the second sub- memory cell is opposite.In the memory cell reading process of the present invention, it is not necessary to which reference current, the current intervals that memory cell is read are bigger, shorten the time of reading, improve the reliability of reading.
Description
Technical field
The present invention relates to memory technology field, more particularly to a kind of memory cell and memory.
Background technology
Memory is part important in digital integrated electronic circuit, and it is even more to build the application system based on microprocessor
An indispensable part.In recent years, various memories are embedded in inside processor to improve the integrated level of processor by people
With operating efficiency, therefore, the performance of memory array and its peripheral circuit largely determines the work of whole system
Efficiency.
Reading circuit is the important component of the peripheral circuit of memory, and reading circuit is usually used to memory
Memory cell carry out read operation when on memory cell bit line (BL, Bit Line) tiny signal carry out sampling transformation go forward side by side
Row amplification, so that it is determined that the storage information in memory cell.
The working mechanism of reading circuit is by the current/voltage on the memory cell bit line by memory and benchmark electricity
Stream/voltage ratio compared with and read the data in memory cell.More specifically, the work of reading circuit is divided into two stages, when
Pre-charging stage, i.e. the bit line of the memory cell to choosing is pre-charged, second, comparison phase, the position for the memory cell that will be chosen
Line current/voltage and reference current/voltage ratio compared with.In pre-charging stage, the current potential of bit line is promoted to can be single in storage
The level of the bit line current of enough sizes is produced in member；And in comparison phase, by bit line current/voltage and reference current/electricity
Pressure is compared and outputting standard logic level, so as to play a part of amplifying bit line signal, is easy to read data.
With reference to shown in figure 1, the tiny signal difference of bit line current and reference current is enlarged into the logic state " 0 " of standard
" 1 ", then export " 0 " or " 1 ".Following defect at least be present in the reading circuit of prior art：By bit line current and benchmark electricity
Flow in comparison procedure, reference current is arranged to the current value between logical zero and " 1 " so that logical zero and the electric current of " 1 " and
Interval R1, R2 of reference current are smaller, and so as to which the read access time resulted in the need for is long, the reliability of reading is low.
The content of the invention
It is an object of the present invention to provide a kind of memory cell and memory, solves memory cell in the prior art and reads
The problem of overlong time, low reliability.
In order to solve the above technical problems, the present invention provides a kind of memory cell, including：
First sub- memory cell, including the first transistor and second transistor, the grid connection choosing of the first transistor
Gate line is selected, source electrode connects the drain electrode of the second transistor, and drain electrode connects first bit line, the grid of the second transistor
Pole connects the first wordline, source electrode connection source electrode line；
Second sub- memory cell, including third transistor and the 4th transistor, the grid connection institute of the third transistor
Selection grid polar curve is stated, source electrode connects the drain electrode of the 4th transistor, and drain electrode connects second bit line, the 4th transistor
Grid connect the second wordline, source electrode connects the source electrode line；
Wherein, the logic state of the described first sub- memory cell and the second sub- memory cell is opposite.
Optionally, first bit line is drawn into the memory cell compared with the electric current of second bit line
Logic state.
Optionally, if the first sub- memory cell is logical zero, the second sub- memory cell is logical one, then institute
The electric current for stating the first bit line is more than the electric current of second bit line, and the memory cell is logical zero.
Optionally, if the first sub- memory cell is logical one, the second sub- memory cell is logical zero, then institute
The electric current for stating the first bit line is less than the electric current of second bit line, and the memory cell is logical one.
Optionally, the first transistor, the second transistor, the third transistor and the 4th transistor are equal
For PMOS transistor.
Optionally, the first transistor including the first source electrode in Semiconductor substrate, the first drain electrode and is located at
The first choice grid in the Semiconductor substrate between first source electrode and first drain electrode.
Optionally, the second transistor include be located at the Semiconductor substrate in the second source electrode, second drain electrode, be located at
Second source electrode and it is described second drain electrode between the Semiconductor substrate on the first floating gate and positioned at described first
The first control gate in floating gate.
Optionally, the third transistor including the 3rd source electrode in Semiconductor substrate, the 3rd drain electrode and is located at
The second selection gate in the Semiconductor substrate between 3rd source electrode and the 3rd drain electrode.
Optionally, the 4th transistor include be located at the Semiconductor substrate in the 4th source electrode, the 4th drain electrode, be located at
4th source electrode and it is described 4th drain electrode between the Semiconductor substrate on the second floating gate and positioned at described second
The second control gate in floating gate.
Accordingly, the present invention also provides a kind of memory, including：
The said memory cells of array distribution；
Comparator, has at least two inputs and an output end, and two inputs connect the first bit line respectively
With the second bit line, and according to the size of current of first bit line and second bit line, the logic of the memory cell is exported
State.
Optionally, if the first sub- memory cell is logical zero, the second sub- memory cell is logical one, then described first
The electric current of line is more than the electric current of second bit line, and the comparator exports the logic state " 0 " of the memory cell.
Optionally, if the first sub- memory cell is logical one, the second sub- memory cell is logical zero, then described first
The electric current of line is less than the electric current of second bit line, and the comparator exports the logic state " 1 " of the memory cell.
In the memory cell and memory of the present invention, memory cell includes the first sub- memory cell of connection and the second son is deposited
The logic state of storage unit, the first sub- memory cell and the second sub- memory cell to memory cell on the contrary, patrol
When the state of collecting is read out, it is connected by the electric current for the first bit line being connected with the first quantum memory and with the second quantum memory
The electric current of second bit line is compared, and patrolling for the memory cell is determined according to the size of the first bit line and the electric current of the second bit line
The state of collecting.In the memory cell reading process of the present invention, it is not necessary to reference current, the current intervals that memory cell is read are bigger,
Shorten the time read, improve the reliability of reading.
Brief description of the drawings
Fig. 1 is the schematic diagram that memory cell of the prior art is read；
Fig. 2 is the device architecture schematic diagram of memory cell in one embodiment of the invention；
Fig. 3 is the electrical block diagram of memory cell in one embodiment of the invention；
Fig. 4 is the structural representation of the memory in one embodiment of the invention.
Embodiment
The memory cell and memory of the present invention are described in more detail below in conjunction with schematic diagram, which show
The preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still realize
The advantageous effects of the present invention.Therefore, description below is appreciated that for the widely known of those skilled in the art, and not
As limitation of the present invention.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expended
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The core concept of the present invention is that memory cell includes the first sub- memory cell connected and the second son storage is single
The logic state of member, the first sub- memory cell and the second sub- memory cell is on the contrary, in the logic shape to memory cell
When state is read out, by the electric current for the first bit line being connected with the first quantum memory and be connected with the second quantum memory second
The electric current of bit line is compared, and the logic shape of the memory cell is determined according to the size of the first bit line and the electric current of the second bit line
State.In the memory cell reading process of the present invention, it is not necessary to which reference current, the current intervals that memory cell is read are bigger, shorten
The time of reading, improve the reliability of reading.
The memory cell and memory of the present invention are described in detail below in conjunction with Fig. 2~Fig. 4,
With reference to shown in Fig. 2 and Fig. 3, a kind of memory cell provided by the invention is deposited including the first sub- memory cell 11 and second
Storage unit 12, the first memory cell 11 is identical with the structure of the second memory cell 12, wherein, Fig. 2 is the device junction of memory cell
Structure schematic diagram, Fig. 3 are the electrical block diagram of memory cell.
With reference to shown in figure 2, the first sub- memory cell 11 includes the first transistor P1 and second transistor P2, the second son storage
Unit 12 includes third transistor P3 and the 4th transistor P4, the first transistor P1, second transistor P2, the 4th transistor P4 with
And third transistor P3 is sequentially formed in Semiconductor substrate 100.In the present embodiment, with the first transistor P1, described
Second transistor P2, third transistor P3 and the 4th transistor P4 are to illustrate exemplified by PMOS transistor.Wherein, it is described
The first transistor P1 is including the first drain D 1 in Semiconductor substrate 100, the first source S 1 and positioned at first source
First choice grid SG1 in the Semiconductor substrate 100 between pole S1 and first drain D 1.The second transistor
The second source S 1 ' that P2 includes being located in the Semiconductor substrate 100, the second drain D 1 ', positioned at second source S 1 ' and
The first floating gate FG1 in the Semiconductor substrate 100 between second drain D 1 ' and positioned at first floating gate
The 3rd drain electrode D2 that the first control gate CG1 on FG1, the third transistor P3 include being located in Semiconductor substrate 100, the
Three source Ss 2 and positioned at the 3rd source S 2 and it is described 3rd drain electrode D2 between the Semiconductor substrate 100 on second
Selection gate SG2.The 4th transistor P4 includes the 4th drain D 2 ', the 4th source electrode being located in the Semiconductor substrate 100
The second floating gate on S2 ', the Semiconductor substrate 100 between the 4th source S 2 ' and the 4th drain D 2 '
FG2 and the second control gate CG2 on the second floating gate FG2.
It is understood that the first transistor P1 the first source S 1 and second transistor P2 the second drain D 1 ' shares
Identical doped region in Semiconductor substrate 100, third transistor P3 the 3rd source S 2 and the 4th transistor P4 the 4th drain electrode
Identical doped region in D2 common semiconductors substrate 100 ', the of second transistor P2 the second source S 1 ' and the 4th transistor
Identical doped region in the common semiconductor substrate 100 of four source S 2 '.
With reference to shown in figure 3.Grid (first choice grid SG1) the connection selection grid polar curve SG of the first transistor P1,
The first transistor P1 source electrode (the first source S 1) connects the drain electrode (the second drain D 1 ') of the second transistor P2, and first is brilliant
Body pipe P1 drain electrode (the first drain D 1) connects the first bit line BL1, grid (the first control gate of the second transistor P2
Pole CG1) connect the first wordline WL1, second transistor P2 source electrode (the second source S 1 ') connection source electrode line SL.Described 3rd is brilliant
Body pipe P3 grid (the second selection gate SG2) connects the selection grid polar curve SG, third transistor P3 source electrode (the 3rd source electrode
S2 the drain electrode (the 4th drain D 2 ') of the 4th transistor P4, third transistor P3 drain electrode (the 3rd drain electrode D2) connection) are connected
The second bit line BL2, the 4th transistor P4 grid connect the second wordline WL2, the 4th transistor P4 source electrode the (the 4th
Source S 2 ') the connection source electrode line SL.
In the present invention, the logic state of the first sub- memory cell 11 and the second sub- memory cell 12 is on the contrary, i.e.
When being write to memory cell so that the logic state of the first sub- memory cell 12 of memory cell 11 and second is on the contrary, so as to the
One sub- 11 and second sub- memory cell 12 of memory cell is respectively logical one or logical zero so that the first bit line BL1 and second
Electric current on bit line BL2 is different, and the first bit line BL1 is shown into institute compared with the electric current of the second bit line BL2
State the logic state of memory cell.In the present invention, the first bit line BL1 and the second bit line BL2 are respectively connected in a comparator
Different inputs, comparator determine the logic shape of memory cell according to the size of the first bit line BL1 and the second bit line BL2 electric current
State.Wherein, if the first sub- memory cell 11 is logical zero, the second sub- memory cell 12 is logical one, then described
First bit line BL1 electric current is more than the electric current of the second bit line BL2, and the memory cell is logical zero.If first son
Memory cell 11 is logical one, and the second sub- memory cell 12 is logical zero, then the electric current of the first bit line BL1 is less than
The electric current of the second bit line BL2, the memory cell are logical one.
Accordingly, with reference to shown in figure 4, the present invention also provides a kind of memory, includes the said memory cells of array distribution
10 and comparator (not shown), the comparator there is at least two inputs and an output end, two are described defeated
Enter end and connect the first bit line and the second bit line respectively, and according to the size of current of first bit line and second bit line, it is defeated
Go out the logic state of the memory cell.In the present embodiment, the first transistor P1 of same row drain electrode connection same bit line,
For example, BL1, BL1n, the grid of the second transistor P2 in the memory cell of same row connects with third transistor P3 grid
Same selection grid polar curve, for example, SG, SGn.The third transistor P3 of same row drain electrode connection same bit line, for example,
BL2, BL2n, the second transistor P2 of same row grid connection same wordline, for example, WL1, WLn, the 4th of same row is brilliant
Body pipe P4 grid connects same wordline, for example, WL2, WL2n, with the second transistor in the memory cell of a line source electrode and
The source electrode connection same source electrode line of 4th transistor, for example, SL1, SL2, SL3, SL4.Two inputs difference of comparator
BL1 and BL2 is connected, or connects BL1n and BL2n respectively, the electric current on two bit lines is compared, determines patrolling for memory cell
The state of collecting.
Specifically, if the first sub- memory cell 11 is logical zero, the second sub- memory cell 12 is logical one, then described
One bit line BL1 electric current is more than the electric current of the second bit line BL2, and the comparator exports the logic shape of the memory cell 10
State " 0 ".If the first sub- memory cell 11 is logical one, the second sub- memory cell 12 is logical zero, then the first bit line BL1
Electric current be less than the electric current of the second bit line BL2, the comparator exports the logic state " 1 " of the memory cell.
In summary, in the memory cell of offer of the invention and memory, the first son that memory cell includes connection is deposited
The logic state of storage unit and the second sub- memory cell, the first sub- memory cell and the second sub- memory cell on the contrary,
When the logic state to memory cell is read out, by with the electric current of first the first bit line being connected from memory and with
Two are compared from the electric current of the second bit line of memory connection, are drawn according to the size of the first bit line and the electric current of the second bit line
The logic state of the memory cell.In the memory cell reading process of the present invention, it is not necessary to which reference current, memory cell are read
Current intervals it is bigger, shorten the time of reading, improve the reliability of reading.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (12)
- A kind of 1. memory cell, it is characterised in that including：First sub- memory cell, including the first transistor and second transistor, the grid connection selection grid of the first transistor Polar curve, source electrode connect the drain electrode of the second transistor, and drain electrode connects first bit line, and the grid of the second transistor connects Connect the first wordline, source electrode connection source electrode line；Second sub- memory cell, including third transistor and the 4th transistor, the grid of the third transistor connect the choosing Gate line is selected, source electrode connects the drain electrode of the 4th transistor, and drain electrode connects second bit line, the grid of the 4th transistor Pole connects the second wordline, and source electrode connects the source electrode line；Wherein, the logic state of the described first sub- memory cell and the second sub- memory cell is opposite.
- 2. memory cell as claimed in claim 1, it is characterised in that by first bit line and the electric current of second bit line It is compared, draws the logic state of the memory cell.
- 3. memory cell as claimed in claim 2, it is characterised in that described if the first sub- memory cell is logical zero Second sub- memory cell is logical one, then the electric current of first bit line is more than the electric current of second bit line, and the storage is single Member is logical zero.
- 4. memory cell as claimed in claim 2, it is characterised in that described if the first sub- memory cell is logical one Second sub- memory cell is logical zero, then the electric current of first bit line is less than the electric current of second bit line, and the storage is single Member is logical one.
- 5. memory cell as claimed in claim 1, it is characterised in that the first transistor, the second transistor, described Third transistor and the 4th transistor are PMOS transistor.
- 6. memory cell as claimed in claim 1, it is characterised in that the first transistor includes being located in Semiconductor substrate The first source electrode, first drain electrode and positioned at first source electrode and it is described first drain electrode between the Semiconductor substrate on First choice grid.
- 7. memory cell as claimed in claim 1, it is characterised in that the second transistor includes serving as a contrast positioned at the semiconductor The second source electrode in bottom, the second drain electrode, in the Semiconductor substrate between second source electrode and second drain electrode The first floating gate and the first control gate in first floating gate.
- 8. memory cell as claimed in claim 1, it is characterised in that the third transistor includes being located in Semiconductor substrate The 3rd source electrode, the 3rd drain electrode and positioned at the 3rd source electrode and it is described 3rd drain electrode between the Semiconductor substrate on Second selection gate.
- 9. memory cell as claimed in claim 1, it is characterised in that the 4th transistor includes serving as a contrast positioned at the semiconductor The 4th source electrode in bottom, the 4th drain electrode, in the Semiconductor substrate between the 4th source electrode and the 4th drain electrode The second floating gate and the second control gate in second floating gate.
- A kind of 10. memory, it is characterised in that including：The memory cell as described in any one in claim 1~9 of array distribution；Comparator, has at least two inputs and an output end, and two inputs connect the first bit line and respectively Two bit lines, and according to the size of current of first bit line and second bit line, export the logic state of the memory cell.
- 11. memory as claimed in claim 10, it is characterised in that if the first sub- memory cell is logical zero, the second son is deposited Storage unit is logical one, then the electric current of first bit line is more than the electric current of second bit line, described in comparator output The logic state " 0 " of memory cell.
- 12. memory as claimed in claim 10, it is characterised in that if the first sub- memory cell is logical one, the second son is deposited Storage unit is logical zero, then the electric current of first bit line is less than the electric current of second bit line, described in comparator output The logic state " 1 " of memory cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610485907.0A CN107527641A (en) | 2016-06-22 | 2016-06-22 | Memory cell and memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610485907.0A CN107527641A (en) | 2016-06-22 | 2016-06-22 | Memory cell and memory |
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| Publication Number | Publication Date |
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| CN107527641A true CN107527641A (en) | 2017-12-29 |
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| CN201610485907.0A Pending CN107527641A (en) | 2016-06-22 | 2016-06-22 | Memory cell and memory |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110491423A (en) * | 2019-08-12 | 2019-11-22 | 北京航空航天大学 | A kind of data reading circuit and method of non-volatile memory |
| CN111091860A (en) * | 2019-12-26 | 2020-05-01 | 普冉半导体（上海）有限公司 | EEPROM memory |
| CN115985375A (en) * | 2022-12-29 | 2023-04-18 | 珠海创飞芯科技有限公司 | Differential OTP memory cell circuit and related equipment |
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| CN105654987A (en) * | 2016-03-02 | 2016-06-08 | 深圳市芯飞凌半导体有限公司 | SONOS (silicon-oxide-nitride-oxide-silicon) structural EEPROM (electrically erasable programmable read-only memory) and memory array and operation method thereof, and SONOS device |
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| US7916535B2 (en) * | 2004-01-09 | 2011-03-29 | Broadcom Corp. | Data encoding approach for implementing robust non-volatile memories |
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