CN107528557B

CN107528557B - A data-driven operational amplifier

Info

Publication number: CN107528557B
Application number: CN201710801461.2A
Authority: CN
Inventors: 魏琦; 周斌; 李享; 陈志勇; 张嵘
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2017-09-07
Filing date: 2017-09-07
Publication date: 2021-03-02
Anticipated expiration: 2037-09-07
Also published as: CN107528557A

Abstract

The embodiment of the invention discloses a data-driven operational amplifier, which comprises: the circuit comprises an N-type complementary input circulating folding transconductance operational amplifier circuit and a P-type complementary input circulating folding transconductance operational amplifier circuit which are connected with each other, and an operational amplifier bias circuit driven by data; the data-driven operational amplifier bias circuit includes an input differential signal comparator; the input differential signal comparator is used for detecting the input differential signal, increasing the bias current of the circuit when the input differential signal is larger than or equal to the opening threshold value of the input differential signal comparator, and keeping the bias current of the circuit unchanged when the input differential signal is smaller than the opening threshold value of the input differential signal comparator. And the current of the amplifier can be dynamically adjusted according to application requirements, and the comparator opens a threshold value and the speed of the comparator to control a working window of large current. Through the scheme of the embodiment, the speed of the high-performance switched capacitor circuit is improved, the power consumption is reduced, and the yield is improved.

Description

Data-driven operational amplifier

Technical Field

The embodiment of the invention relates to a super large scale integrated circuit design technology in the fields of microelectronics and solid electronics, in particular to a data-driven operational amplifier.

Background

The operational amplifier is one of the most important modules of many analog circuits, is widely applied to analog signal processing circuits such as analog-to-digital conversion circuits and filters, and generally determines the indexes such as precision, speed and power consumption which can be achieved by a high-performance switched capacitor circuit. In a switched capacitor circuit, the load is usually of a pure capacitance nature, and a single-stage operational transconductance amplifier OTA is superior to a multi-stage operational amplifier. Therefore, the conventional folded operational transconductance amplifier is widely used. However, the conventional folded OTA has the disadvantages of slow speed and large power consumption, and especially when the load capacitance is large, the speed of the operational amplifier becomes a major bottleneck limiting the speed of the switched capacitor circuit.

Disclosure of Invention

In order to solve the above technical problems, embodiments of the present invention provide a data-driven operational amplifier, which can increase the speed of a high-performance switched capacitor circuit, reduce power consumption, and increase yield.

To achieve the object of the embodiments of the present invention, the embodiments of the present invention provide a data-driven operational amplifier, including: the circuit comprises an N-type complementary input circulating folding transconductance operational amplifier circuit and a P-type complementary input circulating folding transconductance operational amplifier circuit which are connected with each other, and an operational amplifier bias circuit driven by data; the data-driven operational amplifier bias circuit includes an input differential signal comparator;

the input differential signal comparator is used for detecting an input differential signal, increasing the bias current of the circuit when the input differential signal is larger than or equal to the opening threshold of the input differential signal comparator, and keeping the bias current of the circuit unchanged when the input differential signal is smaller than the opening threshold of the input differential signal comparator.

Optionally, the N-type and P-type complementary input circularly folded transconductance operational amplifier circuit includes:

the N-type complementary input differential pair unit comprises an N-type complementary input differential pair unit, and an N-type bias voltage transistor unit, an N-type bias tail current transistor unit and an N-type cascode transistor pair unit which are connected with the N-type complementary input differential pair unit; and the number of the first and second groups,

the P-type complementary input differential pair unit comprises a P-type complementary input differential pair unit, and a P-type bias voltage transistor unit, a P-type bias tail current transistor unit and a P-type cascode transistor pair unit which are connected with the P-type complementary input differential pair unit.

Alternatively,

the N-type complementary input differential pair cell includes: the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the gates of the first NMOS transistor and the second NMOS transistor are connected with a first differential signal VINN in the input differential signals; the grids of the third NMOS tube and the fourth NMOS tube are connected with a second differential signal VINP in the input differential signals;

the N-type bias voltage transistor unit includes: a fifth NMOS transistor; and the grid electrode of the fifth NMOS tube is connected with a first bias voltage, the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is connected with the source electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube.

Alternatively,

the P-type complementary input differential pair cell includes: a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube and a twelfth PMOS tube; the gates of the ninth PMOS tube and the tenth PMOS tube are both connected with the first differential signal VINN; the grids of the eleventh PMOS tube and the twelfth PMOS tube are both connected with the second differential signal VINP;

the P-type biased tail current transistor cell includes: the PMOS transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor; the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and then connected with the drain electrode of the fourth NMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and then connected with the drain electrode of the second NMOS tube, and the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected with power supply voltage;

the P-type cascode transistor pair unit includes: a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube and then connected with a second bias voltage; the grid electrode of the seventh PMOS tube is connected with the grid electrode of the eighth PMOS tube and then is also connected with the second bias voltage; the source electrode of the fifth PMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the sixth PMOS tube is connected with the drain electrode of the third PMOS tube, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the seventh PMOS tube is connected with the drain electrode of the first NMOS tube and then connected with the drain electrode of the first PMOS tube, and the source electrode of the eighth PMOS tube is connected with the drain electrode of the third NMOS tube and then connected with the drain electrode of the fourth PMOS tube;

the P-type bias voltage transistor unit includes: a thirteenth PMOS tube; and the grid electrode of the thirteenth PMOS tube is connected with the common-mode control signal, the source electrode of the thirteenth PMOS tube is connected with the power supply voltage, and the drain electrode of the thirteenth PMOS tube is connected with the source electrodes of the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube and the twelfth PMOS tube.

Alternatively,

the N-type biased tail current transistor cell includes: a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the grid electrode of the sixth NMOS tube is connected with the grid electrode of the seventh NMOS tube and then connected with the drain electrode of the twelfth PMOS tube, the grid electrode of the eighth NMOS tube is connected with the grid electrode of the ninth NMOS tube and then connected with the drain electrode of the tenth PMOS tube, and the source electrodes of the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube are grounded;

the N-type cascode transistor pair unit includes: a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor; the grid electrode of the tenth NMOS tube is connected with the grid electrode of the eleventh NMOS tube and then connected with a third bias voltage, the grid electrode of the twelfth NMOS tube is connected with the grid electrode of the thirteenth NMOS tube and then also connected with the third bias voltage, the source electrode of the tenth NMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the eleventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, the drain electrode of the tenth NMOS tube is connected with the drain electrode of the twelfth PMOS tube, the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the tenth PMOS tube, the source electrode of the twelfth NMOS tube is connected with the drain electrode of the ninth PMOS tube and then connected with the drain electrode of the sixth NMOS tube, and the source electrode of the thirteenth NMOS tube is connected with the drain electrode of the eleventh PMOS tube and then connected with the drain electrode of the ninth NMOS tube.

Alternatively,

the drain electrode of the seventh PMOS tube is connected with the drain electrode of the twelfth NMOS tube to output a first output differential signal VOUTP, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the thirteenth NMOS tube to output a second output differential signal VOUTN, and the first output differential signal VOUTP and the second output differential signal VOUTN jointly form a fully differential output signal.

Optionally, the data-driven operational amplifier bias circuit comprises: the circuit comprises a bias voltage generating circuit, an input differential signal comparator and a data driving current branch circuit.

Alternatively,

the bias voltage generating circuit includes: a first bias current source, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth NMOS transistor, a twenty-sixth NMOS transistor, a twenty-seventh NMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, and a twenty-seventh PMOS transistor;

the negative electrode of the first bias current source is connected with the power supply voltage, the positive electrode of the first bias current source is connected with the drain electrode of the fourteenth NMOS tube and then connected with the grid electrodes of the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube, the eighteenth NMOS tube, the nineteenth NMOS tube, the twentieth NMOS tube and the twenty-first NMOS tube, the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the fifteenth NMOS tube, the source electrode of the sixteenth NMOS tube is connected with the drain electrode of the seventeenth NMOS tube, the source electrode of the eighteenth NMOS tube is connected with the drain electrode of the nineteenth NMOS tube, the source electrode of the twentieth NMOS tube is connected with the drain electrode of the twenty-first NMOS tube, the drain electrode of the twenty-second NMOS tube is connected with the grid electrode of the twenty-third NMOS tube and the twenty-fourth NMOS tube, and then connected with the drain electrodes of the twenty-third NMOS tube and the twenty-fourth NMOS tube, and then connected with the grid electrodes of the twenty-fifth NMOS tube The source electrodes of the twenty-third NMOS transistor and the twenty-eighth NMOS transistor are connected, the source electrode of the twenty-fourth NMOS transistor and the drain electrode of the twenty-ninth NMOS transistor are connected, the gate electrode of the twenty-eighth NMOS transistor is connected with the first control word, the gate electrode of the twenty-ninth NMOS transistor is connected with the second control word, the gate electrode of the twenty-fifth NMOS transistor and the drain electrode of the twenty-sixth NMOS transistor are connected and then connected with the gate electrode of the twenty-seventh NMOS transistor to serve as the third bias voltage, the drain electrode of the twenty-sixth NMOS transistor and the gate electrode of the twenty-seventh NMOS transistor are connected to serve as the first bias voltage, the source electrode of the twenty-sixth NMOS transistor and the drain electrode of the twenty-seventh NMOS transistor are connected, the fifteenth NMOS transistor, the seventeenth NMOS transistor, the nineteenth NMOS transistor, the twenty-first NMOS transistor, the twenty-seventh NMOS transistor, the twenty-eighth NMOS transistor and the twenty-ninth NMOS transistor are connected, and the gate electrode and the drain electrode of the fourteenth PMOS are connected with the gate electrode of the fifteenth PMOS and the gate electrode of the sixteenth PMOS transistor The source electrode of the fourteenth PMOS tube is connected with the drain electrode of the fifteenth PMOS tube and the drain electrode of the sixteenth PMOS tube and then connected with the source electrode of the seventeenth PMOS tube, the source electrode of the fifteenth PMOS tube is connected with the drain electrode of the twenty sixth PMOS tube, the source electrode of the sixteenth PMOS tube is connected with the drain electrode of the twenty seventh PMOS tube, the grid electrode of the twenty sixth PMOS tube is connected with the third control word, the grid electrode of the twenty seventh PMOS tube is connected with the fourth control word, the grid electrode and the drain electrode of the seventeenth PMOS tube are connected and then connected with the drain electrode of the eighteenth NMOS tube to serve as the second bias voltage, the second bias voltage is connected with the grid electrodes of the eighteenth PMOS tube, the twentieth PMOS tube, the twenty second PMOS tube and the twenty fourth PMOS tube PMOS, the drain electrode of the eighteenth PMOS tube PMOS is connected with the drain electrode of the twentieth NMOS tube PMOS, and the source electrode of the eighteenth PMOS tube drain electrode is connected with the drain electrode of the nineteen, the grid electrode of the nineteenth PMOS tube is connected with the grid electrode of the twenty-first PMOS tube and then connected with the drain electrode of the eighteenth PMOS tube as a fourth bias voltage, the fourth bias voltage is connected with the grid electrodes of the twenty-third PMOS tube and the twenty-fifth PMOS tube, the source electrode of the twentieth PMOS tube is connected with the drain electrode of the twenty-first PMOS tube, the drain electrode of the twentieth PMOS tube is connected with the drain electrode of the twenty-second NMOS tube, the source electrode of the twenty-second PMOS tube is connected with the drain electrode of the twenty-third PMOS tube, the drain electrode of the twenty-second PMOS tube is connected with the drain electrode of the twenty-fifth NMOS tube, the source electrode of the twenty-fourth PMOS tube is connected with the drain electrode of the twenty-fifth PMOS tube, the drain electrode of the twenty-fourth PMOS tube is connected with the drain electrode of the twenty-sixth NMOS tube, the nineteenth PMOS tube, the twenty-third PMOS tube, the twenty-fifth PMOS tube, the twenty, The source electrodes of the twenty-sixth PMOS tube and the twenty-seventh PMOS tube are connected with the power supply voltage;

the input differential signal comparator includes: a first comparator and a second comparator; the negative input end of the first comparator and the positive input end of the second comparator are connected with the first differential signal VINN, the positive input end of the first comparator and the negative input end of the second comparator are connected with the second differential signal VINP, the first comparator outputs a first control signal VC1, and the second comparator outputs a second control signal VC 2;

the data driving current branch includes: a second bias current source, a third bias current source, a thirty-first NMOS transistor, a thirty-second NMOS transistor, a thirty-third NMOS transistor, a thirty-fourth NMOS transistor and a thirty-fifth NMOS transistor;

wherein, the cathode of the second bias current source and the cathode of the third bias current source are connected with the supply voltage, the source of the thirty-first NMOS transistor is connected with the source of the thirty-first NMOS transistor and then connected with the anode of the second bias current source, the gate of the thirty-first NMOS transistor is connected with the first control signal VC1, the gate of the thirty-first NMOS transistor is connected with the second control signal VC2, the drain of the thirty-first NMOS transistor is connected with the drain of the thirty-first NMOS transistor and then connected with the drain of the thirty-fourth NMOS transistor, the gate of the thirty-fourth NMOS transistor is connected with the fifth control word, the source of the thirty-second NMOS transistor is connected with the source of the thirty-third NMOS transistor and then connected with the anode of the third bias current source, the gate of the thirty-second NMOS transistor is connected with the first control signal VC1, and the gate of the thirty-third NMOS transistor is connected with the second control signal VC2, the drain electrode of the thirty-second NMOS tube is connected with the drain electrode of the thirty-third NMOS tube and then connected with the drain electrode of the thirty-fifth NMOS tube, the gate electrode of the thirty-fifth NMOS tube is connected with the sixth control word, and the source electrode of the thirty-fourth NMOS tube and the source electrode of the thirty-fifth NMOS tube are connected with the drain electrode of the fourteenth NMOS tube.

Optionally, the first comparator and the second comparator each comprise: the comparator main circuit and the bias circuit with adjustable bias current;

the comparator main circuit comprises: a thirty-sixth NMOS transistor, a thirty-seventh NMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a forty-first NMOS transistor, a forty-second NMOS transistor, a forty-third NMOS transistor, a forty-fourth NMOS transistor, a forty-fifth NMOS transistor, a forty-sixth NMOS transistor, a forty-seventh NMOS transistor, a forty-eighth NMOS transistor, a twenty-eighth PMOS transistor, a twenty-ninth PMOS transistor, a thirty-eighth PMOS transistor, a thirty-eleventh PMOS transistor, a thirty-second PMOS transistor, a thirty-third PMOS transistor, a thirty-fourth PMOS transistor, a thirty-fifth PMOS transistor, a thirty-sixth PMOS transistor, a thirty-seventh PMOS transistor, a thirty-eighth PMOS transistor, a thirty-ninth PMOS transistor, a forty-first PMOS transistor, a second forty PMOS transistor, and a forty-third PMOS transistor;

the gates of the thirty-sixth and thirty-seventh NMOS transistors are connected to the third differential signal VCN in the input differential signal, the gates of the thirty-eighth and thirty-ninth NMOS transistors are connected to the fourth differential signal VCP in the input differential signal, the gate of the forty-NMOS transistor is connected to the fifth bias voltage, the source is grounded, the drain is connected to the sources of the thirty-sixth, thirty-seventh, thirty-eighth, and thirty-ninth NMOS transistors, the gate of the twenty-eighth PMOS transistor is connected to the gate of the twenty-ninth PMOS transistor and then to the drain of the thirty-ninth NMOS transistor, the source of the twenty-eighth, twenty-ninth, thirty-eighth, and thirty-eleventh PMOS transistors, the gate of the thirty-second PMOS transistor is connected to the gate of the thirty-third PMOS transistor and then to the sixth bias voltage, the gate of the thirty-fourth PMOS transistor is connected to the gate of the thirty-fifth PMOS transistor and then to the sixth bias voltage A source electrode of the thirty-second PMOS transistor is connected to a drain electrode of the twenty-ninth PMOS transistor, a source electrode of the thirty-third PMOS transistor is connected to a drain electrode of the thirty-ninth PMOS transistor, a drain electrode of the thirty-second PMOS transistor is connected to a drain electrode of the thirty-ninth NMOS transistor, a drain electrode of the thirty-third PMOS transistor is connected to a drain electrode of the thirty-seventh NMOS transistor, a source electrode of the thirty-fourth PMOS transistor is connected to a drain electrode of the thirty-sixth NMOS transistor and then connected to a drain electrode of the twenty-eighth PMOS transistor, a source electrode of the thirty-fifth PMOS transistor is connected to a drain electrode of the thirty-eighth NMOS transistor and then connected to a drain electrode of the thirty-eleventh PMOS transistor, gates of the thirty-sixth PMOS transistor and the thirty-seventh PMOS transistor are both connected to the third differential signal VCN, gates of the thirty-eighth PMOS transistor and the thirty-ninth PMOS transistor are both connected to the fourth differential signal VCP, and gates of the forty-first PMOS transistor are connected to the seventh bias voltage, the source electrode of the forty-first PMOS tube is connected with the drain electrode of the forty-second PMOS tube, the source electrode of the forty-first PMOS tube is connected with the drain electrode of the forty-third PMOS tube, the gate electrode of the forty-second PMOS tube is connected with the seventh control word, the gate electrode of the forty-third PMOS tube is connected with the eighth control word, the source electrodes of the forty-second PMOS tube and the forty-third PMOS tube are connected with the power supply voltage, the drain electrodes of the forty-second PMOS tube and the forty-first PMOS tube are connected with the source electrodes of the thirty-sixth PMOS tube, the thirty-seventh PMOS tube, the thirty-eighth PMOS tube and the thirty-ninth PMOS tube, the gate electrode of the forty-first NMOS tube is connected with the gate electrode of the forty-second NMOS tube and then connected with the drain electrode of the thirty-ninth PMOS tube, the gate electrode of the forty-third NMOS tube is connected with the gate electrode of the forty-fourth NMOS tube and then connected with the drain electrode of the thirty-seventh PMOS tube, the forty NMOS tube, the forty-second NMOS tube, the source electrodes of the forty-third NMOS transistor and the forty-fourth NMOS transistor are grounded, the gate electrode of the forty-fifth NMOS transistor is connected to the gate electrode of the forty-sixth NMOS transistor and then connected to an eighth bias voltage, the gate electrode of the forty-seventh NMOS transistor is connected to the gate electrode of the forty-eighth NMOS transistor and then also connected to the eighth bias voltage, the source electrode of the forty-fifth NMOS transistor is connected to the drain electrode of the forty-second NMOS transistor, the source electrode of the forty-sixth NMOS transistor is connected to the drain electrode of the forty-third NMOS transistor, the drain electrode of the forty-fifth NMOS transistor is connected to the drain electrode of the thirty-ninth PMOS transistor, the drain electrode of the forty-sixth NMOS transistor is connected to the drain electrode of the thirty-seventh PMOS transistor, the source electrode of the forty-seventh NMOS transistor is connected to the drain electrode of the thirty-sixth PMOS transistor and then to the drain electrode of the forty-first NMOS transistor, and the source electrode of the forty-eighth NMOS transistor is connected to the drain electrode of the thirty-eighth PMOS transistor and then to the drain electrode of the forty-fourth NMOS transistor, the drain of the forty-eighth NMOS transistor is connected with the drain of the thirty-fifth PMOS transistor and then connected with the gate of the thirty-sixth PMOS transistor and the gate of the thirty-first PMOS transistor, and the forty-seventh NMOS transistor is connected with the thirty-fourth PMOS transistor to serve as a comparator output VCOUT;

the bias circuit with adjustable bias current comprises: a fourth bias current source, a fifth bias current source, a forty-ninth NMOS transistor, a fifty-first NMOS transistor, a fifty-second NMOS transistor, a fifty-third NMOS transistor, a fifty-fourth NMOS transistor, a fifty-fifth NMOS transistor, a fifty-sixth NMOS transistor, a fifty-seventh NMOS transistor, a fifty-eighth NMOS transistor, a fifty-ninth NMOS transistor, a sixty-first NMOS transistor, a sixty-second NMOS transistor, a sixty-third NMOS transistor, a forty-fourth PMOS transistor, a forty-fifth PMOS transistor, a forty-sixth PMOS transistor, a forty-seventh PMOS transistor, a forty-eighth PMOS transistor, a forty-ninth PMOS transistor, a fifty-fifth PMOS transistor, a fifty-third PMOS transistor, and a fifty-fourth PMOS transistor;

wherein, the negative pole of the fourth bias current source and the negative pole of the fifth bias current source are connected with the power voltage, the drain of the forty-ninth NMOS transistor is connected with the gates of the forty-ninth NMOS transistor, the fifty-first NMOS transistor, the fifty-second NMOS transistor, the fifty-third NMOS transistor, the fifty-fourth NMOS transistor, the fifty-fifth NMOS transistor and the fifty-sixth NMOS transistor, the source of the forty-ninth NMOS transistor is connected with the drain of the fifty-NMOS transistor, the source of the fifty-first NMOS transistor is connected with the drain of the fifty-second NMOS transistor, the source of the fifty-third NMOS transistor is connected with the drain of the fifty-fourth NMOS transistor, the source of the fifty-fifth NMOS transistor is connected with the drain of the fifty-sixth NMOS transistor, the drain of the fifty-seventh NMOS transistor is connected with the gate, and then is connected with the gate of the eighth NMOS transistor, and the source of the seventh NMOS transistor is connected with the drain of the fifty-eighth NMOS transistor, then is connected with the source of the fifty-ninth NMOS transistor, a gate and a drain of the fifty-ninth NMOS transistor are connected to each other and then connected to a gate of the sixty NMOS transistor as the eighth bias voltage, a drain of the sixty NMOS transistor is connected to a gate of the sixty NMOS transistor as the fifth bias voltage, a source of the sixty NMOS transistor is connected to a drain of the sixty NMOS transistor, a source of the fifty NMOS transistor is connected to a drain of the sixty first NMOS transistor, a gate and a drain of the fifty NMOS transistor, the fifty-second NMOS transistor, the fifty-fourth NMOS transistor, the fifty-sixth NMOS transistor, the fifty-eighth NMOS transistor, and the sixty first NMOS transistor are connected to ground, a gate of the forty-fourth PMOS transistor is connected to a gate and a drain of the forty-fifth PMOS transistor and then connected to a drain of the fifty-sixth PMOS transistor, a source of the forty-fourth PMOS transistor is connected to a drain of the fifth PMOS transistor and then connected to a drain of the forty-sixth PMOS transistor, and a gate and a drain of the forty-sixth PMOS transistor are connected to a drain of the fifty-third NMOS transistor as the sixth bias voltage, the second bias voltage is connected with the gates of the forty-seventh, forty-ninth, fifty-first and fifty-third PMOS transistors, the drain of the forty-seventh PMOS transistor is connected with the drain of the fifty-fifth NMOS transistor, the source of the forty-seventh PMOS transistor is connected with the drain of the forty-eighth PMOS transistor, the gate of the forty-eighth PMOS transistor is connected with the gate of the fifty-fifth PMOS transistor and then connected with the drain of the forty-seventh PMOS transistor as the seventh bias voltage, the fourth bias voltage is connected with the gates of the fifty-second and fifty-fourth PMOS transistors, the source of the forty-ninth PMOS transistor is connected with the drain of the fifty-fifth PMOS transistor, the drain of the forty-ninth PMOS transistor is connected with the drain of the fifty-seventh NMOS transistor, the source of the first PMOS transistor is connected with the drain of the fifty-second PMOS transistor, and the drain of the fifty-ninth PMOS transistor is connected with the drain of the fifty-NMOS transistor, the source electrode of the fifty-third PMOS tube is connected with the drain electrode of the fifty-fourth PMOS tube, the drain electrode of the fifty-third PMOS tube is connected with the drain electrode of the sixty NMOS tube, the source electrodes of the forty-fifth PMOS tube, the forty-eighth PMOS tube, the fifty-fifth PMOS tube, the fifty-second PMOS tube and the fifty-fourth PMOS tube are connected with the power supply voltage, the positive electrode of the fourth bias current source is connected with the drain electrode of the sixty-second NMOS tube, the gate electrode of the sixty-second NMOS tube is connected with the ninth control word, the positive electrode of the fifth bias current source is connected with the drain electrode of the sixty-third NMOS tube, the gate electrode of the sixty-third NMOS tube is connected with the tenth control word, and the source electrodes of the sixty-third NMOS tube and the sixty-third NMOS tube are connected with the drain electrode of the forty-ninth NMOS tube.

Optionally, the N-type and P-type complementary input circularly folded transconductance operational amplifier circuit further includes: a common mode feedback circuit; the common mode feedback circuit includes: the full differential signal and common mode signal input transistor unit, the bias voltage transistor unit and the common mode feedback control signal generation unit;

the fully differential signal and common mode signal input transistor unit includes: sixty-fourth, sixty-fifth, sixty-sixth, and sixty-seventh NMOS transistors;

the grid electrode of the sixty-fourth NMOS transistor is connected with the second output differential signal VOUTN, the grid electrode of the sixty-seventh NMOS transistor is connected with the first output differential signal VOUTP, and the grid electrode of the sixty-fifth NMOS transistor is connected with the grid electrode of the sixty-sixth NMOS transistor and then connected with a common-mode input voltage VCM;

the bias voltage transistor unit includes: sixty eight NMOS transistors and sixty nine NMOS transistors;

the drain electrode of the sixty-eight NMOS tube is connected with the source electrode of the sixty-four NMOS tube and the source electrode of the sixty-five NMOS tube, the drain electrode of the sixty-nine NMOS tube is connected with the source electrode of the sixty-six NMOS tube and the source electrode of the sixty-seven NMOS tube, the grid electrode of the sixty-eight NMOS tube is connected with the grid electrode of the sixty-nine NMOS tube and then connected with the first bias voltage, and the source electrode of the sixty-eight NMOS tube and the source electrode of the sixty-nine NMOS tube are grounded;

the common mode feedback control signal generating unit includes: a fifty-fifth PMOS (P-channel metal oxide semiconductor) tube, a fifty-sixth PMOS tube, and a first resistor R1 and a second resistor R2 which are connected in series with each other;

the grid electrode of the fifty-fifth PMOS tube is connected with the grid electrode of the fifty-sixth PMOS tube and then connected with the serial end of the first resistor R1 and the second resistor R2, the drain electrode of the fifty-fifth PMOS tube is connected with the non-serial end of the first resistor R1 and then connected with the drain electrode of the sixty-fourth NMOS tube and the drain electrode of the sixty-seventh NMOS tube, and is connected with the common mode control signal VCMFB after being connected, the drain electrode of the fifty-sixth PMOS tube is connected with the non-serial end of the second resistor R2 and then connected with the drain electrode of the sixty-fifth NMOS tube and the drain electrode of the sixty-sixth NMOS tube, and the source electrode of the fifty-fifth PMOS tube and the source electrode of the fifty-sixth PMOS tube are connected with the power supply voltage.

The embodiment of the invention comprises the following steps: the circuit comprises an N-type complementary input circulating folding transconductance operational amplifier circuit and a P-type complementary input circulating folding transconductance operational amplifier circuit which are connected with each other, and an operational amplifier bias circuit driven by data; the data-driven operational amplifier bias circuit includes an input differential signal comparator; the input differential signal comparator is used for detecting an input differential signal, increasing the bias current of the circuit when the input differential signal is larger than or equal to the opening threshold of the input differential signal comparator, and keeping the bias current of the circuit unchanged when the input differential signal is smaller than the opening threshold of the input differential signal comparator. And the current of the amplifier can be dynamically adjusted according to application requirements, and the comparator opens a threshold value and the speed of the comparator to control a working window of large current. Through the scheme of the embodiment, the speed of the high-performance switched capacitor circuit is improved, the power consumption is reduced, and the yield is improved.

Additional features and advantages of embodiments of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of the invention. The objectives and other advantages of the embodiments of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the examples of the application do not constitute a limitation of the embodiments of the invention.

FIG. 1 is a schematic diagram of a data-driven operational amplifier according to an embodiment of the present invention;

FIG. 2 is a circuit schematic of a first comparator and a second comparator according to an embodiment of the present invention;

fig. 3 is a circuit diagram of a common mode feedback circuit according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

In the embodiment of the invention, in order to overcome the defects of low speed and large power consumption of the current folding OTA (single-stage operational transconductance amplifier), the embodiment of the invention designs a data-driven operational amplifier. The embodiment of the invention detects the input differential signal through the comparator, increases the bias current of the circuit to improve the speed of the amplifier when the input differential signal is greater than the opening threshold of the comparator, and does not increase the bias current of the circuit when the input differential signal is less than the opening threshold of the comparator, thereby saving power consumption. The embodiment of the invention can improve the speed of high-performance switched capacitor circuits such as a high-performance analog-to-digital converter, a filter and the like, avoids the compromise relationship between the static power consumption, the maximum output current and the cross-over distortion of the traditional AB class amplifier, and has the advantages of high speed and high linearity and overcomes the defect of large static bias current compared with the traditional A class amplifier.

In an embodiment of the present invention, fig. 1 shows a complementary input circular folded transconductance operational amplifier and a bias circuit with a data driving branch. The complementary input circular folding OTA is different from the conventional OTA, and adopts NMOS (N-channel Metal-Oxide-Semiconductor) tube and PMOS (P-channel Metal-Oxide-Semiconductor) tube branch complementary input.

In the embodiment of the present invention, in fig. 1, the transistors P1a, P1b, P2a, P2b are P-type input devices, and N1a, N1b, N2a, N2b are N-type input devices. VINN and VINP are input differential signals, VINN is applied to the gates of P1a, P1b, N1a, N1b, and VINP is applied to the gates of P2a, P2b, N2a, N2 b. Transistor P0 provides bias current for P-type input branches P1a, P1b, P2a, P2b, and transistor N0 provides bias current for N-type input branches N1a, N1b, N2a, N2 b. Transistors N5, N6, N7, N8 are biased tail current transistors of the P-type input branch, and transistors P5, P6, P7, P8 are biased tail current transistors of the N-type input branch. Transistors N3, N4, N9, N10 are a cascode transistor pair for the P-type input branch, and transistors P3, P4, P9, P10 are a cascode transistor pair for the N-type input branch. The drain of transistor P9 is connected to the drain of transistor N9 to provide one differential output VOUTP, and the drain of transistor P10 is connected to the drain of transistor N10 to provide the other differential output VOUTN. VOUTP and VOUTN constitute a fully differential output. The bias voltage of the transistor N0 is Vb1, the bias voltages of the transistors N3, N4, N9 and N10 are Vb2, the bias voltages of the transistors P3, P4, P9 and P10 are Vb3, and the bias voltage of the transistor P0 is a common mode control signal VCMFB generated in the common mode feedback circuit. The complementary circular folding OTA adopted by the invention has the advantages that the cascode transistors N9 and N10 of the P-type input branch and the cascode transistors P9 and P10 of the N-type input branch share the same current, so that the current of each branch is fully utilized, and the unit gain bandwidth GBW of the operational amplifier is improved. The connection relationship of the respective units in fig. 1 will be described in detail below.

The N-type complementary input differential pair cell includes: the first NMOS transistor (N1a), the second NMOS transistor (N1b), the third NMOS transistor (N2a) and the fourth NMOS transistor (N2b), wherein the gates of the first NMOS transistor (N1a) and the second NMOS transistor (N1b) are connected with one differential signal VINN (namely the first differential signal VINN) in the input fully differential signals, and the gates of the third NMOS transistor (N2a) and the fourth NMOS transistor (N2b) are connected with the other differential signal VINP (the second differential signal VINP) in the input fully differential signals;

the N-type bias voltage transistor unit includes: and the grid electrode of the fifth NMOS tube (N0) is connected with the first bias voltage (Vb1), the source electrode of the fifth NMOS tube (N0) is Grounded (GND), and the drain electrode of the fifth NMOS tube (N0) is connected with the source electrodes of the first NMOS tube (N1a), the second NMOS tube (N1b), the third NMOS tube (N2a) and the fourth NMOS tube (N2 b).

The P-type complementary input differential pair cell includes: a ninth PMOS tube (P1a), a tenth PMOS tube (P1b), an eleventh PMOS tube (P2a) and a twelfth PMOS tube (P2 b); the gates of the ninth PMOS transistor (P1a) and the tenth PMOS transistor (P1b) are both connected to one of the input fully differential signals VINN, and the gates of the eleventh PMOS transistor (P2a) and the twelfth PMOS transistor (P2b) are both connected to the other one of the input fully differential signals VINP.

The P-type biased tail current transistor cell includes: a first PMOS tube (P5), a second PMOS tube (P6), a third PMOS tube (P7) and a fourth PMOS tube (P8); the grid electrode of the first PMOS tube (P5) is connected with the grid electrode of the second PMOS tube (P6) and then connected with the drain electrode of the fourth NMOS tube (N2b), the grid electrode of the third PMOS tube (P7) is connected with the grid electrode of the fourth PMOS tube (P8) and then connected with the drain electrode of the second NMOS tube (N1b), and the source electrodes of the first PMOS tube (P5), the second PMOS tube (P6), the third PMOS tube (P7) and the fourth PMOS tube (P8) are connected with the power supply Voltage (VDD).

The P-type cascode transistor pair unit includes: a fifth PMOS (P3), a sixth PMOS (P4), a seventh PMOS (P9) and an eighth PMOS (P10); wherein, the grid of the fifth PMOS transistor (P3) is connected with the grid of the sixth PMOS transistor (P4) and then connected with the second bias voltage (Vb3), the grid of the seventh PMOS transistor (P9) is connected with the grid of the eighth PMOS transistor (P10) and then connected with the second bias voltage (Vb3), the source of the fifth PMOS transistor (P3) is connected with the drain of the second PMOS transistor (P6), the source of the sixth PMOS transistor (P4) is connected with the drain of the third PMOS transistor (P7), the drain of the fifth PMOS transistor (P3) is connected with the drain of the fourth NMOS transistor (N2b), the drain of the sixth PMOS transistor (P4) is connected with the drain of the second NMOS transistor (N1b), the source of the seventh PMOS transistor (P9) is connected with the drain of the first NMOS transistor (N1a) and then connected with the drain of the first PMOS transistor (P5), the source electrode of the eighth PMOS tube (P10) is connected with the drain electrode of the third NMOS tube (N2a) and then connected with the drain electrode of the fourth PMOS tube (P8).

The P-type bias voltage transistor unit includes: a thirteenth PMOS tube (P0); the gate of the thirteenth PMOS tube (P0) is connected with a common mode control signal (VCMFB), the source is connected with a power Voltage (VDD), and the drain is connected with the sources of the ninth PMOS tube (P1a), the tenth PMOS tube (P1b), the eleventh PMOS tube (P2a) and the twelfth PMOS tube (P2 b).

The N-type biased tail current transistor cell includes: a sixth NMOS transistor (N5), a seventh NMOS transistor (N6), an eighth NMOS transistor (N7) and a ninth NMOS transistor (N8); the grid electrode of the sixth NMOS tube (N5) is connected with the grid electrode of the seventh NMOS tube (N6) and then connected with the drain electrode of the twelfth PMOS tube (P2b), the grid electrode of the eighth NMOS tube (N7) is connected with the grid electrode of the ninth NMOS tube (N8) and then connected with the drain electrode of the tenth PMOS tube (P1b), and the source electrodes of the sixth NMOS tube (N5), the seventh NMOS tube (N6), the eighth NMOS tube (N7) and the ninth NMOS tube (N8) are Grounded (GND).

The N-type cascode transistor pair unit includes: a tenth NMOS transistor (N3), an eleventh NMOS transistor (N4), a twelfth NMOS transistor (N9) and a thirteenth NMOS transistor (N10); wherein, the grid of the tenth NMOS transistor (N3) is connected to the grid of the eleventh NMOS transistor (N4) and then connected to the third bias voltage (Vb2), the grid of the twelfth NMOS transistor (N9) is connected to the grid of the thirteenth NMOS transistor (N10) and then connected to the third bias voltage (Vb2), the source of the tenth NMOS transistor (N3) is connected to the drain of the seventh NMOS transistor (N6), the source of the eleventh NMOS transistor (N4) is connected to the drain of the eighth NMOS transistor (N7), the drain of the tenth NMOS transistor (N3) is connected to the drain of the twelfth PMOS transistor (P2b), the drain of the eleventh NMOS transistor (N4) is connected to the drain of the tenth PMOS transistor (P1b), the source of the twelfth NMOS transistor (N9) is connected to the drain of the ninth PMOS transistor (P1a) and then connected to the drain of the sixth NMOS transistor (N5), the source electrode of the thirteenth NMOS tube (N10) is connected with the drain electrode of the eleventh PMOS tube (P2a) and then connected with the drain electrode of the ninth NMOS tube (N8).

The drain electrode of the seventh PMOS tube (P9) is connected with the drain electrode of the twelfth NMOS tube (N9) to output a differential signal (VOUTP), namely a first output differential signal VOUTP; the drain electrode of the eighth PMOS tube (P10) is connected with the drain electrode of the thirteenth NMOS tube (N10) to output another differential signal (VOUTN), namely a second output differential signal VOUTN; the differential signals VOUTP and VOUTN together form a fully differential output signal.

In the embodiment of the invention, the bias circuit of the OTA is different from the conventional bias circuit, and a data driving branch and two comparators are added in addition to the common circuit for providing the bias voltage of the operational amplifier. Transistors M1, M2, M3, M4, M5, M6a, M6b, M7, MK7 constitute an operational amplifier bias main circuit, the gate of transistor M7 is connected with bias voltage Vb 7, the gates of transistors M7 and M7 are connected with bias voltage Vb 7, the gates of transistors M7, M7 and M7 are connected with bias voltage 7, and the gates of transistors M7, M7 and M7 are connected with bias voltage 7. The control words EN3 and EN4 control the on-off of the transistors MK3 and MK4, so that M6a and M6b which are connected in parallel can be selectively switched into the circuit, and the value of the bias voltage Vb3 can be changed. By controlling the on and off of the transistors MK5 and MK6 through control words EN5 and EN6, M17a and M17b which are connected in parallel can be selectively switched into a circuit, and the value of the bias voltage Vb2 can be changed. The current source I1 provides a conventional bias current for the bias circuit. The negative input terminal of the comparator COMP1 and the positive input terminal of the comparator COMP2 are connected to the differential input signal VINN, and the positive input terminal of the comparator COMP1 and the negative input terminal of the comparator COMP2 are connected to the differential input signal VINP. The data driving branch circuit is composed of transistors MS1, MS2, MS3, MS4, MK1 and MK2 and current sources I2 and I3, the gates of the transistors MS1 and MS3 are connected with the output of a comparator COMP1, and the gates of the transistors MS2 and MS4 are connected with the output of a comparator COMP 2. When the input differential signal is large, one of the comparator COMP1 and the comparator COMP2 is triggered to output a high level, so that one of the transistor MS1 and the transistor MS2, and one of the transistor MS3 and the transistor MS4 are turned on accordingly, and the current of the current source I2 or I3 is added to the bias circuit, thereby increasing the speed of the OTA. The control words EN1, EN2 may selectively turn on the transistors MK1, MK2, thereby controlling the magnitude of the data driving branch current. The connection relationship of each circuit in the data-driven operational amplifier bias circuit will be described in detail below.

The bias voltage generating circuit includes: a first bias current source (I1), a fourteenth NMOS transistor (M1), a fifteenth NMOS transistor (M2), a sixteenth NMOS transistor (M3), a seventeenth NMOS transistor (M4), an eighteenth NMOS transistor (M8), a nineteenth NMOS transistor (M9), a twentieth NMOS transistor (M10), a twenty-first NMOS transistor (M11), a twenty-second NMOS transistor (M16), a twenty-third NMOS transistor (M17a), a twenty-fourth NMOS transistor (M17b), a twenty-fifth NMOS transistor (M18), a twenty-sixth NMOS transistor (M23), a twenty-seventh NMOS transistor (M24), a twenty-eighth NMOS transistor (MK5), a twenty-ninth NMOS transistor (MK6), a fourteenth PMOS transistor (M5), a fifteenth PMOS transistor (M6a), a sixteenth PMOS transistor (M6a), a seventeenth PMOS transistor (M a), an eighteenth PMOS transistor (M a), a nineteenth NMOS transistor (M a), a fourteenth PMOS transistor (M a), a twenty-ninth PMOS transistor (M a), a twenty-fifth PMOS transistor (M36, A twenty-fourth PMOS (M21), a twenty-fifth PMOS (M22), a twenty-sixth PMOS (MK3) and a twenty-seventh PMOS (MK 4);

wherein, the negative pole of the first bias current source (I1) is connected with the power Voltage (VDD), the positive pole of the first bias current source (I1) is connected with the drain of the fourteenth NMOS tube (M1) and then connected with the gates of the fourteenth NMOS tube (M1), the fifteenth NMOS tube (M2), the sixteenth NMOS tube (M3), the seventeenth NMOS tube (M4), the eighteenth NMOS tube (M8), the nineteenth NMOS tube (M9), the twentieth NMOS tube (M10) and the twenty-first NMOS tube (M11), the source of the fourteenth NMOS tube (M1) is connected with the drain of the fifteenth NMOS tube (M2), the source of the sixteenth NMOS tube (M3) is connected with the drain of the seventeenth NMOS tube (M84), the source of the eighteenth NMOS tube (M8) is connected with the drain of the nineteenth NMOS tube (M9), the source of the twentieth NMOS tube (M10) is connected with the drain of the twenty-first NMOS tube (M5848), the twenty-second NMOS tube (M4617) is connected with the twenty-second NMOS tube (M a), the source of the twenty-second NMOS tube (M16) is connected with the drains of the twenty-third NMOS tube (M17a) and the twenty-fourth NMOS tube (M17b) and then connected with the source of the twenty-fifth NMOS tube (M18), the source of the twenty-third NMOS tube (M17a) is connected with the drain of the twenty-eighth NMOS tube (MK5), the source of the twenty-fourth NMOS tube (M17b) is connected with the drain of the twenty-ninth NMOS tube (MK6), the gate of the twenty-eighth NMOS tube (MK5) is connected with the first control word (EN5), the gate of the twenty-ninth NMOS tube (MK6) is connected with the second control word (EN6), the gate of the twenty-fifth NMOS tube (M18) is connected with the drain of the twenty-sixth NMOS tube (M23) and then connected with the gate of the twenty-sixth NMOS tube (M3523) as a third bias voltage (Vb2), the drain of the twenty-sixth NMOS tube (M23) is connected with the drain of the seventh NMOS tube (M356) and the source of the twenty-sixth NMOS tube (M3527) is connected with the twenty-eighth NMOS tube (23), a fifteenth NMOS tube (M2), a seventeenth NMOS tube (M4), a nineteenth NMOS tube (M9), a twenty first NMOS tube (M11), a twenty seventh NMOS tube (M24), a twenty eighth NMOS tube (MK5) and a twenty ninth NMOS tube (MK6), wherein the source electrode of the fourteenth PMOS tube (M5) is connected with the drain electrode of the sixteenth NMOS tube (M3) after the grid electrode and the drain electrode of the fourteenth PMOS tube (M6a) are connected with the grid electrode of the sixteenth PMOS tube (M6b), the source electrode of the fourteenth PMOS tube (M5) is connected with the drain electrode of the fifteenth PMOS tube (M6a) and the drain electrode of the sixteenth PMOS tube (M6b) and then connected with the source electrode of the seventeenth PMOS tube (M7), the source electrode of the fifteenth PMOS tube (M6a) is connected with the drain electrode of the twenty sixth PMOS tube (3), the source electrode of the sixteenth PMOS tube (M6) is connected with the source electrode of the seventeenth PMOS tube (M4684), and the source electrode of the twenty fifth PMOS tube (MK3) is connected with the drain electrode of the twenty sixth PMOS tube (EN3), a twenty-seventh PMOS transistor (MK4) has a gate connected to the fourth control word (EN4), a seventeenth PMOS transistor (M7) has a gate and a drain connected to the drain of the eighteenth NMOS transistor (M8) as a second bias voltage (Vb3), the second bias voltage (Vb3) is connected to the gates of the eighteenth PMOS transistor (M12), the twentieth PMOS transistor (M14), the twenty-second PMOS transistor (M19) and the twenty-fourth PMOS transistor (M21), the drain of the eighteenth PMOS transistor (M12) is connected to the drain of the twenty-first PMOS transistor (M10), the source of the eighteenth PMOS transistor (M12) is connected to the drain of the nineteenth PMOS transistor (M13), the gate of the nineteenth PMOS transistor (M13) is connected to the gate of the twenty-first PMOS transistor (M15) and then to the drain of the eighteenth PMOS transistor (M12) as a fourth bias voltage (Vb 84), the gate of the seventeenth PMOS transistor (M4642) is connected to the twenty-fourth bias voltage (M22), the source of a twentieth PMOS tube (M14) is connected with the drain of a twenty-first PMOS tube (M15), the drain of the twentieth PMOS tube (M14) is connected with the drain of the twenty-second NMOS tube (M16), the source of the twentieth PMOS tube (M19) is connected with the drain of a twenty-third PMOS tube (M20), the drain of the twenty-second PMOS tube (M19) is connected with the drain of the twenty-fifth NMOS tube (M18), the source of the twenty-fourth PMOS tube (M21) is connected with the drain of a twenty-fifth PMOS tube (M22), the drain of the twenty-fourth PMOS tube (M21) is connected with the drain of the twenty-sixth NMOS tube (M23), the nineteenth PMOS tube (M13), the twenty-first PMOS tube (M15), the twenty-third PMOS tube (M20), the twenty-fifth PMOS tube (M22), the twenty-sixth PMOS tube (M3) and the source of the seventh PMOS tube (MK4) is connected with the power supply voltage VDD.

The input differential signal comparator includes: two comparators (COMP1, COMP2), a first comparator COMP1 and a second comparator COMP 2; the negative input end of the first comparator (COMP1) and the positive input end of the second comparator (COMP2) are connected with the input differential signal VINN (i.e. the first differential signal VINN), the positive input end of the first comparator (COMP1) and the negative input end of the second comparator (COMP2) are connected with the input differential signal VINP (i.e. the second differential signal VINP), the first comparator (COMP1) outputs the first control signal VC1, and the second comparator (COMP2) outputs the second control signal VC 2.

The data driving current branch includes: a second bias current source (I2), a third bias current source (I3), a thirty-NMOS transistor (MS1), a thirty-eleventh NMOS transistor (MS2), a thirty-second NMOS transistor (MS3), a thirty-third NMOS transistor (MS4), a thirty-fourth NMOS transistor (MK1) and a thirty-fifth NMOS transistor (MK 2);

wherein, the cathode of the second bias current source (I2) and the cathode of the third bias current source (I3) are connected with the power Voltage (VDD), the source of the thirtieth NMOS transistor (MS1) is connected with the source of the thirty-first NMOS transistor (MS2) and then connected with the anode of the second bias current source (I2), the gate of the thirtieth NMOS transistor (MS1) is connected with the first control signal VC1, the gate of the thirty-first NMOS transistor (MS2) is connected with the second control signal VC2, the drain of the thirty-second NMOS transistor (MS1) is connected with the drain of the thirty-fourth NMOS transistor (MS2) and then connected with the drain of the thirty-fourth NMOS transistor (MS1), the gate of the thirty-fourth NMOS transistor (MK1) is connected with the fifth control word (EN1), the source of the thirty-second NMOS transistor (MS3) is connected with the gate of the thirty-third NMOS transistor (MS4) and then connected with the gate of the third bias current source (I3), the cathode of the thirty-second bias current source (I3) is connected with the third bias current source (VC 4642), the third NMOS transistor (VC 4), the drain of the thirty-second NMOS transistor (MS3) is connected with the drain of the thirty-third NMOS transistor (MS4) and then connected with the drain of the thirty-fifth NMOS transistor (MK2), the gate of the thirty-fifth NMOS transistor (MK2) is connected with the sixth control word (EN2), and the source of the thirty-fourth NMOS transistor (MK1) and the source of the thirty-fifth NMOS transistor (MK2) are connected with the drain of the fourteenth NMOS transistor (M1).

Optionally, the first comparator and the second comparator each comprise: the comparator main circuit and the bias circuit with adjustable bias current.

In the embodiment of the present invention, fig. 2 is a circuit diagram of the comparator of the present invention. The main circuit of the comparator also adopts a complementary input cycle structure and is composed of transistors MK7, MK8, PC0a, PC0b, PC1a, PC1b, PC2a, PC2b, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, NC0, NC1a, NC1b, NC2a, NC2b, NC3, NC4, NC5, NC6, NC7, NC8, NC9 and NC 10. According to different application requirements, the transistors MK7 and MK8 are switched on and off by control words EN7 and EN8, and the transistor PC0a or PC0b can be selectively switched into a circuit to adjust the bias current of the P input branch so as to change the opening threshold of the comparator. The transistors MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8, MC9, MC10, MC11, MC12, MC13, MC14, MC15, MC16, MC17, MC18, MC19, MC20, MC21, MC22, MC23 and MC24 constitute a comparator bias main circuit. The bias current of the comparator is provided by the current sources IC1 and IC2, and the on-off of the transistors MK9 and MK10 is controlled by the control words EN9 and EN10 according to different application requirements, so that the magnitude of the bias current of the comparator can be adjusted, and the speed of the comparator can be adjusted. By setting the control words EN7, EN8, EN9 and EN10, the working window of large current can be controlled.

The comparator main circuit comprises: a thirty-sixth NMOS transistor (NC1a), a thirty-seventh NMOS transistor (NC1b), a thirty-eighth NMOS transistor (NC2a), a thirty-ninth NMOS transistor (NC2b), a forty-NMOS transistor (NC0), a forty-first NMOS transistor (NC5), a forty-second NMOS transistor (NC6), a forty-third NMOS transistor (NC7), a forty-fourth NMOS transistor (NC8), a forty-fifth NMOS transistor (NC3), a forty-sixth NMOS transistor (NC4), a forty-seventh NMOS transistor (NC9), a forty-eighth NMOS transistor (NC10), a twenty-eighth PMOS transistor (PC5), a twenty-ninth PMOS transistor (PC6), a thirty-fifth PMOS transistor (PC7), a thirty-eleventh PMOS transistor (PC8), a thirty-second PMOS transistor (PC3), a thirty-third PMOS transistor (PC4), a thirty-fourth PMOS transistor (PC9), a thirty-fifth PMOS transistor (PC10), a sixth PMOS transistor (PC 8472), a thirty-seventh PMOS transistor (PC a), a thirty-ninth PMOS (PC a), a thirty-eighth PMOS a), a thirty-ninth PMOS (PC a), A forty-first PMOS (PC0b), a forty-second PMOS (MK7) and a forty-third PMOS (MK 8);

wherein, the gates of the thirty-sixth NMOS transistor (NC1a) and the thirty-seventh NMOS transistor (NC1b) are connected to one differential signal VCN (i.e. the third differential signal VCN) of the input fully differential signals, the gates of the thirty-eighth NMOS transistor (NC2a) and the thirty-ninth NMOS transistor (NC2b) are connected to the other differential signal VCP (i.e. the fourth differential signal VCP) of the input fully differential signals, the gate of the forty-eighth NMOS transistor (NC0) is connected to the fifth bias voltage (VCb1), the source is Grounded (GND), the drain is connected to the thirty-sixth NMOS transistor (NC1a), the thirty-seventh NMOS transistor (NC1b), the thirty-eighth NMOS transistor (NC2a) and the source of the thirty-ninth NMOS transistor (NC2b), the gate of the twenty-eighth PMOS transistor (PC5) is connected to the gate of the twenty-ninth PMOS transistor (PC6), the drain of the thirty-ninth NMOS transistor (PC b), the twenty-ninth NMOS transistor (PC 3638), the thirty-ninth PMOS 7) and the thirty-ninth source of the thirty-ninth NMOS transistor (PC 3638), a gate of a thirty-second PMOS transistor (PC3) is connected to a gate of a thirty-third PMOS transistor (PC4) and then connected to a sixth bias voltage (VCb3), a gate of a thirty-fourth PMOS transistor (PC9) is connected to a gate of a thirty-fifth PMOS transistor (PC10) and then connected to a sixth bias voltage (VCb3), a source of the thirty-second PMOS transistor (PC3) is connected to a drain of a twenty-ninth PMOS transistor (PC6), a source of the thirty-third PMOS transistor (PC4) is connected to a drain of a thirty-fifth PMOS transistor (PC7), a drain of the thirty-second PMOS transistor (PC3) is connected to a drain of a thirty-ninth NMOS transistor (NC2 NC b), a drain of the thirty-third PMOS transistor (PC4) is connected to a drain of a thirty-seventh NMOS transistor (NC1b), a source of the thirty-fourth PMOS transistor (PC9) is connected to a drain of the thirty-sixth NMOS transistor (PC a), and then connected to a drain of an eighth PMOS transistor (PC 356), and a drain of the thirty-eighth PMOS transistor (PC a) is connected to a drain of the thirty-eighth NMOS transistor (PC a), the gates of a thirty-sixth PMOS transistor (PC1a) and a thirty-seventh PMOS transistor (PC1b) are connected to one of the differential signals VCN (i.e. the third differential signal VCN) in the input fully differential signals, the gates of a thirty-eighth PMOS transistor (PC2a) and a thirty-ninth PMOS transistor (PC2b) are connected to the other differential signal VCP (i.e. the fourth differential signal VCP) in the input fully differential signals, the gates of a forty-PMOS transistor (PC0a) and a forty-first PMOS transistor (PC0b) are connected to a seventh bias voltage (VCb4), the source of the forty-PMOS transistor (PC0a) is connected to the drain of a forty-second PMOS transistor (MK7), the source of the forty-first PMOS transistor (PC0b) is connected to the drain of a forty-third PMOS transistor (MK8), the gate of the forty-second PMOS transistor (forty-7) is connected to a seventh control word (EN7), the gate of the forty-third PMOS transistor (PC1 4637) is connected to the forty-eighth PMOS transistor (MK) and the forty-ninth PMOS transistor (MK8) is connected to the forty-eighth control voltage (MK 3638), the drains of a forty-sixth PMOS tube (PC0a) and a forty-first PMOS tube (PC0b) are connected with the sources of a thirty-sixth PMOS tube (PC1a), a thirty-seventh PMOS tube (PC1b), a thirty-eighth PMOS tube (PC2a) and a thirty-ninth PMOS tube (PC2b), the gate of the forty-first NMOS tube (NC5) is connected with the gate of a forty-second NMOS tube (NC6) and then connected with the drain of a thirty-ninth PMOS tube (PC2b), the gate of the forty-third NMOS tube (NC7) is connected with the gate of a forty-fourth NMOS tube (NC8) and then connected with the drain of a thirty-seventh NMOS tube (PC1b), the forty-first NMOS tube (NC5), the forty-second NMOS tube (NC6), the forty-third NMOS tube (NC7) and the source of the forty-fourth NMOS tube (NC 35 8) are grounded, the fifth NMOS tube (PC3) is connected with the gate of an forty-sixth NMOS tube (NC 4624 b) and then connected with the gate of an eighth NMOS tube (NC9) and then connected with the gate of an eighth NMOS 2b, the source of the forty-fifth NMOS transistor (NC3) is connected to the drain of the forty-second NMOS transistor (NC6), the source of the forty-sixth NMOS transistor (NC4) is connected to the drain of the forty-third NMOS transistor (NC7), the drain of the forty-fifth NMOS transistor (NC3) is connected to the drain of the thirty-ninth PMOS transistor (PC2b), the drain of the forty-sixth NMOS transistor (NC4) is connected to the drain of the thirty-seventh PMOS transistor (PC1b), the source of the forty-seventh NMOS transistor (NC9) is connected to the drain of the thirty-sixth PMOS transistor (PC1a) and then to the drain of the forty-first NMOS transistor (NC5), the source of the eighth NMOS transistor (NC10) is connected to the drain of the thirty-eighth PMOS transistor (PC2a) and then to the drain of the forty-NMOS transistor (PC8), the drain of the forty-eighth NMOS transistor (NC10) and the thirty-fifth NMOS transistor (NC10) are connected to the thirty-fifth PMOS transistor (PC10) and the thirty-third PMOS (PC7), the forty-seventh NMOS transistor (NC9) is connected to the thirty-fourth PMOS transistor (PC9) as the comparator output VCOUT.

The bias circuit with adjustable bias current comprises: a fourth bias current source (IC1), a fifth bias current source (IC2), a forty-ninth NMOS transistor (MC1), a fifty-fifth NMOS transistor (MC2), a fifty-first NMOS transistor (MC3), a fifty-second NMOS transistor (MC4), a fifty-third NMOS transistor (MC8), a fifty-fourth NMOS transistor (MC9), a fifty-fifth NMOS transistor (MC10), a fifty-sixth NMOS transistor (MC11), a fifty-seventh NMOS transistor (MC16), a fifty-eighth NMOS transistor (MC17), a fifty-ninth NMOS transistor (MC18), a sixty NMOS transistor (MC23), a sixty-first NMOS transistor (MC24), a sixty-second NMOS transistor (MK 56), a sixty-third NMOS transistor (MK10), a forty-fourth PMOS transistor (MC5), a forty-fifth PMOS transistor (MC6), a forty-sixth PMOS transistor (MC7), a forty-seventh PMOS transistor (12), a forty-eighth PMOS 72), a forty-ninth PMOS (MC13), a forty-fifth PMOS (MC 368672), a forty-PMOS) and a forty-fifth PMOS (MC13), A fifty-third PMOS tube (MC21) and a fifty-fourth PMOS tube (MC 22);

wherein, the cathode of the fourth bias current source (IC1) and the cathode of the fifth bias current source (IC2) are connected with the power Voltage (VDD), the drain of the forty-ninth NMOS transistor (MC1) is connected with the gates of the forty-ninth NMOS transistor (MC1), the fifty-NMOS transistor (MC2), the fifty-first NMOS transistor (MC3), the fifty-second NMOS transistor (MC4), the fifty-third NMOS transistor (MC8), the fifty-fourth NMOS transistor (MC9), the fifty-fifth NMOS transistor (MC10) and the fifty-sixth NMOS transistor (MC11), the source of the forty-ninth NMOS transistor (MC1) is connected with the drain of the fifty-fifth NMOS transistor (MC2), the source of the fifty-first NMOS transistor (MC3) is connected with the drain of the second NMOS transistor (MC4), the source of the fifty-third NMOS transistor (MC8) is connected with the drain of the fifty-fourth NMOS transistor (9), the source of the fifth NMOS transistor (MC10) is connected with the drain of the sixth NMOS transistor (MC 4642), and the eighth NMOS 16) are connected with the gate of the eighth NMOS transistor (MC17), the source of the fifty-seventh NMOS transistor (MC16) is connected with the drain of the fifty-eighth NMOS transistor (MC17) and then connected with the source of the fifty-ninth NMOS transistor (MC18), the gate of the fifty-ninth NMOS transistor (MC18) is connected with the drain of the fifty-ninth NMOS transistor (MC18) and then connected with the gate of the sixty NMOS transistor (MC23) as an eighth bias voltage (VCb2), the drain of the sixty NMOS transistor (MC23) is connected with the gate of the sixty NMOS transistor (MC24) as a fifth bias voltage (VCb1), the source of the sixty NMOS transistor (MC23) is connected with the drain of the sixty NMOS transistor (MC24), the source of the fifty-NMOS transistor (MC2), the fifty-second NMOS transistor (MC4), the fourth NMOS transistor (MC9), the sixth NMOS transistor (MC11), the fifty-eighth NMOS transistor (MC17), the drain of the sixty-NMOS transistor (MC24) is grounded, the fourth PMOS transistor (MC5) is connected with the gate of the fifty-eighth NMOS transistor (MC6) and the fifth PMOS transistor (MC3), the source electrode of a forty-fourth PMOS tube (MC5) is connected with the drain electrode of a forty-fifth PMOS tube (MC6) and then is connected with the source electrode of a forty-sixth PMOS tube (MC7), the gate electrode and the drain electrode of the forty-sixth PMOS tube (MC7) are connected with the drain electrode of the fifty-third NMOS tube (MC8) to form a sixth bias voltage (VCb3), the second bias voltage (Vb3) is connected with the forty-seventh PMOS tube (MC12), the forty-ninth PMOS tube (MC14), the fifty-first PMOS tube (MC19) and the gate electrode of the fifty-third PMOS tube (MC21), the drain electrode of the forty-seventh fifty-seventh PMOS tube (MC12) is connected with the drain electrode of the foregoing forty-fifth NMOS tube (MC10), the source electrode of the forty-seventh PMOS tube (MC12) is connected with the drain electrode 632 of the forty-eighth PMOS tube (MC 638) and then is connected with the drain electrode 12) of the forty-seventh PMOS tube (MC 638) to form a seventh bias voltage (VCb4), the fourth bias voltage (Vb4) is connected to the gates of a fifty-second PMOS transistor (MC20) and a fifty-fourth PMOS transistor (MC22), the source of a forty-ninth PMOS transistor (MC14) is connected to the drain of a fifty-fifth PMOS transistor (MC15), the drain of a forty-ninth PMOS transistor (MC14) is connected to the drain of the fifty-seventh NMOS transistor (MC16), the source of a fifty-first PMOS transistor (MC19) is connected to the drain of a fifty-second PMOS transistor (MC20), the drain of a fifty-first PMOS transistor (MC19) is connected to the fifty-fifth NMOS transistor (MC18), the source of a fifty-third PMOS transistor (MC21) is connected to the drain of a fifty-fourth PMOS transistor (MC22), the drain of a PMOS transistor (MC21) is connected to the drain of the sixty NMOS transistor (MC23), the forty-fifth PMOS transistor (MC6), the forty-eighth PMOS transistor (MC 356), the drain of a forty-fourth PMOS transistor (MC20), and the source of a forty-fourth PMOS transistor (MC20), and the fourth PMOS 20), the positive electrode of the fourth bias current source (IC1) is connected with the drain electrode of a sixty-second NMOS tube (MK9), the grid electrode of the sixty-second NMOS tube (MK9) is connected with a ninth control word (EN9), the positive electrode of the fifth bias current source (IC2) is connected with the drain electrode of a sixty-third NMOS tube (MK10), the grid electrode of the sixty-third NMOS tube (MK10) is connected with a tenth control word (EN10), and the source electrode of the sixty-second NMOS tube (MK9) and the source electrode of the sixty-third NMOS tube (MK10) are connected with the drain electrode of a forty-ninth NMOS tube (MC 1).

Optionally, the N-type and P-type complementary input circularly folded transconductance operational amplifier circuit further includes: a common mode feedback circuit; the common mode feedback circuit includes: the device comprises a fully differential signal and common mode signal input transistor unit, a bias voltage transistor unit and a common mode feedback control signal generation unit.

In an embodiment of the present invention, fig. 3 is a connection diagram of a common mode feedback circuit. The N-type transistors M25, M26, M27, and M28 are input transistors of the common mode feedback circuit, wherein the gate of the transistor M25 is connected to the fully differential output signal VOUTN, the gate of the transistor M28 is connected to the other fully differential output signal VOUTP, and the gates of the transistors M26 and M27 are connected to the common mode input voltage VCM. Transistors M29 and M30 provide bias current to the input transistors, and the gates of M29 and M30 are tied to a bias voltage Vb 1. The voltage difference between the input transistors M25, M28 and M26, M27 generates the common mode control signal VCMFB for OTA in fig. 1 via transistors M31, M32 and series resistors R1, R2. VDD and GND may be supply voltages of 2.5V and 0V, respectively.

The fully differential signal and common mode signal input transistor unit includes: sixty-fourth (M25), sixty-fifth (M26), sixty-sixth (M27), and sixty-seventh (M28) NMOS transistors;

the grid electrode of the sixty-fourth NMOS tube (M25) is connected with the output differential signal VOUTN, the grid electrode of the sixty-seventh NMOS tube (M28) is connected with the other output differential signal VOUTP, and the grid electrode of the sixty-fifth NMOS tube (M26) is connected with the grid electrode of the sixty-sixth NMOS tube (M27) and then connected with the common-mode input Voltage (VCM).

The bias voltage transistor unit includes: sixty-eight (M29) and sixty-nine (M30) NMOS transistors;

the drain of the sixty-eight NMOS transistor (M29) is connected with the source of the sixty-four NMOS transistor (M25) and the source of the sixty-five NMOS transistor (M26), the drain of the sixty-nine NMOS transistor (M30) is connected with the source of the sixty-six NMOS transistor (M27) and the source of the sixty-seven NMOS transistor (M28), the gate of the sixty-eight NMOS transistor (M29) is connected with the gate of the sixty-nine NMOS transistor (M30) and then connected with the first bias voltage (Vb1), and the source of the sixty-eight NMOS transistor (M29) is Grounded (GND) with the source of the sixty-nine NMOS transistor (M30).

The common mode feedback control signal generating unit includes: a fifty-fifth PMOS (M31), a fifty-sixth PMOS (M32) and two resistors connected in series, namely a first resistor R1 and a second resistor R2 connected in series;

the grid electrode of a fifty-fifth PMOS tube (M31) is connected with the grid electrode of a fifty-sixth PMOS tube (M32) and then connected with the series end of the resistor R1 and the resistor R2, the drain electrode of the fifty-fifth PMOS tube (M31) is connected with the non-series end of the resistor R1 and then connected with the drain electrode of the sixty-fourth NMOS tube (M25) and the drain electrode of the sixty-seventh NMOS tube (M28) and then connected with the common mode control signal (VCMFB), the drain electrode of the fifty-sixth PMOS tube (M32) is connected with the non-series end of the resistor R2 and then connected with the drain electrode of the sixty-fifth NMOS tube (M26) and the drain electrode of the sixty-sixth NMOS tube (M27), and the source electrode of the fifth PMOS tube (M31) is connected with the source electrode of the fifty-sixth PMOS tube (M32) and then connected with the power supply Voltage (VDD).

The embodiment of the invention comprises the following steps: the circuit comprises an N-type complementary input circulating folding transconductance operational amplifier circuit and a P-type complementary input circulating folding transconductance operational amplifier circuit which are connected with each other, and an operational amplifier bias circuit driven by data; the data-driven operational amplifier bias circuit includes an input differential signal comparator; the input differential signal comparator is used for detecting an input differential signal, increasing the bias current of the circuit when the input differential signal is larger than or equal to the opening threshold of the input differential signal comparator, and keeping the bias current of the circuit unchanged when the input differential signal is smaller than the opening threshold of the input differential signal comparator. Through the scheme of the embodiment, the speed of the high-performance switched capacitor circuit is improved, the power consumption is reduced, the yield is improved, and the high-speed high-linearity switched capacitor circuit has the advantages of high speed and high linearity.

In the embodiment of the invention, differential input signals are compared through comparators (COMP1, COMP2) to detect virtual ground states of positive and negative input ends (VINN, VINP) of a closed-loop amplifier, and the output level of the comparators is used for controlling current sources, such as output level control switches (MS1, MS2) of the comparators, so that bias current can be increased when the differential input signals are larger, the speed of a circuit is improved, the current of the amplifier can be dynamically adjusted according to application requirements, and the working window of large current is controlled by opening thresholds and the speed of the comparators. The circuit is suitable for switched capacitor circuits with large load capacitance, such as analog-to-digital conversion circuits, filters and the like, can improve the speed of the circuit, reduce power consumption, improve yield, meet different application requirements through configuration, and meet the current research and development direction of integrated circuits.

Although the embodiments of the present invention have been described above, the above descriptions are only for the convenience of understanding the present invention, and are not intended to limit the embodiments of the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the invention as defined by the appended claims.

Claims

1. A data-driven operational amplifier, the operational amplifier comprising: the circuit comprises an N-type complementary input circulating folding transconductance operational amplifier circuit and a P-type complementary input circulating folding transconductance operational amplifier circuit which are connected with each other, and an operational amplifier bias circuit driven by data; the data-driven operational amplifier bias circuit includes an input differential signal comparator;

the input differential signal comparator is used for detecting an input differential signal, increasing the bias current of the circuit when the input differential signal is greater than or equal to the opening threshold of the input differential signal comparator, and keeping the bias current of the circuit unchanged when the input differential signal is less than the opening threshold of the input differential signal comparator;

the data-driven operational amplifier bias circuit includes: a bias voltage generating circuit;

the negative electrode of the first bias current source is connected with a power supply voltage, the positive electrode of the first bias current source is connected with the drain electrode of the fourteenth NMOS tube and then connected with the grid electrodes of the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube, the eighteenth NMOS tube, the nineteenth NMOS tube, the twentieth NMOS tube and the twenty-first NMOS tube, the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the fifteenth NMOS tube, the source electrode of the sixteenth NMOS tube is connected with the drain electrode of the seventeenth NMOS tube, the source electrode of the eighteenth NMOS tube is connected with the drain electrode of the nineteenth NMOS tube, the source electrode of the twentieth NMOS tube is connected with the drain electrode of the twenty-first NMOS tube, the drain electrode of the twenty-second NMOS tube is connected with the grid electrode of the twenty-third NMOS tube and then connected with the grid electrode of the twenty-fourth NMOS tube, and the source electrode of the twenty-second NMOS tube is connected with the drain electrodes of the twenty-third NMOS tube and the twenty-fourth NMOS tube and then connected with the grid electrodes of the fifth NMOS tube The source electrode of the twenty-third NMOS transistor is connected with the drain electrode of the twenty-eighth NMOS transistor, the source electrode of the twenty-fourth NMOS transistor is connected with the drain electrode of the twenty-ninth NMOS transistor, the gate electrode of the twenty-eighth NMOS transistor is connected with the first control word, the gate electrode of the twenty-ninth NMOS transistor is connected with the second control word, the gate electrode of the twenty-fifth NMOS transistor is connected with the drain electrode and then connected with the gate electrode of the twenty-sixth NMOS transistor as a third bias voltage, the drain electrode of the twenty-sixth NMOS transistor is connected with the gate electrode of the twenty-seventh NMOS transistor as the first bias voltage, the source electrode of the twenty-sixth NMOS transistor is connected with the drain electrode of the twenty-seventh NMOS transistor, the fifteenth NMOS transistor, the seventeenth NMOS transistor, the nineteenth NMOS transistor, the twenty-first NMOS transistor, the twenty-seventh NMOS transistor, the twenty-eighth NMOS transistor and the twenty-ninth NMOS transistor are grounded, and the gate electrode and drain electrode of the fourteenth PMOS transistor are connected with the gate electrode of the fifteenth NMOS transistor and the sixteenth NMOS transistor The drain electrode of the sixteenth NMOS tube is connected, the source electrode of the fourteenth PMOS tube is connected with the drain electrode of the fifteenth PMOS tube and the drain electrode of the sixteenth PMOS tube and then connected with the source electrode of the seventeenth PMOS tube, the source electrode of the fifteenth PMOS tube is connected with the drain electrode of the twenty sixth PMOS tube, the source electrode of the sixteenth PMOS tube is connected with the drain electrode of the twenty seventh PMOS tube, the gate electrode of the twenty sixth PMOS tube is connected with the third control word, the gate electrode of the twenty seventh PMOS tube is connected with the fourth control word, the gate electrode and the drain electrode of the seventeenth PMOS tube are connected and then connected with the drain electrode of the eighteenth NMOS tube to be used as a second bias voltage, the second bias voltage is connected with the gate electrodes of the eighteenth PMOS tube, the twentieth PMOS tube PMOS, the twenty second PMOS tube and the twenty fourth PMOS tube PMOS, the grid electrode of the nineteenth PMOS tube is connected with the grid electrode of the twenty-first PMOS tube and then connected with the drain electrode of the eighteenth PMOS tube as a fourth bias voltage, the fourth bias voltage is connected with the grid electrodes of the twenty-third PMOS tube and the twenty-fifth PMOS tube, the source electrode of the twentieth PMOS tube is connected with the drain electrode of the twenty-first PMOS tube, the drain electrode of the twentieth PMOS tube is connected with the drain electrode of the twenty-second NMOS tube, the source electrode of the twenty-second PMOS tube is connected with the drain electrode of the twenty-third PMOS tube, the drain electrode of the twenty-second PMOS tube is connected with the drain electrode of the twenty-fifth NMOS tube, the source electrode of the twenty-fourth PMOS tube is connected with the drain electrode of the twenty-fifth PMOS tube, the drain electrode of the twenty-fourth PMOS tube is connected with the drain electrode of the twenty-sixth NMOS tube, the nineteenth PMOS tube, the twenty-third PMOS tube, the twenty-fifth PMOS tube, the twenty, And the source electrodes of the twenty-sixth PMOS tube and the twenty-seventh PMOS tube are connected with the power supply voltage.

2. The data-driven operational amplifier of claim 1, wherein the N-type and P-type complementary input circularly folded transconductance operational amplifier circuit comprises:

3. The data-driven operational amplifier of claim 2,

4. The data-driven operational amplifier of claim 3,

5. The data-driven operational amplifier of claim 4,

6. The data-driven operational amplifier of claim 5,

7. The data-driven operational amplifier of claim 1 or 5, wherein the data-driven operational amplifier bias circuit further comprises: inputting a differential signal comparator and a data driving current branch circuit;

the input differential signal comparator includes: a first comparator and a second comparator; the negative input end of the first comparator and the positive input end of the second comparator are connected with a first differential signal VINN, the positive input end of the first comparator and the negative input end of the second comparator are connected with a second differential signal VINP, the first comparator outputs a first control signal VC1, and the second comparator outputs a second control signal VC 2;

8. The data-driven operational amplifier of claim 7, wherein the first comparator and the second comparator each comprise: the comparator main circuit and the bias circuit with adjustable bias current;

9. The data driven operational amplifier of claim 7, wherein the N-type and P-type complementary input circularly folded transconductance operational amplifier circuit further comprises: a common mode feedback circuit; the common mode feedback circuit includes: the full differential signal and common mode signal input transistor unit, the bias voltage transistor unit and the common mode feedback control signal generation unit;

the grid electrode of the sixty-four NMOS transistor is connected with a second output differential signal VOUTN, the grid electrode of the sixty-seven NMOS transistor is connected with a first output differential signal VOUTP, and the grid electrode of the sixty-five NMOS transistor is connected with the grid electrode of the sixty-six NMOS transistor and then connected with a common-mode input voltage VCM;