CN107611031B - Method for improving Faraday loop resistance - Google Patents
Method for improving Faraday loop resistance Download PDFInfo
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- CN107611031B CN107611031B CN201710695142.8A CN201710695142A CN107611031B CN 107611031 B CN107611031 B CN 107611031B CN 201710695142 A CN201710695142 A CN 201710695142A CN 107611031 B CN107611031 B CN 107611031B
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- tungsten silicide
- silicide film
- pvd
- resistance
- deposited
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- 238000000034 method Methods 0.000 title claims abstract description 22
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000004927 fusion Effects 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 238000005240 physical vapour deposition Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for improving Faraday loop resistance, which comprises the following steps: firstly, a tungsten silicide film is deposited by using a PVD method, and then a tungsten silicide film is deposited by using a CVD method. According to the invention, through a two-step tungsten silicide film forming mode, the PVD tungsten silicide film grown firstly can effectively avoid gaps formed by steep shapes of polycrystalline silicon or silicon oxide, and then a CVD tungsten silicide film is grown, so that the same material has good fusion characteristics, and better step coverage and lower film resistance can be considered.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for improving Faraday ring resistance.
Background
In the manufacturing process of the RF LDMOS (radio frequency LDMOS), the appearance of the side wall of the grid electrode is relatively steep. The faraday ring (faraday ring Shield) is a layer of silicide for modulating the electric field, which is typically a silicide of tungsten of CVDLPG, overlying the polysilicon gate. Because the step coverage performance is not good, gaps are easy to generate, and when the line width of the Faraday ring becomes small, a stripping phenomenon is easy to generate in the step of wet cleaning after etching on the tungsten silicide.
The problem of step coverage can be better solved by adopting a PVD method to deposit tungsten silicide. But after the tungsten silicide etching process, an oxide layer is deposited to form boron-phosphorus-silicon glass, and a high-temperature reflux process is carried out to increase the fluidity so as to improve the surface appearance, wherein the general process temperature reaches 800-1000 ℃. The thermal budget thereafter has a large effect on the resistance of the PVD deposited tungsten silicide. This is probably because the film formation temperatures of the two processes are greatly different. The CVD film forming temperature is 575 ℃, while the film forming temperature of PVD tungsten silicide is only 300 ℃.
Disclosure of Invention
The present invention is directed to a method for improving resistance of a faraday ring, which has a better step coverage and a lower sheet resistance.
To solve the above problems, the method for improving the resistance of the faraday ring according to the present invention comprises: firstly, a tungsten silicide film is deposited by using a PVD method, then a tungsten silicide film is deposited by using a CVD method, and then a Faraday ring is formed by patterning.
The PVD deposition has better step coverage performance, and the formed tungsten silicide film has good adhesion effect with a polysilicon gate or silicon oxide.
The tungsten silicide film formed by CVD can be well adhered with the tungsten silicide film formed by PVD, and has lower film resistance.
According to the invention, a PVD tungsten silicide film is grown in a two-step tungsten silicide film forming mode, so that a gap formed by steep shape of polycrystalline silicon or silicon oxide can be avoided, and then a CVD tungsten silicide film is grown, so that the same material has good fusion characteristics, and better step coverage and lower film resistance can be considered.
Drawings
FIG. 1 is a schematic illustration of the present invention first depositing a first tungsten silicide film by a PVD process.
FIG. 2 is a schematic illustration of the present invention further employing a CVD process to deposit a second tungsten silicide film.
FIG. 3 is a process flow diagram of the present invention.
Detailed Description
According to the method for improving the Faraday ring resistance, as shown in figure 1, after a polycrystalline silicon grid of an LDMOS device is formed, a layer of tungsten silicide film 1 is deposited on the polycrystalline silicon grid (including a silicon oxide dielectric layer deposited and covered on the polycrystalline silicon grid) in a PVD (physical vapor deposition) method, and the PVD deposition process has good step coverage performance, so that the tungsten silicide film 1 and the polycrystalline silicon or silicon oxide have good adhesion effect directly, and the surface appearance of the polycrystalline silicon grid can be perfectly attached.
Then, as shown in fig. 2, a tungsten silicide film 2 is deposited by CVD method on the basis of the above, and the tungsten silicide film formed by CVD can be well adhered to the tungsten silicide film formed by PVD, and has a low film resistance. Through the two-step tungsten silicide film forming mode, a PVD tungsten silicide film grown firstly can effectively avoid gaps formed by steep shape of polycrystalline silicon, surface shape copying performance is good, a CVD tungsten silicide film is grown later, resistivity is low, the same material has good fusion characteristics, and therefore good step coverage and low film resistance can be achieved.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (3)
1. A method of improving faraday ring resistance, comprising: after the polycrystalline silicon grid of the LDMOS device is formed, a tungsten silicide film is deposited by using a PVD method, then a tungsten silicide film is deposited on the surface of the tungsten silicide film deposited by using the PVD method by using a CVD method, and then a Faraday ring is formed by patterning.
2. The method for improving faraday ring resistance as claimed in claim 1, wherein: the PVD deposition has better step coverage performance, and the formed tungsten silicide film has good adhesion effect with polysilicon or silicon oxide.
3. The method for improving faraday ring resistance as claimed in claim 1, wherein: the silicide film formed by CVD is attached to the silicide film formed by PVD, and has lower film resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710695142.8A CN107611031B (en) | 2017-08-15 | 2017-08-15 | Method for improving Faraday loop resistance |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710695142.8A CN107611031B (en) | 2017-08-15 | 2017-08-15 | Method for improving Faraday loop resistance |
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| Publication Number | Publication Date |
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| CN107611031A CN107611031A (en) | 2018-01-19 |
| CN107611031B true CN107611031B (en) | 2020-06-09 |
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| CN201710695142.8A Active CN107611031B (en) | 2017-08-15 | 2017-08-15 | Method for improving Faraday loop resistance |
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Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102361035A (en) * | 2011-10-21 | 2012-02-22 | 昆山华太电子技术有限公司 | Structure of RF-LDMOS (radio frequency laterally double-diffused metal oxide semiconductor) device without epitaxial layer |
| CN102790088A (en) * | 2012-07-20 | 2012-11-21 | 昆山华太电子技术有限公司 | Breakdown voltage-adjustable RF-LDMOS device |
| CN103035681B (en) * | 2012-08-13 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | The manufacture method of RF LDMOS device |
| CN103035727B (en) * | 2012-11-09 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | RFLDMOS device and manufacture method |
| CN104716177B (en) * | 2013-12-11 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | A kind of manufacture method for the radio frequency LDMOS device for improving electric leakage |
| CN106257630B (en) * | 2015-06-16 | 2019-08-30 | 北大方正集团有限公司 | Manufacturing method of radio frequency RF LDMOS device |
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2017
- 2017-08-15 CN CN201710695142.8A patent/CN107611031B/en active Active
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| CN107611031A (en) | 2018-01-19 |
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