CN107634013A - A kind of ion implantation energy test structure and method of testing, electronic installation - Google Patents
A kind of ion implantation energy test structure and method of testing, electronic installation Download PDFInfo
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- CN107634013A CN107634013A CN201610565429.4A CN201610565429A CN107634013A CN 107634013 A CN107634013 A CN 107634013A CN 201610565429 A CN201610565429 A CN 201610565429A CN 107634013 A CN107634013 A CN 107634013A
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- 238000012360 testing method Methods 0.000 title claims abstract description 81
- 238000005468 ion implantation Methods 0.000 title claims abstract description 26
- 238000009434 installation Methods 0.000 title claims abstract description 19
- 238000010998 test method Methods 0.000 title claims abstract description 7
- 238000002347 injection Methods 0.000 claims abstract description 183
- 239000007924 injection Substances 0.000 claims abstract description 183
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims description 26
- 238000002513 implantation Methods 0.000 claims description 17
- 238000004458 analytical method Methods 0.000 claims description 10
- 230000002159 abnormal effect Effects 0.000 abstract description 9
- 238000012544 monitoring process Methods 0.000 abstract description 6
- 230000008901 benefit Effects 0.000 description 9
- 239000012212 insulator Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000047 product Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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Abstract
The present invention relates to a kind of ion implantation energy test structure and method of testing, electronic installation.The test structure includes：Semiconductor substrate, there is the first conduction type；Second injection zone, in the Semiconductor substrate, there is the second conduction type；First injection zone, in second injection zone, there is the first conduction type；Wherein, the Semiconductor substrate and second injection zone are electrically connected to earth terminal, and stress current is applied with first injection zone.The energy that can be injected by the test structure with monitoring ion, the wafer to be caught the exception online during WAT is tested, reduce the abnormal risk of wafer, further improve the performance and yield of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of ion implantation energy test structure and test side
Method, electronic installation.
Background technology
Manufacture of semiconductor rapid technological improvement in recent years, at present product stress compact, IC volumes are less and less, function
It is increasingly stronger, pin number is more and more, in order to reduce the area shared by chip package with improving IC efficiency, flip (Flip at this stage
Chip) mode, which encapsulates, is generally applied to drawing chip, chipset, memory and CPU etc..Above-mentioned high-order packaged type unit price is high
It is high, if chip testing can be carried out before packaging, find among with the presence of defective products wafer, that is, be marked, until back segment seals
The defective products of these marks is given up before dress processing procedure, unnecessary packaging cost can be saved.
It is wafer acceptance test (wafer acceptance test, WAT) that technique, which has a kind of conventional method, at present,
The WAT methods are tested for special resolution chart (test key) by electrical parameter whether just to control each step process
Often and stably.Various electric parameters testing structures, such as various transistor patterns, resistance test pattern, leakage are set on Cutting Road
Electric current/breakdown test pattern, to determine whether wafer undergoes normal technique.
More and more, ion implantation dosage and Implantation Energy in the use of the preparation process intermediate ion injection technology of chip
Directly affect the reliability and electrical parameter of device.
There are many test structures to monitor implantation dosage at present, but no structure can monitor Implantation Energy.If
Implantation Energy is shifted in injection process, and the wafer of poor performance or failure can not be noticeable in WAT tests, so as to straight
Client is given in sending and receiving.
Therefore, need to be improved the test structure is further at present at present, to eliminate above mentioned problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to overcome the problem of presently, there are, the invention provides a kind of ion implantation energy test structure, the test
Structure includes：
Semiconductor substrate, there is the first conduction type；
Second injection zone, in the Semiconductor substrate, there is the second conduction type；
First injection zone, in second injection zone, there is the first conduction type；
Wherein, the Semiconductor substrate and second injection zone are electrically connected to earth terminal, first injection zone
On be applied with stress current.
Alternatively, the top of second injection zone is concordant with the top of first injection zone, and described
Part below at the top of one injection zone is surrounded by second injection zone.
Alternatively, the top of second injection zone is concordant with the top of the Semiconductor substrate, and described second
Part below at the top of injection zone is surrounded by the Semiconductor substrate.
Alternatively, the test structure includes the first pad, the second pad and the 3rd pad；
Wherein, one end of first pad is electrically connected to first injection zone, the other end of first pad
On be applied with the stress current；
One end of second pad is electrically connected to second injection zone, the other end electrical connection of second pad
To the earth terminal；
One end of 3rd pad is electrically connected to the Semiconductor substrate, and the other end of the 3rd pad is electrically connected to
The earth terminal.
Alternatively, first conduction type is p-type, and second conduction type is N-type.
Alternatively, the test structure also includes benchmark knot, energy and institute on the basis of the Implantation Energy of the benchmark knot
Stating benchmark knot has reference resistance.
Present invention also offers a kind of method of testing of above-mentioned test structure, it is characterised in that methods described includes：
The Semiconductor substrate and second injection zone are electrically connected to earth terminal, and in first injection zone
Upper application stress current；
The resistance for the knot that first injection zone and second injection zone are formed is tested, and according to the resistance point
Analyse ion implantation energy.
Alternatively, when the resistance is more than reference resistance, the surface of the knot away from the Semiconductor substrate, described the
The energy of one injection zone intermediate ion injection is more than reference energy.
Alternatively, when the resistance is less than reference resistance, the knot is close to the surface of the Semiconductor substrate, and described the
The energy of one injection zone intermediate ion injection is less than reference energy.
Alternatively, the method for testing of the resistance includes：
The voltage tested on second ion implanted regions, the electricity is calculated according to the voltage and the stress current
Resistance.
Present invention also offers a kind of electronic installation, the electronic installation includes above-mentioned test structure.
Present invention also offers a kind of electronic installation, the electronic installation includes above-mentioned test structure.
Further aspect of the present invention provides a kind of electronic installation, including foregoing test structure.
In order to solve above mentioned problem present in current technique, the invention provides a kind of test knot of ion implantation energy
Structure, the energy test structure include the first injection zone and the second injection zone, and first injection zone is less than described the
Two injection zones, to form knot, then apply electric current on first injection zone, and measure on second injection zone
Voltage, the resistance of the knot is calculated by the electric current and voltage, passes through the first injection zone described in the Resistance Analysis
Implantation Energy and dosage.The energy that can be injected by the test structure with monitoring ion, is captured online during WAT is tested
Abnormal wafer, reduce the abnormal risk of wafer, further improve the performance and yield of semiconductor devices.
The test structure of the present invention, as a result of above-mentioned manufacture method, thus equally has above-mentioned advantage.The present invention's
Electronic installation, as a result of above-mentioned test structure, thus equally there is above-mentioned advantage.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the flow chart of the method for testing of test structure of the present invention；
Fig. 2 shows the structural representation of test structure of the present invention；
Fig. 3 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, part, area, floor and/or part, these elements, part, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another
Element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, part, area,
Floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of with
The different orientation of device in operation.For example, if the device upset in accompanying drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this
Invent the technical scheme proposed.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this hair
It is bright to have other embodiment.
In order to solve above mentioned problem present in current technique, the invention provides a kind of test knot of ion implantation energy
Structure, the test structure include：
Semiconductor substrate, there is the first conduction type；
Second injection zone, in the Semiconductor substrate, there is the second conduction type；
First injection zone, in second injection zone, there is the first conduction type；
Wherein, the Semiconductor substrate and second injection zone are electrically connected to earth terminal, first injection zone
On be applied with stress current.
Wherein, the area of first injection zone is less than the area of second injection zone, for example, second note
The top for entering region with first injection zone is concordant, and at the top of first injection zone below part by described the
Two injection zones surround completely.
Wherein, second injection zone is concordant with the top of the Semiconductor substrate, and second injection zone
Part below top is surrounded completely by the Semiconductor substrate.
Wherein, the test structure also includes benchmark knot, energy and described on the basis of the Implantation Energy of the benchmark knot
Benchmark knot has reference resistance.
Alternatively, first conduction type is p-type, and second conduction type is N-type.
I.e. described first injection zone is p-type ion implanted regions, and second ion implanted regions are N-type ion implanting
Region, the Semiconductor substrate are P-type semiconductor substrate, but what the embodiment was merely exemplary.
Or first injection zone is N-type ion implanted regions, second ion implanted regions are noted for p-type ion
Entering region, the Semiconductor substrate is N-type semiconductor substrate, but what the embodiment was merely exemplary.
The Semiconductor substrate and second injection zone are electrically connected to earth terminal in the test structure, and
Apply stress current on first injection zone；
The resistance for the knot that first injection zone and second injection zone are formed is tested, and according to the resistance point
Analyse ion implantation energy.
When the resistance is more than reference resistance, the surface of the knot away from the Semiconductor substrate, first injection
The energy of region intermediate ion injection is more than reference energy.
When the resistance is less than reference resistance, the knot is close to the surface of the Semiconductor substrate, first injection
The energy of region intermediate ion injection is less than reference energy.
Wherein, the voltage tested on second ion implanted regions, calculated according to the voltage and the stress current
The resistance, the resistance is can obtain with the voltage divided by the stress current.
In order to solve above mentioned problem present in current technique, the invention provides a kind of test knot of ion implantation energy
Structure, the energy test structure include the first injection zone and the second injection zone, and first injection zone is less than described the
Two injection zones, to form knot, then apply electric current on first injection zone, and measure on second injection zone
Voltage, the resistance of the knot is calculated by the electric current and voltage, passes through the first injection zone described in the Resistance Analysis
Implantation Energy and dosage.The energy that can be injected by the test structure with monitoring ion, is captured online during WAT is tested
Abnormal wafer, reduce the abnormal risk of wafer, further improve the performance and yield of semiconductor devices.
The test structure of the present invention, as a result of above-mentioned manufacture method, thus equally has above-mentioned advantage.The present invention's
Electronic installation, as a result of above-mentioned test structure, thus equally there is above-mentioned advantage.
Embodiment one
Below with reference to the accompanying drawings being described in detail to test structure of the invention, Fig. 2 show test knot of the present invention
The structural representation of structure.
Below, the test structure of the present invention is described in detail.
As shown in Fig. 2 test structure of the present invention includes：
Semiconductor substrate 201, there is the first conduction type；
Second injection zone 202, in the Semiconductor substrate, there is the second conduction type；
First injection zone 203, in second doped region, there is the first conduction type；
Wherein, the Semiconductor substrate and second injection zone are electrically connected to earth terminal, first injection zone
On be applied with stress current.
The Semiconductor substrate 201 can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator
(SOI) silicon (SSOI), is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
And germanium on insulator (GeOI) etc. (SiGeOI).
On the semiconductor substrate can also be formed with other active devices, passive device and integrated device etc..
The Semiconductor substrate is adulterated with the first conduction type, and for example, p-type is adulterated, naturally it is also possible to and it is n-type doping,
Example is doped to below with p-type to illustrate.
Wherein, the dopant dose of the P type substrate is smaller, and doping depth is larger, to surround first injection region completely
Domain 203 and second injection zone 202.
Wherein, the area of first injection zone is less than the area of second injection zone, for example, second note
The top for entering region with first injection zone is concordant, and at the top of first injection zone below part by described the
Two injection zones surround completely.
Wherein, the area of second injection zone is less than the semiconductor substrate area, such as second injection region
Domain is concordant with the top of the Semiconductor substrate, and the part below second injection zone top is served as a contrast by the semiconductor
Bottom surrounds completely.
Alternatively, first conduction type is p-type, and second conduction type is N-type.
I.e. described first injection zone is p-type injection zone, and second ion implanted regions are N-type injection zone, institute
It is P-type semiconductor substrate to state Semiconductor substrate, but what the embodiment was merely exemplary.
Or first injection zone is N-type injection zone, second ion implanted regions are p-type injection zone,
The Semiconductor substrate is N-type semiconductor substrate, but what the embodiment was merely exemplary.
Wherein, the test structure also includes benchmark knot, energy and described on the basis of the Implantation Energy of the benchmark knot
Benchmark knot has reference resistance.
Wherein, the benchmark knot is as reference, for evaluating the size of the ion implantation energy.
Because the second injection zone intermediate ion Implantation Energy is different so that first injection zone and described second
The depth for the knot that injection zone is formed is different, when the second injection zone intermediate ion Implantation Energy is more than benchmark Implantation Energy,
The depth for the knot that first injection zone and second injection zone are formed is larger, the table away from the Semiconductor substrate
The resistance for the knot that face, first injection zone and second injection zone are formed is more than reference resistance.
Similarly, when the second injection zone intermediate ion Implantation Energy is less than benchmark Implantation Energy, first injection region
The depth for the knot that domain and second injection zone are formed is smaller, close to the surface of the Semiconductor substrate, first injection
The resistance for the knot that region and second injection zone are formed is less than reference resistance.
Therefore the resistance of the knot that can be formed by measuring first injection zone and second injection zone is commented
The depth for the knot that first injection zone described in valency and second injection zone are formed, and then analyze in second injection zone
Ion implantation energy.
Specifically, the Semiconductor substrate and second injection zone are electrically connected to ground connection in the test structure
End, and apply stress current on first injection zone；
The resistance for the knot that first injection zone and second injection zone are formed is tested, and according to the resistance point
Analyse ion implantation energy.
When the resistance is more than reference resistance, the surface of the knot away from the Semiconductor substrate, first injection
The energy of region intermediate ion injection is more than reference energy.
When the resistance is less than reference resistance, the knot is close to the surface of the Semiconductor substrate, first injection
The energy of region intermediate ion injection is less than reference energy.
Wherein, the voltage tested on second ion implanted regions, calculated according to the voltage and the stress current
The resistance, the resistance is can obtain with the voltage divided by the stress current.
In order to solve above mentioned problem present in current technique, the invention provides a kind of test knot of ion implantation energy
Structure, the energy test structure include the first injection zone and the second injection zone, and first injection zone is less than described the
Two injection zones, to form knot, then apply electric current on first injection zone, and measure on second injection zone
Voltage, the resistance of the knot is calculated by the electric current and voltage, passes through the first injection zone described in the Resistance Analysis
Implantation Energy and dosage.The energy that can be injected by the test structure with monitoring ion, is captured online during WAT is tested
Abnormal wafer, reduce the abnormal risk of wafer, further improve the performance and yield of semiconductor devices.
The test structure of the present invention, as a result of above-mentioned manufacture method, thus equally has above-mentioned advantage.The present invention's
Electronic installation, as a result of above-mentioned test structure, thus equally there is above-mentioned advantage.
Embodiment two
Present invention also offers a kind of method of testing based on test structure described in embodiment one, as shown in figure 1, the side
Method includes：
The Semiconductor substrate and second injection zone are electrically connected to earth terminal, and in first injection zone
Upper application stress current；
The resistance for the knot that first injection zone and second injection zone are formed is tested, and according to the resistance point
Analyse ion implantation energy.
Wherein, when the resistance is more than reference resistance, the surface of the knot away from the Semiconductor substrate, described first
The energy of injection zone intermediate ion injection is more than reference energy.
Wherein, when the resistance is less than reference resistance, the surface of the close Semiconductor substrate of knot, described first
The energy of injection zone intermediate ion injection is less than reference energy.
Because the second injection zone intermediate ion Implantation Energy is different so that first injection zone and described second
The depth for the knot that injection zone is formed is different, when the second injection zone intermediate ion Implantation Energy is more than benchmark Implantation Energy,
The depth for the knot that first injection zone and second injection zone are formed is larger, the table away from the Semiconductor substrate
The resistance for the knot that face, first injection zone and second injection zone are formed is more than reference resistance.
Similarly, when the second injection zone intermediate ion Implantation Energy is less than benchmark Implantation Energy, first injection region
The depth for the knot that domain and second injection zone are formed is smaller, close to the surface of the Semiconductor substrate, first injection
The resistance for the knot that region and second injection zone are formed is less than reference resistance.
Therefore the resistance of the knot that can be formed by measuring first injection zone and second injection zone is commented
The depth for the knot that first injection zone described in valency and second injection zone are formed, and then analyze in second injection zone
Ion implantation energy.
Specifically, the Semiconductor substrate and second injection zone are electrically connected to ground connection in the test structure
End, and apply stress current on first injection zone；
The resistance for the knot that first injection zone and second injection zone are formed is tested, and according to the resistance point
Analyse ion implantation energy.
When the resistance is more than reference resistance, the surface of the knot away from the Semiconductor substrate, first injection
The energy of region intermediate ion injection is more than reference energy.
When the resistance is less than reference resistance, the knot is close to the surface of the Semiconductor substrate, first injection
The energy of region intermediate ion injection is less than reference energy.
Wherein, the voltage tested on second ion implanted regions, calculated according to the voltage and the stress current
The resistance, the resistance is can obtain with the voltage divided by the stress current.
In order to solve above mentioned problem present in current technique, the invention provides a kind of survey based on ion implantation energy
The method of testing of structure is tried, the energy that can be injected by methods described with monitoring ion, is caught the exception online during WAT is tested
Wafer, reduce the abnormal risk of wafer, further improve the performance and yield of semiconductor devices.
Embodiment three
An alternative embodiment of the invention provides a kind of electronic installation, and it includes test structure, and the test structure is foregoing
Test structure in embodiment one.
The electronic installation, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or have
The intermediate products of above-mentioned test structure, such as：Cell phone mainboard with the integrated circuit etc..
Due to including test structure part there is higher performance, the electronic installation equally has above-mentioned advantage.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing test structure, and the test structure includes Semiconductor substrate, tool
There is the first conduction type；Second injection zone, in the Semiconductor substrate, there is the second conduction type；First injection region
Domain, in second doped region, there is the first conduction type；Wherein, the Semiconductor substrate and second injection
Region is electrically connected to earth terminal, and stress current is applied with first injection zone.The invention provides a kind of ion implanting
The test structure of energy, the energy test structure include the first injection zone and the second injection zone, first injection region
Domain is less than second injection zone, to form knot, then applies electric current on first injection zone, and measure described the
Voltage on two injection zones, the resistance of the knot is calculated by the electric current and voltage, by described in the Resistance Analysis
The Implantation Energy and dosage of first injection zone.The energy that can be injected by the test structure with monitoring ion, WAT is surveyed
The wafer to be caught the exception online in examination, reduce the abnormal risk of wafer, further improve the performance and yield of semiconductor devices.
The test structure of the present invention, as a result of above-mentioned manufacture method, thus equally has above-mentioned advantage.The present invention's
Electronic installation, as a result of above-mentioned test structure, thus equally there is above-mentioned advantage.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of ion implantation energy test structure, it is characterised in that the test structure includes：
Semiconductor substrate, there is the first conduction type；
Second injection zone, in the Semiconductor substrate, there is the second conduction type；
First injection zone, in second injection zone, there is the first conduction type；
Wherein, the Semiconductor substrate and second injection zone are electrically connected to earth terminal, are applied on first injection zone
Added with stress current.
2. test structure according to claim 1, it is characterised in that the top of second injection zone and described first
The top of injection zone is concordant, and the part below first injection zone top is surrounded by second injection zone.
3. test structure according to claim 1, it is characterised in that partly led with described at the top of second injection zone
The top of body substrate is concordant, and the part below second injection zone top is surrounded by the Semiconductor substrate.
4. test structure according to claim 1, it is characterised in that the test structure includes the first pad, the second weldering
Disk and the 3rd pad；
Wherein, one end of first pad is electrically connected to first injection zone, is applied on the other end of first pad
Added with the stress current；
One end of second pad is electrically connected to second injection zone, and the other end of second pad is electrically connected to institute
State earth terminal；
One end of 3rd pad is electrically connected to the Semiconductor substrate, and the other end of the 3rd pad is electrically connected to described
Earth terminal.
5. test structure according to claim 1, it is characterised in that first conduction type is p-type, and described second leads
Electric type is N-type.
6. test structure according to claim 1, it is characterised in that the test structure also includes benchmark knot, the base
Energy and the benchmark knot have reference resistance on the basis of the Implantation Energy of quasi- knot.
7. a kind of method of testing based on one of claim 1 to 6 test structure, it is characterised in that methods described includes：
The Semiconductor substrate and second injection zone are electrically connected to earth terminal, and applied on first injection zone
Add stress current；
Test the resistance for the knot that first injection zone and second injection zone are formed, and according to the Resistance Analysis from
Sub- Implantation Energy.
8. according to the method for claim 7, it is characterised in that when the resistance is more than reference resistance, the knot is remote
The surface of the Semiconductor substrate, the energy of the first injection zone intermediate ion injection are more than reference energy.
9. according to the method for claim 7, it is characterised in that when the resistance is less than reference resistance, the knot is close
The surface of the Semiconductor substrate, the energy of the first injection zone intermediate ion injection are less than reference energy.
10. according to the method for claim 7, it is characterised in that the method for testing of the resistance includes：
The voltage tested on second ion implanted regions, the resistance is calculated according to the voltage and the stress current.
11. a kind of electronic installation, it is characterised in that the electronic installation includes the test knot described in one of claim 1 to 6
Structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610565429.4A CN107634013A (en) | 2016-07-18 | 2016-07-18 | A kind of ion implantation energy test structure and method of testing, electronic installation |
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| CN201610565429.4A CN107634013A (en) | 2016-07-18 | 2016-07-18 | A kind of ion implantation energy test structure and method of testing, electronic installation |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040185587A1 (en) * | 2003-03-18 | 2004-09-23 | Song Doo Guen | Method of testing ion implantation energy in ion implantation equipment |
| CN101452968A (en) * | 2007-11-28 | 2009-06-10 | 上海华虹Nec电子有限公司 | PN junction varactor and merit figure extracting process thereof |
| CN103165486A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Through silicon via detection structure and corresponding detection method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040185587A1 (en) * | 2003-03-18 | 2004-09-23 | Song Doo Guen | Method of testing ion implantation energy in ion implantation equipment |
| CN101452968A (en) * | 2007-11-28 | 2009-06-10 | 上海华虹Nec电子有限公司 | PN junction varactor and merit figure extracting process thereof |
| CN103165486A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Through silicon via detection structure and corresponding detection method |
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Application publication date: 20180126 |