CN107660313A - Gallium Nitride (GAN) Transistor Structure on a Substrate - Google Patents

Abstract

Techniques for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate are disclosed. In some cases, GaN transistor structures may be used for system-on-chip (SoC) integration of high voltage GaN front-end Radio Frequency (RF) switches on bulk silicon structures. The techniques may include forming a plurality of fins in a substrate, depositing a GaN layer on the fins, oxidizing at least a portion of each fin in a gap under the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. In some cases, the techniques may be used to form various non-planar isolated GaN transistor architectures with relatively small form factors, low on-resistance, and low off-state leakage.

Description

Gallium Nitride (GAN) Transistor Structure on a Substrate

Background technique

Radio frequency (RF) switches are important components built into the RF front-end systems of modern mobile communication devices. RF front-ends today need to support multiple wireless services in different frequency bands such as long-range wireless bands (eg, WiFi protocols), short-range wireless bands (eg, Bluetooth protocols), and cellular bands (eg, 3G/4G/LTE/GSM protocols) . While some devices include multiple RF power amplifiers (e.g. more than 6) specifically for different frequency bands, there is generally room for no more than 3 antennas. Also, the RF switch needs to implement functions such as the ability to download data simultaneously while the main antenna is occupied for voice communication. There can be as many as 20 to 30 RF switches in a typical RF front end. Furthermore, RF switches must be able to handle up to 50V on the drain and source in their off-state while maintaining as low leakage as possible. In their on-state, RF switches must provide the lowest possible on-resistance to reduce power dissipation.

Description of drawings

FIG. 1 illustrates a method of forming an integrated circuit according to various embodiments of the present disclosure.

2A-F illustrate exemplary structures formed when the method of FIG. 1 is performed, according to various embodiments of the present disclosure.

Figure 2F' shows a cross-section through the channel region of a fin-shaped non-planar multiple quantum well (MQW) gallium nitride (GaN) transistor structure, according to an embodiment of the disclosure.

Figure 2F" shows a cross-section through the channel region of a fin-like non-planar three-dimensional electron gas (3DEG) GaN transistor structure according to an embodiment of the disclosure.

3 is a transmission electron microscope (TEM) image showing a cross-sectional side view of an integrated circuit structure formed according to an embodiment of the disclosure.

4 illustrates a functional block diagram of a system-on-chip (SoC) implementation of a mobile computing platform, according to various embodiments of the present disclosure.

FIG. 5 illustrates a computing system implemented using integrated circuit structures or devices formed using the techniques disclosed herein, according to various embodiments of the present disclosure.

Detailed ways

Techniques for gallium nitride (GaN) oxide isolation and formation of GaNk transistor structures on substrates such as bulk silicon (Si) substrates are disclosed. GaN transistor structures can be used, for example, for system-on-chip (SoC) integration of high-voltage GaN front-end radio frequency (RF) switches on Si substrates. In an embodiment, the technique may include forming a plurality of fins in the substrate, depositing a GaN layer on the fins, oxidizing at least a portion of each fin in the gap below the GaN layer, and One or more transistors are formed on and/or from the GaN layer. For example, a GaN layer can be used for the transistor channel, but the transistor source and drain regions can be grown epitaxially on the GaN layer. The technique may be used, for example, in a process for forming low-leakage high-breakdown enhancement-mode high-k dielectric GaN transistors on isolated GaN islands. The technique can also be used, for example, to form GaN transistors including multiple quantum well (MQW) or three-dimensional electron gas (3DEG) architectures with reduced on-resistance. Techniques can also be used to form fin (or tri-gate) and nanowire (or gate wrap) architectures to achieve low off-state leakage, for example. Many variations and configurations will be apparent from the present disclosure.

general overview

Radio frequency (RF) switches are implemented primarily using gallium arsenide (GaAs) pseudotyped high electron mobility transistors (pHEMTs) on semi-insulating GaAs substrates. Note that HEMTs (or pHEMTs) may also be referred to as heterostructure field-effect transistors (HFETs), modulation-doped FETs (MODFETs), two-dimensional electron gas FETs (TEGFETs), or selectively doped heterostructure transistors ( SDHT); however, for ease of description, the device is primarily referred to herein as a HEMT. GaAs pHEMTs present complex issues such as difficulty in simultaneously achieving low on-resistance and small form factor (die size) required for system-on-chip (SoC) applications. Furthermore, GaAs pHEMTs are generally formed as depletion-mode (D-mode) devices, which require a negative supply voltage to turn them off and thus result in increased circuit complexity and system cost. Furthermore, the relatively low bandgap of GaAs (bandgap of 1.4eV) limits GaAs pHEMTs with respect to, for example, scalability, on-resistance, off-state leakage, RF losses, control logic integration, applied voltage capability, and power dissipation. Ability. Correspondingly, Gallium Nitride (GaN), a higher bandgap material (3.4eV bandgap), is considered as a GaAs replacement in HEMT devices. However, such GaN transistors are primarily D-mode HEMT devices implemented on relatively expensive silicon carbide (SiC) wafers with relatively small diameters (eg, 3-4 inches). Consequently, the cost of such GaN transistors is correspondingly high, rendering the device impractical for many applications.

Accordingly and in accordance with one or more embodiments of the present disclosure, techniques for GaN oxide isolation and formation of GaN transistor structures on silicon (Si) substrates are disclosed. As will be apparent in light of this disclosure, oxide isolation techniques enable the formation of GaN transistor structures on Si substrates and also achieve the low leakage required for HEMT devices at high applied voltages (V _DD ). Accordingly, according to an embodiment, the technique may eg be used for system-on-chip (SoC) integration of a high-voltage GaN front-end RF switch on a Si substrate. As previously stated, GaN is a higher bandgap material (bandgap of 3.4eV) compared to, for example, GaAs (bandgap of 1.4eV), and thus GaN offers many benefits in the context of transistor performance, as described herein . In some embodiments, techniques may be used to form GaN transistor structures on silicon germanium (SiGe) or germanium (Ge) substrates. In some embodiments, techniques can be used to form GaN transistor architectures, including but not limited to HEMTs, pHEMTs, transistors using two-dimensional electron gas (2DEG) architectures, using three-dimensional electron gas (3DEG) or 3D polarized field effect transistors ( FET) architecture and transistors using multiple quantum well (MQW) or superlattice architecture.

In some embodiments, techniques include forming nano-templates in a substrate (eg, a bulk Si substrate) by patterning the substrate and etching the fins, eg, via Shallow Trench Recess (STR) etching. Shallow trench isolation (STI) material, such as an oxide or nitride material, may then be deposited in the STR trenches, for example, to isolate the substrate fins from each other. A layer of GaN may then be deposited over the structure, and in some embodiments, a nucleation layer (eg, aluminum nitride) may be deposited prior to depositing the GaN layer (eg, to prevent GaN from reacting with the substrate material). Note that the GaN layer (and nucleation layer, if present) can be deposited such that they grow only on the substrate fins (eg using a Metal Organic Chemical Vapor Deposition (MOCVD) process). A gap may exist between the GaN layer and the STI material, and in some embodiments, the STI material below the GaN layer may optionally be etched away to form a gap or increase the size of the gap, exposing the substrate fin. at least partly. Note that in some embodiments, the STI material may be recessed prior to depositing the GaN layer such that the gap exists after the GaN layer is formed. The exposed portions of the substrate fins in the gaps may then be oxidized to isolate the GaN layer from the substrate. The gap between the GaN layer and the STI material can then be filled (eg, using a spin-on deposition process) with additional STI material. The resulting isolated GaN layer (whether a single continuous GaN layer across the top of the fin or multiple GaN layers or so-called GaN islands, each corresponding to a particular fin top, as the case may be) can be used Various transistor devices are formed on and/or from this layer. In this way, the GaN layer acts as a pseudo substrate electrically isolated from the underlying substrate (eg Si, SiGe, Ge substrate) on which transistor structures can be formed. For example, in some embodiments, n-channel transistor devices may be formed by epitaxial regrowth of n-type source and drain (S/D) regions. As will be apparent from this disclosure, such transistor devices may include the following geometries: HEMT architectures, MQW or superlattice architectures, 3DEG architectures, fin-like (e.g. Tri-Gate or FinFET) configurations, and/or nanowire ( or nanoribbon or gate surround) configurations, to provide only a few exemplary device geometries.

In some embodiments, advantages may be realized as a result of using isolated GaN for the transistor structures described in various ways herein. As previously mentioned, GaN has a wide bandgap of 3.4eV (compared eg to the 1.4eV bandgap of GaAs), thus allowing GaN transistors to withstand larger electric fields (applied voltage V _DD ) before suffering breakdown. For example, a GaN transistor can withstand an electric field that is orders of magnitude greater than a similarly sized GaAs transistor can withstand before suffering breakdown. This also enables GaN transistors to be scaled down to even smaller physical dimensions while operating at the same V _DD , enabling smaller on-resistance, smaller capacitance, and smaller transistor widths, resulting in Benefits such as reduced power dissipation, higher circuit efficiency, and smaller form factors. Also, GaN has high electron mobility (for example, about 1000 cm2/(Vs)). GaN n-channel transistors can also employ 2DEGs, which can be located at steep heterointerfaces formed by epitaxial growth of a charge-induced film (referred to herein as a polarization layer) with large spontaneous and piezoelectric polarization. Such polarizing layer materials may include Aluminum Nitride (AlN), Aluminum Gallium Nitride (AlGaN), Indium Aluminum Nitride (InAlN), Indium Aluminum Gallium Nitride (InAlGaN), or any other suitable material, depending on the final purpose or target application. Accordingly, very high charge densities (eg, up to 2E13 per square centimeter) can be formed by such mechanisms without impurity dopants, allowing high mobility to be maintained.

Many other benefits of the techniques and structures variously described herein will be apparent in light of this disclosure. For example, technology can be used to achieve large-scale SoC integration by integrating GaN on large Si substrates (eg, 8 inches/20 cm and larger). Additionally, oxide isolation technology enables the low leakage required at the high V _DD typically used in SoC implementations. In addition, technologies and structures can improve the on-resistance by utilizing multiple quantum wells and 3DEG architectures and non-planar/3D configurations (such as fin or tri-gate architectures, nanowires or nanoribbons or gate surround architectures, etc.), thus reducing the on-resistance. The required transistor width is small and thus enables a small form factor. Another benefit of the techniques is that they can be used to implement enhancement-mode GaN transistors, removing the need for bias circuits supplying negative gate voltages, and thus enabling smaller form factors and saving AND and depletion-mode (D-mode ) Transistor structure-related components and costs associated with processing. Still further, GaN has particular utility for the techniques variously described herein because GaN will not be oxidized during the oxidation process, in contrast to other III-V materials that decompose under oxidizing conditions. Still further, GaN can achieve high electron mobility (eg, about 1000 cm2/(V _−s )) required for HEMT device applications. Furthermore, GaN provides improved figure of merit (FOM) performance compared to, for example, existing Si metal oxide semiconductor field effect transistors (MOSFETs).

When analyzed (e.g., using scanning/transmission electron microscopy (SEM/TEM), composite mapping, secondary ion mass spectrometry (SIMS), atom probe imaging, 3D tomography, etc.), according to one or more embodiments Configured structures or devices will effectively represent the integrated circuit and transistor structures described herein in various ways. For example, in some embodiments, GaN transistors formed on fins of Si, SiGe, or Ge substrates may be inspected. Furthermore, the GaN layer in and/or on which the transistor is formed (for example, the transistor channel region may be formed in the GaN layer, but the source and drain regions may be formed on this layer via epitaxial regrowth) may The fin is electrically isolated from the substrate due to at least a portion of the substrate being oxidized. For example, in the case of a Si substrate, at least a portion of each fin may be oxidized to silicon dioxide, thereby electrically isolating the upper GaN layer from the underlying Si substrate and reducing or preventing the flow from the GaN transistor to the Si substrate. of leaks. Accordingly, the technology allows SoC integration where GaN transistors can be formed on Si substrates. In some embodiments, GaN transistor structures may be included in one or more RF switches (eg, high voltage front-end RF switches). GaN transistor structures described in various ways herein may be suitable for a variety of applications, such as personal computers (PCs), tablet computers, smartphones, power management and communications applications, and power conversion and automotive applications; however, this disclosure does not are intended to be so limited. For example, as consumers demand smaller form factors to fit more integrated circuits into more functions, there is high demand for efficient and small form factor RF front-ends, and thus SoC solutions based on isolated GaN transistors are very attractive. Many configurations and modifications will be apparent in light of this disclosure.

Architecture and Methodology

FIG. 1 illustrates a method 100 of forming an integrated circuit in accordance with one or more embodiments of the present disclosure. 2A-F illustrate exemplary integrated circuit structures formed when performing the method 100 of FIG. 1 in accordance with various embodiments. As will be apparent from the formed structures, method 100 discloses techniques for GaN oxide isolation for the purpose of forming GaN transistor structures on a substrate. A variety of transistor geometries can benefit from the techniques described herein, including but not limited to HEMTs, pHEMTs, transistors with 2DEG architectures, transistors with 3DEG (or 3D polarized FETs) architectures, multiple quantum well (MQW) or ultra- Lattice architecture of transistors. In addition, techniques can be used to form CMOS transistors/devices/circuits, wherein the GaN transistor structures described herein in various ways are eg n-MOS transistors for CMOS.

As can be seen in FIG. 1 , according to an embodiment, method 100 includes forming ( 102 ) fins 202 in substrate 200 to form the exemplary resulting structure shown in FIG. 2A . In some embodiments, substrate 200 may be a bulk substrate of Si, SiGe, or Ge. In some embodiments, substrate 200 may be an X-on-insulator (SOI) substrate, where X includes Si, SiGe, or Ge, and the insulator material is an oxide material or a dielectric material or some other electrically insulating material or some other suitable A multilayer structure where the top layer includes Si, SiGe or Ge. For example, in some embodiments, the substrate may be a bulk Si substrate with a buffer layer of SiGe or Ge on top of a portion of the bulk Si substrate, where the buffer layer may be used for the substrate as described herein in various ways 200. In some exemplary applications, the bulk Si substrate can have a high resistivity (eg, greater than 10 ohm-cm). Fins 202 may be formed ( 102 ) from substrate 200 using any suitable technique, such as using one or more patterning, masking, photolithography, and etching (wet and/or dry) processes. As can be seen in FIG. 2A , in some examples, the structure includes trenches 205 that may be referred to as shallow trench recess (STR) trenches. Trenches 205 may be formed with different widths and depths, and fins 202 may be formed with different widths and heights, depending on the end use or target application. Fins 202 may be formed to have different widths and heights. Note that, for ease of illustration, in this exemplary structure, trenches 205 and fins 202 are both shown as having the same width and height/depth; however, the disclosure is not intended to be so limited. Also note that although four fins 202 are shown in the exemplary configuration, any number of fins may be formed, such as one, two, ten, hundreds, thousands, millions etc., depending on the end use or target application.

According to an embodiment, method 100 of FIG. 1 continues with depositing ( 104 ) shallow trench isolation (STI) material 210 and planarizing to form the resulting exemplary structure shown in FIG. 2B . Deposition 104 of STI material 210 may include any suitable technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any other suitable deposition process. STI material 210 may include any suitable insulating material, such as one or more oxides (eg, silicon dioxide) and/or nitrides (eg, silicon nitride). In some embodiments, STI material 210 may be selected based on substrate material 200 . For example, in the case of Si substrate 200, STI material 210 may be silicon dioxide or silicon nitride. Note that in some cases, fins 202 may protrude from STI material 210 after the planarization process is performed.

According to an embodiment, the method 100 of FIG. 1 continues with optionally recessing the STI material 210 ( 106 ). For example, the recessing 106 process may be performed after the planarizing 104 process to increase the fins 202 by the amount of the fins 202 protruding from the STI material 210 . Such recessing process 106 may include any suitable wet or dry etching process or any other suitable process. As can be seen in FIG. 2B , in this exemplary embodiment, the fins protrude such that the height H of the fins 202 is above the STI material.

According to an embodiment, method 100 of FIG. 1 continues with depositing ( 108 ) GaN layer 230 and depositing ( 110 ) planarization layer 240 to form the resulting exemplary structure shown in FIG. 2C . Depositions 108 and 110 may include any suitable technique, such as growing GaN layer 230 and planarization layer 240 in a metal organic chemical vapor deposition (MOCVD) chamber or any other suitable deposition process. In some embodiments, the growth conditions can be adjusted based on the desired resulting properties of the layer. For example, in some cases, the temperature can be increased and/or the pressure can be decreased and/or the V:III ratio (e.g., the ratio of N2 to Ga precursor gas flow) can be increased to allow faster growth of the lateral features of layers 230 and 240, The layers 230 and 240 are thereby kept as thin as possible in the vertical sections of the layers. In some embodiments, the GaN layer 230 (108) may be deposited such that it grows only on the substrate material (and thus only on the exposed substrate fins 202) and not on the STI material 210. In embodiments where a nucleation layer 220 is present (as described in more detail below), GaN layer 230 may be grown on that nucleation layer and/or substrate fin 202 . Thus in some embodiments, the GaN material of layer 230 may be deposited such that it only grows on the III-V material and substrate material (eg, Si, SiGe, Ge) and not on the STI material 210 . For example, the structure of FIG. 2C is formed because the deposition process 108 used (eg, MOCVD) results in GaN material 230 growing only on fins 202 . In some embodiments, GaN layer 230 may be a separate island of GaN growth on each substrate fin 202 . In such an embodiment, the GaN layer 230 shown in FIG. 2C would include a plurality of GaN islands on top of each fin 202 , but not, for example, those islands that are not connected. In some examples, GaN layer 230 may be separated to form islands of such GaN layer 230 . In some embodiments, GaN layer 230 may be about 1 micron in thickness (eg, about 1 micron high as deposited) or less or any other suitable thickness, depending on the end use or target application.

In some embodiments, the polarizing layer may be aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), indium aluminum gallium nitride (InAlGaN), or any other suitable material, such as It will be apparent in light of this disclosure. In some embodiments, the polarizing layer 240 may be less than 50 nm in thickness, such as about 20-30 nm or any other suitable thickness, depending on the end use or target application. In some embodiments, nucleation layer 220 may optionally be deposited on the structure of FIG. 2B prior to depositing ( 108 ) GaN layer 230 . Nucleation layer 220 may be deposited to prevent GaN layer 230 from reacting with the substrate material (eg, in regions where GaN layer 230 would otherwise be deposited directly on substrate material fin 202 ). Deposition of nucleation layer 220 may be performed, for example, using any suitable technique, such as growing nucleation layer 220 in an MOCVD chamber. In some embodiments, the nucleation layer may be selectively deposited on the fin 202 because the nucleation material may only grow on the substrate fin material 202 and not on the STI material 210 . In some embodiments, for example, the nucleation layer may be a III-V material such as aluminum nitride (AlN) or a low temperature GaN layer (eg, deposited at a temperature in the range of 700 to 950 degrees Celsius). In some embodiments, where present, nucleation layer 220 may have a thickness of less than 50 nm (eg, a thickness of about 20 nm or any other suitable thickness), depending on the end use or intended application.

According to some embodiments, the method 100 of FIG. 1 continues with optionally depositing (112) additional III-V layers on the structure of FIG. 2C to form one of the resulting exemplary structures of FIG. 2C′ or 2C″. As As will be apparent from this disclosure, the exemplary structure of Figure 2C' can be used to form a MQW or superlattice transistor structure, while the exemplary structure of Figure 2C" can be used to form a 3D polarized FET. Deposition 112 may be performed, for example, using any suitable technique, such as growing an additional layer of III-N material in an MOCVD chamber. As shown in the exemplary structure of Figure 2C', an additional two sets of 2DEG layers are deposited, where each set includes a GaN layer and a polarization layer. In other words, the first set of 2DEG layers includes GaN layer 232 and polarization layer 242 , and the second set of 2DEG layers includes GaN layer 234 and polarization layer 244 . Any number of additional 2DEG layer groups may be deposited in process 112 to form a multiple quantum well structure, and although two groups are shown in this exemplary embodiment, one group, five groups, 100 groups, 1000 groups, etc. may be formed. Additionally, polarization layers 242 and 244 may be any of the polarization layer materials described herein (eg, AlN, AlGaN, InAlN, InAlGaN) or any other suitable polarization layer material, depending on the end use or target application. The transistor structure formed from the exemplary structure of Figure 2C' will be described in more detail below. As shown in the exemplary structure of FIG. 2C ″, in this alternative embodiment two additional layers are formed by depositing additional III-N material layers. Layer 236 is a graded layer that includes Increasing indium (In) is uniformly graded around a percentage of about 5-20% (or about 10%) In and then uniformly graded with decreasing In content until 0% In is deposited (and thus only GaN is deposited). GaN until deposited). Polarization layer 246 may then be deposited on graded layer 236. In some examples, aluminum nitride (AlN) may be selected for polarization layer 246 because the resulting structure to be formed may be a 3D polarized FET or 3DEG transistors, as will be described in more detail below.However, any polarizing layer material described herein or any other suitable polarizing layer material may be chosen for layer 246, depending on the end use or target application.

According to an embodiment, the method 100 of FIG. 1 continues with optionally recessing the STI material 210 ( 114 ). For example, depending on the gap G between the GaN layer 230 and the STI material 210 shown in FIG. 2D , the recess 114 may be performed to increase the gap distance G to, for example, provide better opening to the oxidation process 116 described below. In some embodiments, optional recess 114 may be performed using a wet etch to etch below GaN layer 230 . In some such embodiments, the etchant may be selective to the STI material 210 such that it 1) removes the STI material 210 without etching away the substrate material 200//202 or III-N deposited over the STI material 210 The material layers (eg, layers 230 and 240 ), or 2) etch away the STI material 210 at a faster rate than it etches away the substrate material 200/202 and/or the III-N material layer.

According to an embodiment, method 100 of FIG. 1 continues with oxidizing ( 116 ) at least a portion of fin 202 to form the resulting exemplary structure of FIG. 2D having oxidized fin portion 203 . Oxidation 116 of the oxidized fin portion 203 results in complete or almost complete isolation of GaN layer 230 from substrate 200 , which reduces leakage that would otherwise occur without isolation. Oxidation 116 may be performed using any suitable technique, such as a wet or dry thermal oxidation process or any other suitable oxidation process. For example, in embodiments where substrate 200 is Si, oxidation 116 may be performed at a temperature of 800 to 1000 degrees Celsius using, for example, water vapor (typically an ultra-high purity flow) or molecular oxygen as an oxidant to form silicon dioxide. In some cases, oxidized fin portion 203 may be referred to as a high temperature oxide layer (HTO). The oxidation conditions and oxidizing agent selected for the oxidation process 116 may depend on the material of the substrate 200 (and thus naturally the material of the fin 202). For example, lower temperatures may be used during oxidation 116 if substrate 200 is Ge or SiGe with up to 30% Ge. GaN has particular utility for the oxidation process 116 because GaN will not oxidize/decompose as easily or as quickly during the process 116 compared to other III-V materials that will decompose under oxidizing conditions (e.g., as result of the high temperature used). As can be appreciated, oxidation technique 116 allows GaN layer 230 to be used as a dummy substrate on which one or more transistors can be formed because GaN layer 230 is electrically isolated from substrate 200 after oxidation 116 is performed. Thus, in some embodiments, GaN layer 230 may be described as a GaN dummy substrate 230 from which one or more GaN transistor structures may be formed, as will be apparent in light of this disclosure.

According to an embodiment, the method 100 of FIG. 1 continues with underfilling ( 118 ) the gap G between the GaN layer 230 and the STI material 210 with additional STI material 212 to form the resulting exemplary structure shown in FIG. 2E . Underfill 118 may be performed using any suitable technique, such as a spin coating process or other suitable process. In some cases, STI material 212 may be reflowable, allowing it to be subjected to high temperatures (eg, 500-600 degrees Celsius). STI material 212 may be any suitable material, such as any of the materials described for STI layer 210 (eg, oxide and/or nitride materials). In some embodiments, additional STI material 212 may be the same as STI material 210, while in other embodiments, additional STI material 212 may be different from STI material 210, depending on the end use or target application.

Method 100 of FIG. 1 continues (120) with forming one or more transistors on isolated GaN layer 230, according to various embodiments. Various processes can be performed to complete (120) one or more transistors (including those having various geometries such as HEMT architectures, MQW or superlattice architectures (discussed below with respect to FIG. 2F'), 3DEG architectures (below with respect to Figure 2F" discusses the formation of transistors in fin-like (eg tri-gate or FinFET) configurations and/or nanowire (or nanoribbon or gate surround) configurations). For example, Figure 2F shows A transistor formed on the GaN layer 230, wherein the transistor includes source and drain (S/D) 252, 254 and a gate 256 (formed over the channel region in the GaN layer 230). In this exemplary embodiment, the Masking the structure of Figure 2E and etching to remove the polarization layer 240 in the S/D regions 252 and 254, followed by epitaxial regrowth of n-type S/D material to form the S/D regions 252 and 254. For example, the material may be Indium gallium nitride (InGaN) doped with Si to form n-type S/D regions 252 and 254. In some embodiments, the S/D material may be n-doped gallium nitride with a graded indium composition n-type doped InGaN or any other suitable material, as will be apparent from this disclosure. After the S/D regions 252 and 254 are formed, the region of the polarizing layer 240) and form the gate stack 256 to form the gate stack 256, as described in various ways below. In this exemplary embodiment, by removing the pole below the gate 256 layer 240 to achieve enhancement mode operation of the transistor. As is known, enhancement mode involves the transistor being normally off and will not conduct when there is no potential difference between the gate and source. This can be compared to the depletion mode (or D-mode ) transistor configuration, if the polarization layer is not removed before forming the gate stack 256, then the D-mode transistor configuration will be the resulting configuration. However, in some cases, enhancement mode operation is due to the benefits derived from such a mode (some of which are described herein) are more desirable.

In some embodiments, the formation of gate stack 265 may include dummy gate oxide deposition, dummy gate electrode (eg, poly-Si) deposition, and patterned hard mask deposition. Additional processing may include patterning dummy gates and depositing/etching spacer materials. After such a process, the method may continue with insulator deposition, planarization, and then removal of the dummy gate electrode and gate oxide to expose the channel region of the transistor, such as is done for a replacement metal gate (RMG) process. After opening the channel region, the dummy gate oxide and electrode can be replaced with eg a gate dielectric and a replacement metal gate, respectively. Other embodiments may include standard gate stacks formed by any suitable process, such as a subtractive process, where a gate dielectric/gate metal is deposited followed by one or more etch processes. Any number of standard back-end processes may also be performed to assist in completing (120) the formation of the one or more transistors.

In the exemplary structure shown in FIG. 2F , gate stack 256 may include a gate electrode and a gate dielectric formed directly under the gate electrode. The gate dielectric and gate electrodes may be formed using any suitable technique and from any suitable material. For example, the gate stack may be formed during a replacement metal gate process, as previously described, and such process may include any suitable deposition technique (eg, CVD, PVD, etc.). The gate dielectric can be, for example, any suitable oxide, such as silicon dioxide or a high-k gate dielectric material. Examples of high-k gate dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, Yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric layer to improve its quality. In general, the thickness of the gate dielectric should be sufficient to electrically isolate the gate electrode from the source and drain contacts. Furthermore, the gate electrode may for example comprise various materials such as polysilicon, silicon nitride, silicon carbide or various suitable metals or metal alloys such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta ), copper (Cu), titanium nitride (TiN) or tantalum nitride (TaN). Various back-end processes may also be performed, such as forming contacts on S/D regions 252 and 254 using, for example, a silicidation process (typically deposition of a contact metal followed by annealing).

Figure 2F' shows a cross-section through the channel region of a fin-like non-planar multiple quantum well (MQW) GaN transistor structure, according to an embodiment of the disclosure. The transistor structure continues in this exemplary embodiment from the structure of Figure 2C', where multiple 2DEG layer groups (e.g., GaN layer 232/polarization layer 242 and GaN layer 234/polarization layer 244) are formed. From Figure 2C', the structure is oxidized (116) and underfilled (118), as described above in various ways. Completion ( 120 ) of formation of the transistor structure then includes etching and patterning the III-N layer (eg GaN layer and polarization layer) into fins, thereby forming trenches 260 . In some embodiments, fins may be formed, for example, with a width of less than 100 nm and a height of greater than 20 nm. Process 120 may then continue in this exemplary embodiment by forming source/drain regions, which may include, for example, depositing n-type InGaN in those regions or some other suitable technique for source/drain processing. Process 120 may continue in this exemplary embodiment by forming gate stack 256 as variously described herein. Accordingly, method 100 may be used to form MQW or superlattice transistor structures on Si, SiGe, or Ge substrates using the oxide isolation techniques described herein. Recall that any number of sets of 2DEG layers may be formed during process 112 (deposition of additional III-N material). Thus, the MQW channel region shown in Figure 2F' may include more or fewer 2DEG (GaN/polarization layer) groups, depending on the end use or target application. Note that although the trenches 260 are recessed into the first/lowermost GaN layer 230, the present disclosure is not intended to be so limited. In some cases, the trenches 260 used to form the 3DEG fin structure can be shallower or deeper, depending on the end use or target application. In some embodiments, the polarization layer of the MQW structure can be used to reduce the on-resistance of the GaN transistor. Many other configurations and benefits of MQW or superlattice GaN transistor structures will be apparent in light of this disclosure.

Figure 2F" shows a cross-section through the channel region of a fin-shaped non-planar 3DEG GaN transistor structure according to an embodiment of the disclosure. The transistor structure continues in this example embodiment from that of Figure 2C", wherein a gradient is formed 3D polarizing layer 236 . From FIG. 2C″, the structure is oxidized (116) and underfilled (118), as described above in various ways. Completion of the formation of the transistor structure (120) then includes the addition of III-N layers (e.g., GaN layers and Polarization layer) etched and patterned into fins, thereby forming trenches 260. In some embodiments, fins having a width of less than 100 nm and a height of greater than 20 nm may be formed, for example. Process 120 in this exemplary embodiment may then continue by forming source/drain regions, which may include, for example, deposition of n-type InGaN in those regions or some other suitable technique for source/drain processing. Process 120 in this example The exemplary embodiment may continue by forming the gate stack 256, as described in various ways herein. Thus, the method 100 may be used on Si, SiGe, or Ge substrates using the oxide isolation techniques described herein Form a 3DEG or 3D polarized FET transistor structure. Note that although trench 260 is not recessed into first/lowermost GaN layer 230, the disclosure is not intended to be so limited. In some cases, for forming The trench 260 of the 3DEG fin structure can be shallower or deeper, depending on the end use or target application. In some embodiments, the polarization layer of the 3DEG structure can be used to reduce the on-resistance of the GaN transistor. According to this Many other configurations and benefits of 3DEG or 3D polarized FET transistor structures will be apparent from this disclosure.

3 is a transmission electron microscope (TEM) image showing a cross-sectional side view of an integrated circuit structure formed according to an embodiment of the disclosure. As can be seen, the image shows a Si substrate 200 including an oxide fin 203 surrounded by STI material 210 / 212 . As can also be seen, an AlN nucleation layer 220 is formed on the substrate 200 and STI materials 210 / 212 , and a GaN layer 230 is formed on and over the nucleation layer and the substrate 200 . Note that GaN layer 230 has a thickness of approximately 1.1 microns in this exemplary embodiment, although other suitable thicknesses (eg, 0.25 microns to 2.5 microns) may also be used. Oxidation process 116 may then be used in this exemplary embodiment to isolate GaN layer 230 from Si substrate 200 to allow electrically isolated GaN transistor structures to be formed on GaN layer 230 and to prevent or reduce 200 leaks. In some embodiments, techniques may be used to form GaN transistors with off-state leakage currents, eg, less than 1E-4mA per micron, up to about 40V. Accordingly, technology enables SoC integration of GaN transistors on Si substrates (or SiGe substrates or Ge substrates), as described in various ways herein.

In some embodiments, GaN transistor structures variously described herein (such as MQW and 3DEG transistor structures) can be formed with non-planar configurations, such as fins (such as Tri-Gate or FinFET) or nanowires (or nanoribbons). or gate surround) construction. In a fin transistor configuration, there are three active gates - two on either side and one on top - as known in the art. Nanowire transistor constructions are configured similarly to fin-based transistor constructions, but instead of a fin-shaped channel region (with gates on three sides (and thus three effective gates)), one or more nanowires are A gate material is used and typically surrounds each nanowire on all sides. Depending on the particular design, some nanowire transistors have, for example, four active gates. The nanowire(s) may be formed while exposing the channel region during a replacement gate process (eg RMG process) eg after removing the dummy gate or using some other suitable process. Note that the various GaN transistor structures described herein can be designed as depletion-mode (D-mode) or enhancement-mode transistors, depending on the end use or target application. Note further that processes 102-120 of method 100 are shown in a particular order in FIG. 1 for ease of description. However, one or more of processes 102-120 may be performed in a different order or not performed at all. For example, blocks 106 , 112 , and 114 are optional procedures that may not be performed during method 100 . Many variations and configurations will be apparent in light of the present disclosure.

Exemplary System-on-Chip (SoC) Implementation

Figure 4 illustrates a functional block diagram of a SoC implementation of a mobile computing platform according to various embodiments of the present disclosure. Mobile computing platform 400 may be any portable device constructed for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, mobile computing platform 400 may be any of a tablet computer, smartphone, laptop, etc. and includes display screen 405, which in an exemplary embodiment is a touch screen (e.g., capacitive type, inductive, resistive, etc.), SoC 410 and battery 413. As shown, the higher level of integration of the SoC 410 may be occupied by the battery 413 during the longest operating life between charges or by memory (not depicted) such as a solid-state drive for maximum functionality. The more form factors within the mobile computing platform 400 .

Depending on its application, mobile computing platform 400 may include other components including, but not limited to, volatile memory (such as DRAM), nonvolatile memory (such as ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, Cameras and mass storage devices (such as hard drives, compact disks (CD), digital versatile disks (DVD), etc.).

SoC 410 is further shown in expanded view 421 . According to an embodiment, SoC 410 may include a portion of a substrate (chip) on which two or more of: a power management integrated circuit (PMIC) 415; an RF integrated circuit including an RF transmitter and/or receiver; circuit (RFIC) 425; its controller 411; and one or more central processor cores 420,430. RFIC 425 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol designated as 3G, 4G, 5G and beyond. RFIC 425 may include multiple communication chips. For example, the first communication chip can be dedicated to shorter range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip can be dedicated to longer range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE , Ev-DO, etc.

As will be appreciated by those skilled in the art, among these functionally distinct circuit blocks, CMOS transistors are typically employed exclusively, except in PMIC 415 and RFIC 425 . In an embodiment of the present disclosure, PMIC 415 and/or RFIC 425 employ one or more integrated circuit structures (eg, including one or more GaN transistor structures) as variously described herein. In another embodiment, the PMIC 415 and RFIC 425 using the integrated circuit structure described herein can be integrated with one or more of the controller 411 and the processor cores 420, 430, the controller 411 and the processor core 420, 430 are provided in eg Si CMOS technology monolithically integrated with PMIC 415 and/or RFIC 425 onto a substrate (eg substrate 200 as variously described herein). It will be appreciated that within PMIC 415 and/or RFIC 425, CMOS need not be excluded utilizing high voltage GaN front-end RF switches and transistor structures described herein, rather other CMOS devices and structures may be further included within PMIC 415 and RFIC 425 in each of the .

As further shown in the exemplary embodiment of FIG. 4 , PMIC 415 has an output coupled to an antenna, and may also have communication modules (such as RF analog and digital baseband modules (not depicted)) coupled to SoC 410 input terminal. Alternatively, such a communication module may be provided on an off-chip IC of SoC 410 and coupled into SoC 410 for transmission. As can be appreciated based on this disclosure, the isolated GaN transistor structures described in various ways herein can be used to provide high voltage front-end RF switches including the low on-resistance and small form factor required for SOCs. Furthermore, the oxide isolation techniques described in various ways herein allow GaN transistors to be formed on Si, SiGe and Ge substrates.

exemplary system

FIG. 5 illustrates a computing system 1000 implemented using integrated circuit structures or devices formed using the techniques disclosed herein, according to various embodiments of the present disclosure. As can be seen, computing system 1000 houses motherboard 1002 . Motherboard 1002 may include a number of components including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which may be physically and electrically coupled to motherboard 1002 or otherwise integrated therein. As will be appreciated, motherboard 1002 may be, for example, any printed circuit board, whether a motherboard, a daughterboard mounted on a motherboard, or the only board of system 1000, or the like.

Depending on its application, computing system 1000 may include other components that may or may not be physically and electrically coupled to motherboard 1002 . These other components may include, but are not limited to, volatile memory (such as DRAM), nonvolatile memory (such as ROM), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, Touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices such as hard drives, optical discs ( CD), Digital Versatile Disk (DVD), etc.). Any components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques according to the example embodiments. In some embodiments, multiple functions may be integrated into one or more chips (eg note that communications chip 1006 may be part of or otherwise integrated into processor 1004).

Communications chip 1006 enables wireless communications for transferring data to and from computing system 1000 . The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data over a non-solid medium through the use of modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol designated as 3G, 4G, 5G and beyond. Computing system 1000 may include multiple communication chips 1006 . For example, the first communication chip 1006 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1006 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX , LTE, Ev-DO, etc.

Processor 1004 of computing system 1000 includes an integrated circuit die packaged within processor 1004 . In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes electronic data, eg, from registers and/or memory, to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communications chip 1006 may also include an integrated circuit die packaged within communications chip 1006 . According to some of these exemplary embodiments, the integrated circuit die of the communications chip includes one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capabilities may be integrated directly into the processor 1004 (eg, where the functionality of any chip 1006 is integrated into the processor 1004 rather than having a separate communications chip). Note further that processor 1004 may be a chipset with such wireless capabilities. In short, any number of processors 1004 and/or communications chips 1006 may be used. Likewise, any one chip or chipset may have multiple functions integrated therein.

In various implementations, computing device 1000 may be a laptop computer, netbook computer, notebook computer, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, Printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, portable music players, digital video recorders, or any other device that processes data or utilizes one or more integrated circuit structures or devices formed using the disclosed techniques Electronic devices, as variously described herein.

Additional Exemplary Embodiments

The following examples refer to additional embodiments from which many permutations and configurations will be apparent.

Example 1 is an integrated circuit comprising: a substrate from which a plurality of fins are derived, wherein at least a portion of each fin is oxidized; nitrogen on the fins and over the oxidized portions of the fins a gallium nitride (GaN) layer; and a transistor having a channel included in the GaN layer.

Example 2 includes the subject matter of Example 1, wherein the substrate is one of silicon, silicon germanium, and a bulk germanium substrate.

Example 3 includes the subject matter of any of Examples 1-2, further including a nucleation layer at least partially between the fin and the GaN layer.

Example 4 includes the subject matter of Example 3, wherein the nucleation layer is one of aluminum nitride and gallium nitride deposited at a low temperature in the range of 700 to 950 degrees Celsius.

Example 5 includes the subject matter of any of Examples 1-4, further including at least one additional GaN layer above the GaN layer, the transistor channel including at least one additional GaN layer.

Example 6 includes the subject matter of Example 5, further comprising a poling layer over each additional GaN layer, wherein each poling layer is aluminum nitride, aluminum gallium nitride, indium aluminum nitride, and indium aluminum gallium nitride one of them.

Example 7 includes the subject matter of any of Examples 1-4, further including a graded layer overlying the GaN layer, the transistor channel including the graded layer.

Example 8 includes the subject matter of Example 7, wherein the graded layer comprises GaN graded with indium.

Example 9 includes the subject matter of any of Examples 7-8, further including an aluminum nitride layer over the graded layer.

Example 10 includes the subject matter of any of Examples 1-9, wherein the transistor source and drain regions comprise n-type doped indium gallium nitride, n-type doped gallium nitride, n At least one of doped InGaN.

Example 11 includes the subject matter of any of Examples 1-10, wherein the transistor is an enhancement mode transistor.

Example 12 includes the subject matter of any of Examples 1-11, wherein the transistor is electrically isolated from the substrate.

Example 13 includes the subject matter of any of Examples 1-12, wherein the transistor comprises at least one of the following geometries: planar configuration, non-planar configuration, fin configuration, tri-gate configuration, nanowire configuration, gate surround Construction, High Electron Mobility Transistor (HEMT) Architecture, Pseudotyped HEMT (pHEMT) Architecture, Two-Dimensional Electron Gas (2DEG) Architecture, Three-Dimensional Electron Gas (3DEG) Architecture, Three-Dimensional Polarized Field-Effect Transistor (FET) Architecture, Multiquantum well (MQW) architecture and superlattice architecture.

Example 14 is a radio frequency (RF) switch comprising the subject matter of any of Examples 1-13, wherein the RF switch is a component of a system on chip (SoC) implementation.

Example 15 is a computing system comprising the subject matter of any of Examples 1-14.

Example 16 is a transistor comprising: a gallium nitride (GaN) dummy substrate on each of a plurality of fins derived from an underlying bulk silicon (Si) substrate, wherein the GaN dummy substrate is bonded to the Si substrate bottom electrical isolation; and a gate stack over a channel region in and/or on a GaN dummy substrate.

Example 17 includes the subject matter of Example 16, wherein at least a portion of the Si fin originating from the substrate is oxidized to silicon dioxide, providing electrical isolation from the Si substrate.

Example 18 includes the subject matter of any of Examples 16-17, further including a nucleation layer at least partially between the Si fin and the GaN layer.

Example 19 includes the subject matter of Example 18, wherein the nucleation layer is one of aluminum nitride and gallium nitride deposited at a low temperature in the range of 700 to 950 degrees Celsius.

Example 20 includes the subject matter of any of Examples 16-19, further comprising at least one additional GaN layer above the GaN layer, the transistor channel comprising at least one additional GaN layer.

Example 21 includes the subject matter of Example 20, further comprising a poling layer over each additional GaN layer, wherein each poling layer is aluminum nitride, aluminum gallium nitride, indium aluminum nitride, and indium aluminum gallium nitride one of them.

Example 22 includes the subject matter of any of Examples 16-19, further comprising a graded layer overlying the GaN layer, the transistor channel comprising the graded layer.

Example 23 includes the subject matter of Example 22, wherein the graded layer comprises GaN graded with indium.

Example 24 includes the subject matter of any of Examples 22-23, further including an aluminum nitride layer over the graded layer.

Example 25 includes the subject matter of any of Examples 16-24, wherein the transistor source and drain regions comprise n-type doped indium gallium nitride, n-type doped gallium nitride, n Type doped indium gallium nitride at least one.

Example 26 includes the subject matter of any of Examples 16-25, wherein the transistor is an enhancement mode transistor.

Example 27 includes the subject matter of any of Examples 16-26, wherein the GaN dummy substrate on each fin of the native plurality of fins includes a plurality of GaN dummy substrates, the plurality of GaN dummy substrates The dummy substrates each correspond to one of the fins.

Example 28 includes the subject matter of any of Examples 16-27, wherein the transistor comprises at least one of the following geometries: planar configuration, non-planar configuration, fin configuration, tri-gate configuration, nanowire configuration, gate surround Construction, High Electron Mobility Transistor (HEMT) Architecture, Pseudotyped HEMT (pHEMT) Architecture, Two-Dimensional Electron Gas (2DEG) Architecture, Three-Dimensional Electron Gas (3DEG) Architecture, Three-Dimensional Polarized Field-Effect Transistor (FET) Architecture, Multiquantum well (MQW) architecture and superlattice architecture.

Example 29 is a radio frequency (RF) switch comprising the subject matter of any of Examples 16-28, wherein the RF switch is a component of a system on chip (SoC) implementation.

Example 30 is a computing system comprising the subject matter of any of Examples 16-29.

Example 31 is a method of forming an integrated circuit, the method comprising: forming a plurality of fins in a substrate; depositing a gallium nitride (GaN) layer on the fins; oxidizing at least a portion of each fin; Transistors are formed on and/or from the GaN layer.

Example 32 includes the subject matter of Example 31, further comprising depositing a polarizing layer on the GaN layer, wherein the polarizing layer is one of aluminum nitride, aluminum gallium nitride, indium aluminum nitride, and indium aluminum gallium nitride.

Example 33 includes the subject matter of any of Examples 31-32, further comprising depositing shallow trench isolation (STI) material between the fins before depositing the GaN layer on the fins.

Example 34 includes the subject matter of Example 33, further comprising recessing the STI material prior to depositing the GaN layer on the fin.

Example 35 includes the subject matter of any of Examples 33-34, further comprising recessing the STI material after depositing the GaN layer on the fin.

Example 36 includes the subject matter of any of Examples 31-25, further comprising depositing one or more additional layers of III-N material over the GaN layer.

Example 37 includes the subject matter of any of Examples 31-36, further comprising underfilling the gap between the GaN layer and the substrate with an STI material after oxidizing at least a portion of each fin.

Example 38 includes the subject matter of any of Examples 31-37, wherein forming the transistor on and/or from the GaN layer includes patterning the GaN layer and any additional III-N layers thereover into fins.

Example 39 includes the subject matter of any of Examples 31-38, wherein forming the transistor on and/or from the GaN layer comprises depositing n-type doped indium gallium nitride in source and drain regions of the transistor, At least one of n-type doped gallium nitride, n-type doped indium gallium nitride with graded indium composition.

Example 40 includes the subject matter of any of Examples 31-39, wherein the transistor comprises at least one of the following geometries: planar configuration, non-planar configuration, fin configuration, tri-gate configuration, nanowire configuration, gate surround Construction, High Electron Mobility Transistor (HEMT) Architecture, Pseudotyped HEMT (pHEMT) Architecture, Two-Dimensional Electron Gas (2DEG) Architecture, Three-Dimensional Electron Gas (3DEG) Architecture, Three-Dimensional Polarized Field-Effect Transistor (FET) Architecture, Multiquantum well (MQW) architecture and superlattice architecture.

Example 41 includes the subject matter of any of Examples 31-40, wherein depositing the GaN layer on the fin comprises selectively depositing the GaN layer on the fin so as to provide a plurality of GaN islands, each island corresponding to the fin. one of the objects.

The foregoing description of the exemplary embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the present disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority from this application may claim the disclosed subject matter in different ways, and may generally include any combination of one or more limitations as variously disclosed or otherwise presented herein.

Claims (25)

1. a kind of integrated circuit, including：

Substrate, multiple fins are derived from the substrate, wherein, at least a portion of each fin is oxidized；

Gallium nitride (GaN) layer on the fin and above the oxidized portion of the fin；And

Transistor with raceway groove, the transistor channel are included in the GaN layer.

2. integrated circuit according to claim 1, wherein, the substrate is one of silicon, SiGe and germanium body substrate.

3. integrated circuit according to claim 1, further comprise being at least partially situated at the fin and the GaN Nucleating layer between layer.

4. integrated circuit according to claim 3, wherein, the nucleating layer is aluminium nitride and at 700 to 950 degrees Celsius In the range of in a low temperature of one of the gallium nitride that deposits.

5. integrated circuit according to claim 1, further comprise at least one extra above the GaN layer GaN layer, the transistor channel include at least one extra GaN layer.

6. integrated circuit according to claim 5, further comprise the polarization layer above each extra GaN layer, Wherein, each polarization layer is one of aluminium nitride, aluminium gallium nitride alloy, indium nitride aluminium and indium nitride gallium aluminium.

7. integrated circuit according to claim 1, further comprise the graded bedding above the GaN layer, the crystalline substance Body pipe trench road includes the graded bedding.

8. integrated circuit according to claim 7, wherein, the graded bedding is included with the GaN of indium gradual change.

9. integrated circuit according to claim 7, further comprise the aln layer above the graded bedding.

10. integrated circuit according to claim 1, wherein, source transistor polar region and drain region include n-type doping indium nitride At least one of n-type doping InGaN of gallium, n-type doped gallium nitride and the indium component with gradual change.

11. integrated circuit according to claim 1, wherein, the transistor is enhancement mode transistors.

12. integrated circuit according to claim 1, wherein, substrate described in the transistor AND gate is electrically isolated.

13. integrated circuit according to claim 1, wherein, the transistor includes at least one in following geometry Kind：Planar configuration, non-planar configuration, fin-shaped construction, three gate configurations, nano wire construction, grid are around construction, high electron mobility Rate transistor (HEMT) framework, false type HEMT (pHEMT) framework, two dimensional electron gas (2DEG) framework, three-dimensional electronic gas (3DEG) framework, three-dimensional polarization field-effect transistor (FET) framework, MQW (MQW) framework and superlattices framework.

14. a kind of radio frequency (RF) switch, including the integrated circuit according to any one of claim 1-13, wherein, institute State the part that RF switches are on-chip system (SoC) embodiments.

15. a kind of computing system, including integrated circuit according to any one of claim 1-13.

16. a kind of transistor, including：

The pseudo- lining of gallium nitride (GaN) on each fin in multiple fins from lower floor body silicon (Si) substrate Bottom, wherein, the GaN puppets substrate is electrically isolated with the Si substrates；And

Gate stack on channel region, the channel region be located in the GaN puppets substrate and/or on.

17. transistor according to claim 16, wherein, at least one of the Si fins from the substrate Divide and be oxidized to silica, there is provided the electric isolution with the Si substrates.

18. transistor according to claim 16, wherein, on each fin in primary multiple fins The GaN puppets substrate includes multiple GaN puppets substrates, the fin that each GaN puppets substrate is both corresponded in the fin.

19. according to the transistor described in any one of claim 16-18, wherein, the transistor includes following geometry knot At least one of structure：Planar configuration, non-planar configuration, fin-shaped construction, three gate configurations, nano wire construction, grid are around structure Make, HEMT (HEMT) framework, false type HEMT (pHEMT) framework, two dimensional electron gas (2DEG) framework, three Dimensional electron gas body (3DEG) framework, three-dimensional polarization field-effect transistor (FET) framework, MQW (MQW) framework and super brilliant Screen work structure.

20. a kind of method for forming integrated circuit, methods described include：

Multiple fins are formed in the substrate；

Cvd nitride gallium (GaN) layer on the fin；

Aoxidize at least a portion of each fin；And

Transistor is formed in the GaN layer and/or from the GaN layer.

21. according to the method for claim 20, further comprise depositing polarization layer in the GaN layer, wherein, the pole It is one of aluminium nitride, aluminium gallium nitride alloy, indium nitride aluminium and indium nitride gallium aluminium to change layer.

22. in institute before according to the method for claim 20, further comprising depositing the GaN layer on the fin Deposition shallow trench isolates (STI) material between stating fin.

23. according to the method for claim 20, further comprise one or more extra in the GaN layer disposed thereon III-N material layers.

24. according to the method for claim 20, further comprise aoxidize each fin at least a portion it Isolate (STI) material using shallow trench afterwards and underfill is carried out to the gap between the GaN layer and the substrate.

25. according to the method described in any one of claim 20-24, wherein, deposition GaN layer includes on the fin The GaN layer is optionally deposited on the fin, to provide multiple GaN islands, each island corresponds to the fin One of.