CN107706114A - Fin formula field effect transistor and preparation method thereof - Google Patents

Abstract

The present invention discloses a method for manufacturing a Fin Field Effect Transistor, comprising: providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate along a first Extending in the direction, there is a shallow groove around the fin, the shallow groove is filled with a dielectric layer, the upper surface of the dielectric layer is lower than the upper surface of the fin; a barrier layer is formed on the upper surface of part of the dielectric layer, The barrier layer is located on both sides of the fin in the first direction; a first gate is formed, and the first gate is formed on the barrier layer. The invention also provides a corresponding fin field effect transistor. The fin field effect transistor and the preparation method thereof can improve the yield rate and electrical performance of the device.

Description

Fin field effect transistor and its manufacturing method

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a fin field effect transistor and a preparation method thereof.

Background technique

Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and the like. Semiconductor devices include integrated circuits that are formed on a semiconductor wafer by depositing many types of thin film materials over the semiconductor wafer and patterning the thin film materials. Integrated circuits include field effect transistors (FETs), such as metal oxide semiconductor (MOS) transistors.

One of the goals of the semiconductor industry is to continue to shrink the size and increase the speed of individual FETs. To achieve these goals, fin FETs (FinFETs) or multi-gate transistors are used in the 32nm transistor node. FinFETs not only increase areal density, but also enhance gate control of the channel. However, due to the small size of the FinFET, it is difficult to ensure the reliability of the device during the manufacturing process, thereby affecting the yield rate and electrical performance of the product.

Contents of the invention

The object of the present invention is to provide a fin field effect transistor and a manufacturing method thereof, which can improve the yield rate and electrical performance of the device.

In order to solve the above technical problems, the present invention provides a method for preparing a fin field effect transistor, comprising:

Provide semiconductor substrates;

A plurality of fins are formed on the semiconductor substrate, the fins extend along a first direction parallel to the surface of the semiconductor substrate, shallow grooves are formed around the fins, the shallow grooves are filled with a dielectric layer, and the upper surface of the dielectric layer is lower than the upper surface of the fin;

forming a barrier layer on a portion of the upper surface of the dielectric layer, the barrier layer being located on both sides of the fin in the first direction; and

A first gate is formed, the first gate is formed on the blocking layer.

Further, in the manufacturing method of the fin field effect transistor, while forming the first gate, a second gate is also formed, and the second gate is formed along the second gate parallel to the surface of the semiconductor substrate. direction and across the fin and the partially exposed dielectric layer.

Further, in the manufacturing method of the fin field effect transistor, the first direction is perpendicular to the second direction.

Further, in the manufacturing method of the fin field effect transistor, the barrier layer extends along the second direction.

Further, in the manufacturing method of the fin field effect transistor, the first gate extends along the second direction.

Further, in the preparation method of the fin field effect transistor, the preparation method also includes:

forming a protective layer on the top and sidewalls of the first gate and the second gate;

Using the protective layer as a mask, etching the fins to remove the fins on both sides of the first gate and the second gate;

An epitaxial process is performed to form a stress layer on both sides of the first gate and the second gate.

Further, in the preparation method of the fin field effect transistor, the preparation method also includes:

removing the first gate and the second gate, forming a first opening at the position of the first gate, and forming a second opening at the position of the second gate;

A first metal gate is formed in the first opening, and a second metal gate is formed in the second opening.

Further, in the manufacturing method of the fin field effect transistor, the etching selectivity ratio of the material of the second gate and the material of the barrier layer is greater than or equal to 2.

Further, in the manufacturing method of the fin field effect transistor, the material of the barrier layer is nitride or oxide.

Further, in the manufacturing method of the fin field effect transistor, the upper surface of the barrier layer on the dielectric layer is lower than the upper surface of the fin.

Further, in the method for manufacturing a fin field effect transistor, the step of forming a plurality of fins on the semiconductor substrate includes:

forming a patterned mask layer on the semiconductor substrate;

Etching the semiconductor substrate by using the patterned mask layer as a mask, forming the shallow groove in the semiconductor substrate, and forming the fin;

filling the shallow groove with a dielectric to form the dielectric layer;

removing the patterned mask layer;

The dielectric layer is removed on top such that the upper surface of the dielectric layer is lower than the upper surface of the fin.

Further, in the manufacturing method of the fin field effect transistor, the step of forming a barrier layer on the upper surface of part of the dielectric layer includes:

forming a barrier film on the dielectric layer and the fin;

forming a patterned photoresist on the barrier film;

Using the patterned photoresist as a mask, the barrier film is etched to form the barrier layer.

Further, in the manufacturing method of the fin field effect transistor, there is one first gate between two adjacent fins.

According to another aspect of the present invention, a fin field effect transistor is also provided, comprising:

semiconductor substrate;

forming a plurality of fins on the semiconductor substrate, the fins extend along a first direction parallel to the surface of the semiconductor substrate, shallow grooves are formed around the fins, the shallow grooves are filled with a dielectric layer, an upper surface of the dielectric layer is lower than an upper surface of the fin;

a barrier layer formed on a portion of the upper surface of the dielectric layer, the barrier layer being located on both sides of the fin in the first direction; and

A first gate formed on the blocking layer.

Further, in the fin field effect transistor, the fin field effect transistor further includes a second gate, the second gate extends along a second direction parallel to the surface of the semiconductor substrate, and transversely across the fin and the partially exposed dielectric layer.

Further, in the FinFET, the first direction is perpendicular to the second direction.

Further, in the FinFET, the blocking layer extends along the second direction.

Further, in the FinFET, the first gate extends along the second direction.

Further, in the fin field effect transistor, the etching selectivity ratio of the material of the second gate and the material of the barrier layer is greater than or equal to 2.

Further, in the FinFET, the barrier layer is made of nitride or oxide.

Further, in the fin field effect transistor, the upper surface of the blocking layer on the dielectric layer is lower than the upper surface of the fin.

Further, in the fin field effect transistor, there is one first gate between two adjacent fins.

Compared with the prior art, the fin field effect transistor provided by the present invention and its preparation method have the following advantages:

In the manufacturing method of the Fin Field Effect Transistor provided by the present invention, a plurality of fins are formed on the semiconductor substrate, the fins extend along a first direction parallel to the surface of the semiconductor substrate, and the fins are surrounded by There is a shallow groove, the shallow groove is filled with a dielectric layer, the upper surface of the dielectric layer is lower than the upper surface of the fin; a barrier layer is formed on a part of the upper surface of the dielectric layer, and the barrier layer is located on the Fins are on both sides of the first direction; then a first gate is formed, and the first gate is formed on the barrier layer. Since the first gate is provided on both sides of the fin, when the stress layer is subsequently formed, there are symmetrical gate structures (respectively the first gate and the second gate) on both sides of the stress layer. , which is conducive to the formation of the stress layer with a flat surface, avoiding the formation of the stress layer with one side high and the other side low, and can ensure the integrity of the stress layer; and, the first gate passes through the barrier layer Formed on the dielectric layer, when the first gate is subsequently removed, the barrier layer can effectively prevent damage to the surrounding structure, thereby ensuring the reliability of device fabrication and improving product yield and electrical performance .

Further, there is one first gate between two adjacent fins, which can increase the density of the device.

Description of drawings

Fig. 1 is the flowchart of the preparation method of the fin field effect transistor of the first embodiment in the present invention;

2-14 are schematic cross-sectional structure diagrams of the fin field effect transistor in the manufacturing process of the first embodiment of the present invention;

Fig. 15 is a top view of Fig. 6, and Fig. 6 is a sectional view of Fig. 15 along AA' line;

Fig. 16 is the top view of Fig. 8, and Fig. 8 is the sectional view of Fig. 16 along BB' line;

Fig. 17 is the top view of Fig. 9, and Fig. 9 is the sectional view along CC ' line of Fig. 17;

18 is a schematic cross-sectional structure diagram of a fin field effect transistor according to a second embodiment of the present invention;

Fig. 19 is a top view of Fig. 18, and Fig. 18 is a cross-sectional view of Fig. 19 along line DD'.

detailed description

The fin field effect transistor of the present invention and its preparation method will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is represented, and it should be understood that those skilled in the art can modify the present invention described herein and still realize Advantageous effects of the present invention. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be recognized that such a development effort might be complex and time consuming, but would nevertheless be merely a routine undertaking for those skilled in the art.

The core idea of the present invention is to provide a method for preparing a fin field effect transistor, as shown in FIG. 1 , comprising:

Step S11, providing a semiconductor substrate;

Step S12, forming a plurality of fins on the semiconductor substrate, the fins extending along a first direction parallel to the surface of the semiconductor substrate, the fins are surrounded by shallow grooves, and the shallow grooves are filled with a dielectric layer, the upper surface of the dielectric layer is lower than the upper surface of the fin;

Step S13, forming a barrier layer on a part of the upper surface of the dielectric layer, the barrier layer is located on both sides of the fin in the first direction; and

Step S14 , forming a first gate, and the first gate is formed on the barrier layer.

Since the first gate is provided on both sides of the fin, when the stress layer is subsequently formed, there are symmetrical gate structures (respectively the first gate and the second gate) on both sides of the stress layer. , which is conducive to the formation of the stress layer with a flat surface, avoiding the formation of the stress layer with one side high and the other side low, and can ensure the integrity of the stress layer; and, the first gate passes through the barrier layer Formed on the dielectric layer, when the first gate is subsequently removed, the barrier layer can effectively prevent damage to the surrounding structure, thereby ensuring the reliability of device fabrication and improving product yield and electrical performance .

In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

List several embodiments below, to clearly illustrate the content of the present invention, it should be clear that the content of the present invention is not limited to the following examples, and other improvements through conventional technical means by those of ordinary skill in the art are also within the scope of the present invention within the scope of thought.

first embodiment

Referring to FIGS. 2-17 , the fabrication method of the fin field effect transistor of the present invention will be described in detail below.

First, step S11 is performed. As shown in FIG. 2, a semiconductor substrate 100 is provided, and the material of the semiconductor substrate 100 can be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or silicon on insulator (SOI), germanium on insulator (GOI); or other materials, such as III-V compounds such as gallium arsenide, in this embodiment, the semiconductor substrate The material of the bottom 100 is single crystal silicon (Si).

Then, step S12 is performed to form a plurality of fins on the semiconductor substrate 100 . In this embodiment, the step S12 includes the following sub-steps S121 to S125:

Sub-step S121, continuing to refer to FIG. 2, forming a patterned mask layer 101 on the semiconductor substrate 100. The mask layer 101 is preferably a hard mask, which can improve the shape of shallow grooves, for example, The mask layer 101 is a nitride film, or an oxide film and a nitride film stacked sequentially on the semiconductor substrate 100;

Sub-step S122, as shown in FIG. 3, using the patterned mask layer 101 as a mask to etch the semiconductor substrate 100 to form the shallow groove 102 in the semiconductor substrate 100, The semiconductor substrate 100 between the shallow grooves 102 forms the fins 110 ;

Sub-step S123 , as shown in FIG. 4 , filling the shallow trench 102 with a dielectric to form the dielectric layer 103 , generally, the material of the dielectric layer 103 is oxide, such as silicon oxide. In sub-step S123, the dielectric may be deposited first, the dielectric covers the entire mask layer 101 and the shallow groove 102, and then CMP (chemical mechanical polishing) is performed to make the surface of the entire device flat, so The dielectric layer 103 and the shallow trench 102 form shallow trench isolation;

Sub-step S124, as shown in Figure 5, remove the patterned mask layer 101, the process of removing the patterned mask layer 101 can use wet etching process or dry etching process, this is the basic Those of ordinary skill in the art can understand, do not repeat them here;

Sub-step S125, as shown in FIG. 6, remove the dielectric layer 103 at the top, make the upper surface of the dielectric layer 103 lower than the upper surface of the fin 110, and the fin 110 is exposed, remove the top of the The process of the dielectric layer 103 may adopt a wet etching process or a dry etching process, which can be understood by those of ordinary skill in the art and will not be repeated here.

As shown in FIG. 6 and FIG. 15, after step S12, the formed fin 110 extends along the first direction X parallel to the surface of the semiconductor substrate 100, and the fin 110 is surrounded by shallow grooves 102, so The shallow groove 102 defines the position and shape of the fin 110 , the shallow groove 102 is filled with a dielectric layer 103 , and the upper surface of the dielectric layer 103 is lower than the upper surface of the fin 110 .

Next, step S13 is performed, forming a blocking layer on a part of the upper surface of the dielectric layer 103 , the blocking layer is located on both sides of the fin 110 in the first direction X. In this embodiment, the step S13 includes the following sub-steps S131 to S133:

Sub-step S131, as shown in FIG. 7, forming a barrier film 120' on the dielectric layer 103 and the fin 110, the barrier film 120' covering the entire upper surface of the semiconductor substrate 100;

Sub-step S132, forming a patterned photoresist on the barrier film 120', the photoresist exposing the barrier layer on the dielectric layer, which can be understood by those skilled in the art. This is not specifically shown;

In sub-step S133, as shown in FIG. 8 , the barrier film 120' is etched using the patterned photoresist as a mask to form the barrier layer 120.

As shown in FIG. 8 and FIG. 16 , after step S13, the barrier layer 120 extends along the second direction Y, the first direction X is perpendicular to the second direction Y, and is located on the dielectric layer 130 The upper surface of the barrier layer 120 is lower than the upper surface of the fin 110 .

Next, step S14 is performed. As shown in FIG. 9 , a first gate 131 is formed, the first gate 131 is formed on the barrier layer 120, and there is one of the fins 110 adjacent to each other. the first grid 131 . In this embodiment, while forming the first gate 131, the second gate 132 is also formed, as shown in FIG. 9 and FIG. The second direction Y extends across the fin 110 and the partially exposed dielectric layer 102 . The second gate 132 is used to form a device gate, and the first gate 131 is used to form a dummy gate to form a flat stress layer. Preferably, the first grid 131 extends along the second direction Y, and is arranged alternately with the second grid 132 in order to ensure the shape of the stress layer.

Preferably, the etching selectivity ratio between the material of the second gate 132 and the material of the barrier layer 120 is greater than or equal to 2, and in the subsequent process of removing the second gate 132, the barrier layer 120 can be prevented from being destroyed. engraved to wear. In this embodiment, the material of the first gate 131 and the second gate 132 is polysilicon, and the material of the barrier layer 120 is nitride or oxide.

In this embodiment, the fin 110 of the silicon material needs to be removed to form a stress layer, so the following subsequent steps need to be performed:

Subsequently, as shown in FIG. 10 , a protective layer 140 is formed on the top and sidewalls of the first gate 131 and the second gate 132, and the material of the protective layer 140 can be silicon nitride or silicon oxide, etc. ;

After that, as shown in FIG. 11 , using the protection layer 140 as a mask, the fins 110 are etched to remove the fins 110 on both sides of the first gate 131 and the second gate 132 ;

Then, as shown in FIG. 12 , an epitaxial process is performed to form a stress layer 150 on both sides of the first gate 131 and the second gate 132 . Since the two sides of the stress layer 150 have symmetrical gate structures (respectively the first gate 131 and the second gate 132), it is beneficial to form the stress layer 150 with a flat surface, avoiding the formation of one side higher than the other. The stress layer 150 with a lower side can ensure the integrity of the stress layer 150 to ensure the electrical performance of the device.

In this embodiment, the first gate 131 and the second gate 132 need to be removed to form a metal gate, so the following subsequent steps need to be performed:

As shown in Figure 13, another protection layer 160 is formed on the stress layer 150, the material of the other protection layer 160 can be nitride or oxide, etc., with the another protection layer 160 as a mask , remove the first gate 131 and the second gate 132, form a first opening 161 at the position of the first gate 131, and form a second opening at the position of the second gate 132 162.

In the process of removing the first gate 131 and the second gate 132, etching is generally performed by a wet process, and the wet etching solution used includes ammonia (NH ₃ ·H ₂ O), etc., if If the barrier layer 120 is not provided, the wet etching solution may etch part of the semiconductor substrate 100 on the sidewall of the first opening 161 and damage the stress layer 150 to affect the reliability of the device. In this embodiment, since the first gate 131 is formed on the dielectric layer 103 through the barrier layer 120, when the first gate 131 is subsequently removed, the barrier layer 120 can effectively prevent Cause damage to the surrounding structure, thereby ensuring the reliability of device fabrication and improving product yield and electrical performance.

Finally, as shown in FIG. 14 , a first metal gate 171 is formed in the first opening 161 , and a second metal gate 172 is formed in the second opening 162 .

second embodiment

Referring to FIG. 18 and FIG. 19, the fin field effect transistor 1 of the present invention will be described in detail below. The fin field effect transistor 1 can be obtained by the preparation method of the first embodiment, or can be obtained by other methods, which will not be described here. limit. In FIGS. 18 and 19 , reference numerals denote the same structures as those in FIGS. 2 to 17 and represent the same structures as the first embodiment.

18 and 19, the fin field effect transistor 1 includes a semiconductor substrate 100, on which a plurality of fins 110 are formed, and the fins 110 are parallel to the surface of the semiconductor substrate 100. The fin 110 is surrounded by shallow grooves 102 , the shallow grooves 102 are filled with a dielectric layer 103 , and the upper surface of the dielectric layer 103 is lower than the upper surface of the fin 110 . A barrier layer 120 is formed on the upper surface of part of the dielectric layer 103, the barrier layer 120 is located on both sides of the fin 110 in the first direction X, and a first gate 131 is formed on the barrier layer 120 .

In this embodiment, the FinFET 1 further includes a second gate 132, the second gate 132 extends along a second direction Y parallel to the surface of the semiconductor substrate 100, and crosses the The fins 110 and the dielectric layer 103 are partially exposed. The first direction X is perpendicular to the second direction Y.

In this embodiment, the barrier layer 120 extends along the second direction Y, the first gate 131 extends along the second direction Y, and the first gate 131 and the second gate 132 parallel settings. The upper surface of the barrier layer 120 located on the dielectric layer 103 is lower than the upper surface of the fins 110 , and there is one first gate 131 between two adjacent fins 110 .

Preferably, the etching selectivity ratio between the material of the second gate 132 and the material of the barrier layer 120 is greater than or equal to 2, and during the process of removing the second gate 132, the barrier layer 120 can be prevented from being etched. Put on. In this embodiment, the material of the first gate 131 and the second gate 132 is polysilicon, and the material of the barrier layer 120 is nitride or oxide. In addition, the material of the first gate 131 and the second gate 132 is polysilicon, and may also be a material such as metal.

To sum up, the present invention proposes a Fin Field Effect Transistor and a manufacturing method thereof. In the Fin Field Effect Transistor manufacturing method provided by the present invention, a plurality of fins are formed on the semiconductor substrate, and the fins Extending along a first direction parallel to the surface of the semiconductor substrate, the fin is surrounded by a shallow groove, the shallow groove is filled with a dielectric layer, and the upper surface of the dielectric layer is lower than the upper surface of the fin; Forming a barrier layer on the upper surface of part of the dielectric layer, the barrier layer is located on both sides of the fin in the first direction; then forming a first gate, the first gate is formed on the barrier layer superior.

Since the first gate is provided on both sides of the fin, when the stress layer is subsequently formed, there are symmetrical gate structures (respectively the first gate and the second gate) on both sides of the stress layer. , which is conducive to the formation of the stress layer with a flat surface, avoiding the formation of the stress layer with one side high and the other side low, and can ensure the integrity of the stress layer; and, the first grid passes through the barrier layer Formed on the dielectric layer, when the first gate is subsequently removed, the barrier layer can effectively prevent damage to the surrounding structure, thereby ensuring the reliability of device fabrication and improving product yield and electrical performance .

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (22)

1. A method for preparing a fin field effect transistor, comprising: Provide semiconductor substrates; A plurality of fins are formed on the semiconductor substrate, the fins extend along a first direction parallel to the surface of the semiconductor substrate, shallow grooves are formed around the fins, the shallow grooves are filled with a dielectric layer, and the upper surface of the dielectric layer is lower than the upper surface of the fin; forming a barrier layer on a portion of the upper surface of the dielectric layer, the barrier layer being located on both sides of the fin in the first direction; and A first gate is formed, the first gate is formed on the blocking layer. 2. The method for manufacturing a fin field effect transistor according to claim 1, wherein a second gate is also formed while forming the first gate, and the second gate is parallel to the semiconductor substrate. A second direction of the bottom surface extends across the fin and the partially exposed dielectric layer. 3 . The method for manufacturing a fin field effect transistor according to claim 2 , wherein the first direction is perpendicular to the second direction. 4 . 4 . The method for fabricating a fin field effect transistor according to claim 2 , wherein the barrier layer extends along the second direction. 5 . The method for fabricating a fin field effect transistor according to claim 2 , wherein the first gate extends along the second direction. 6. the preparation method of fin field effect transistor as claimed in claim 2 is characterized in that, described preparation method also comprises: forming a protective layer on the top and sidewalls of the first gate and the second gate; Using the protective layer as a mask, etching the fins to remove the fins on both sides of the first gate and the second gate; An epitaxial process is performed to form a stress layer on both sides of the first gate and the second gate. 7. the preparation method of fin field effect transistor as claimed in claim 2 is characterized in that, described preparation method also comprises: removing the first gate and the second gate, forming a first opening at the position of the first gate, and forming a second opening at the position of the second gate; A first metal gate is formed in the first opening, and a second metal gate is formed in the second opening. 8 . The method for manufacturing a fin field effect transistor according to claim 1 , wherein an etching selectivity ratio of the material of the second gate and the material of the barrier layer is greater than or equal to 2. 9 . 9 . The method for manufacturing a fin field effect transistor according to claim 8 , wherein the barrier layer is made of nitride or oxide. 10 . The method for manufacturing a fin field effect transistor according to claim 1 , wherein the upper surface of the barrier layer on the dielectric layer is lower than the upper surface of the fin. 11 . 11. The method for preparing a fin field effect transistor according to any one of claims 1 to 7, wherein the step of forming a plurality of fins on the semiconductor substrate comprises: forming a patterned mask layer on the semiconductor substrate; Etching the semiconductor substrate by using the patterned mask layer as a mask, forming the shallow groove in the semiconductor substrate, and forming the fin; filling the shallow groove with a dielectric to form the dielectric layer; removing the patterned mask layer; The dielectric layer is removed on top such that the upper surface of the dielectric layer is lower than the upper surface of the fin. 12. The method for preparing a fin field effect transistor according to any one of claims 1 to 7, wherein the step of forming a barrier layer on the upper surface of part of the dielectric layer comprises: forming a barrier film on the dielectric layer and the fin; forming a patterned photoresist on the barrier film; Using the patterned photoresist as a mask, the barrier film is etched to form the barrier layer. 13 . The method for manufacturing a fin field effect transistor according to claim 1 , wherein there is one first gate between two adjacent fins. 14 . 14. A fin field effect transistor, characterized in that it comprises: semiconductor substrate; forming a plurality of fins on the semiconductor substrate, the fins extend along a first direction parallel to the surface of the semiconductor substrate, shallow grooves are formed around the fins, the shallow grooves are filled with a dielectric layer, an upper surface of the dielectric layer is lower than an upper surface of the fin; a barrier layer formed on a portion of the upper surface of the dielectric layer, the barrier layer being located on both sides of the fin in the first direction; and A first gate formed on the blocking layer. 15. The fin field effect transistor according to claim 14, wherein the fin field effect transistor further comprises a second gate, and the second gate is along a second gate parallel to the surface of the semiconductor substrate. direction and across the fin and the partially exposed dielectric layer. 16. The FinFET as claimed in claim 15, wherein the first direction is perpendicular to the second direction. 17. The FinFET as claimed in claim 15, wherein the blocking layer extends along the second direction. 18. The FinFET as claimed in claim 15, wherein the first gate extends along the second direction. 19. The fin field effect transistor according to any one of claims 14 to 18, wherein the etching selectivity ratio of the material of the second gate and the material of the barrier layer is greater than or equal to 2. 20. The FinFET as claimed in claim 19, wherein the blocking layer is made of nitride or oxide. 21. The FinFET as claimed in any one of claims 14 to 18, wherein the upper surface of the barrier layer on the dielectric layer is lower than the upper surface of the fin. 22. The fin field effect transistor according to any one of claims 14 to 18, wherein there is one first gate between two adjacent fins.