CN107731952B - radar sensor - Google Patents

Abstract

The present invention relates to the technical field of semiconductor integrated circuits, in particular to a semiconductor radar sensor with a common structure, including a plurality of photoelectric sensors arranged in two-dimensional rows and columns in the vertical and horizontal directions; wherein, the photoelectric sensor includes two triodes, five N transistors and two P transistors. Advantages: The radar sensor solves the problems of easy interference and high power consumption in the field of electromagnetic medium propagation such as electronic tags, unmanned vehicles, and drones.

Description

radar sensor

technical field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a semiconductor radar sensor with a common structure.

Background technique

Radio frequency identification RFID systems are able to detect on a single tag identification unit, each of which can satisfactorily read various parameters over a wide range, but such as temperature and humidity, electromagnetic interference EMI, reader sensitivity, Material properties, and other consequent effects, reduce the reliability of the sensor. A good radio frequency identification RFID integrated circuit is a challenge to the manufacturing process and circuit design, because the radio frequency identification RFID integrated circuit requires extremely low power consumption, large dynamic range, etc. The long-distance reading and writing of radio frequency identification RFID needs to greatly increase the transmission power of the reader, resulting in increased electromagnetic interference, increased cost, and reduced reliability.

Traditional unmanned vehicles, drones and other unmanned automated intelligent IoT devices use radar acoustic sensors to determine the distance from surrounding objects. One method is to scan the radar itself in all directions, and the other method is to use relative For control array radar, these two solutions need to add complex motor equipment to generate additional load. Based on the determined distance, various comfort functions of the unmanned vehicle or drone can be controlled. For example, the speed of unmanned vehicles and unmanned aerial vehicles can be automatically controlled to a predetermined value, wherein it is ensured via a forward distance measurement with the aid of a radar sensor that the speed is not lower than that of a preceding unmanned vehicle. The preset safe distance between vehicles and drones. Other applications of radar sensors include an emergency braking function in the case of rapidly approaching an object, a distance alarm to make it easier for the driver of an unmanned vehicle or drone to maintain contact with a preceding unmanned vehicle , The required safety distance of the UAV.

To sum up, it is necessary to design an anti-jamming, low-power semiconductor radar sensor with a common structure that can be applied to electronic tags, unmanned vehicles, and drones.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention proposes a semiconductor radar sensor with a shared structure, which solves the problems of easy interference and high power consumption in the field of electromagnetic medium propagation such as electronic tags, unmanned vehicles, and drones.

To achieve the above object, the present invention adopts the following technical solutions:

The present invention proposes a semiconductor radar sensor with a common structure. The radar sensor includes a plurality of photoelectric sensors arranged in two-dimensional rows and columns in the vertical and horizontal directions. It is characterized in that the photoelectric sensor includes: two triodes, Six N transistors and two P transistors;

The collector and the emitter of the first triode (T1) are simultaneously connected to the drain of the first N transistor (N1) and the gate of the fourth N transistor (N4);

The base of the first triode (T1) and the drain of the fourth N transistor (N4) are simultaneously connected to the power supply voltage VDD;

The drain of the fifth N transistor (N5) is connected to the source of the first N transistor (N1), the gate is connected to the gate of the sixth N transistor (N6), and the source is grounded;

The drain of the sixth N transistor (N6) is connected to the source of the second N transistor (N2), the gate is connected to the gate of the fifth N transistor (N5), and the source of the fourth N transistor (N4) , the source is grounded;

The base of the second triode (T2) is connected to the gate and drain of the second P transistor (P2) and the gate of the first P transistor (P1), and the collector and emitter are grounded simultaneously;

The drain of the first P transistor (P1) is connected to the drain of the second N transistor (N2), and the source and the source of the second P transistor (P2) are simultaneously connected to the power supply voltage VDD;

Both the first transistor (T1) and the second transistor (T2) are photosensitive transistors.

Preferably, at least one inverting circuit is included, the inverting circuit includes a third P transistor (P3), a third N transistor (N3), and the third P transistor (P3) and the third N transistor (N3) It is connected in series between the power supply terminal and the ground, the source of the third P transistor (P3) is connected to the power supply terminal, the gate of the third N transistor (N3) is connected to the gate of the third P transistor (P3) At the same time, it is connected to the source of the second N transistor (N2), the source is grounded, and the drain is connected to the drain of the third P transistor (P3), and an induction electrical signal is output.

Preferably, the entire area of the photosensitive region of the first triode (T1) receives light irradiation, and the area of the emission region of the second triode (T2) receives light irradiation according to a preset ratio.

Preferably, the preset ratio value depends on the ratio of the width of the first P transistor (P1) to the width of the second P transistor (P2).

Preferably, the conduction level of the first triode (T1) is consistent with the conduction level of the second triode (T2).

Preferably, the lengths of the first N transistor (N1) and the second N transistor (N2) are equal.

Preferably, the width of the first P transistor (P1) or the second N transistor (N2) is 1-20 times the width of the second P transistor (P2).

Preferably, the transistor is one or more of a field effect transistor and a bipolar transistor.

Preferably, the first P transistor (P1), the second P transistor (P2) and the third P transistor (P3) are PMOS transistors, the first N transistor (N1), the second N transistor (N2), the third The N transistor (N3), the fourth N transistor (N4), the fifth N transistor (N5) and the sixth N transistor (N6) are NMOS transistors.

Preferably, the photoelectric sensor is arranged between grid lines in two adjacent rows or columns.

Beneficial effects of the present invention: The semiconductor radar sensor with a common structure of the present invention solves the problems of easy interference and high power consumption in the field of electromagnetic medium propagation such as electronic tags, unmanned vehicles, and drones.

Description of drawings

In order to further illustrate the present invention with the accompanying drawings, the embodiments in the accompanying drawings do not constitute any limitation to the present invention.

FIG. 1 is a structural schematic diagram of an embodiment of a semiconductor radar sensor with a common structure according to the present invention.

Detailed ways

The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and embodiments, which are preferred embodiments of the present invention. A semiconductor radar sensor with a common structure provided by the embodiment of the present invention can be applied to various scenarios in the field of intelligent identification technology of the Internet of Things, including but not limited to 2G GSM, 3G CDMA, 4G LTE/LTE-A, 5G eMBB Systems such as mobile communication, trunking communication, satellite communication, laser communication, optical fiber communication, digital TV, radio frequency identification, power carrier, unmanned vehicle, unmanned aerial vehicle, Internet of Things, radar, etc., are not particularly limited in the embodiments of the present invention.

As shown in Fig. 1, the present invention proposes a kind of semiconductor radar sensor with common structure, and radar sensor comprises a plurality of photoelectric sensors arranged in vertical and horizontal directions into two-dimensional row and column distribution, it is characterized in that, photoelectric sensor comprises: two The triode, six N transistors and two P transistors; the photoelectric sensor is arranged between the gate lines of two adjacent rows or columns, and the present invention does not specifically limit other arrangements with equivalent functions.

The collector and the emitter of the first triode (T1) are simultaneously connected to the drain of the first N transistor (N1) and the gate of the fourth N transistor (N4);

The base of the first triode (T1) and the drain of the fourth N transistor (N4) are simultaneously connected to the power supply voltage VDD;

The drain of the fifth N transistor (N5) is connected to the source of the first N transistor (N1), the gate is connected to the gate of the sixth N transistor (N6), and the source is grounded;

The drain of the sixth N transistor (N6) is connected to the source of the second N transistor (N2), the gate is connected to the gate of the fifth N transistor (N5), and the source of the fourth N transistor (N4), and the source pole grounding;

The base of the second triode (T2) is connected to the gate and drain of the second P transistor (P2) and the gate of the first P transistor (P1), and the collector and emitter are grounded simultaneously;

The drain of the first P transistor (P1) is connected to the drain of the second N transistor (N2), and the source and the source of the second P transistor (P2) are simultaneously connected to the power supply voltage VDD;

Both the first transistor (T1) and the second transistor (T2) are photosensitive transistors.

In this embodiment, at least one inverter circuit is included, the inverter circuit includes a third P transistor (P3), a third N transistor (N3), and the third P transistor (P3) and the third N transistor (N3) are connected to the power supply Terminal and ground are connected in series, the source of the third P transistor (P3) is connected to the power supply terminal, the gate of the third N transistor (N3) and the gate of the third P transistor (P3) are connected to the second N The source of the transistor (N2), the source is grounded, and the drain is connected to the drain of the third P transistor (P3), and outputs an induction electrical signal.

The entire area of the photosensitive area of the first triode (T1) receives light irradiation, and the area of the emission area of the second triode (T2) receives light irradiation according to a preset ratio. In this embodiment, the preset ratio depends on the ratio of the width of the first P transistor ( P1 ) to the width of the second P transistor ( P2 ).

The conduction level of the first triode (T1) is consistent with the conduction level of the second triode (T2).

In this embodiment, the first P transistor (P1), the second P transistor (P2) and the third P transistor (P3) are PMOS transistors, the first N transistor (N1), the second N transistor (N2), the third The N transistor (N3), the fourth N transistor (N4), the fifth N transistor (N5) and the sixth N transistor (N6) are NMOS transistors.

It should be noted that the transistor may be one or more of a field effect transistor and a bipolar transistor. The transistor may also be a structure in which the gate of a depletion-type N-channel MOS transistor is connected to the source. Although not shown in the figure, it may of course also be a structure in which the gate of a depletion-type P-channel MOS transistor is connected to the source. structure.

The sum of the output currents of the phototransistors T1 and T2 when they are illuminated is called photocurrent, and the magnitude of the photocurrent is proportional to the intensity of the light signal. The phototransistors T1 and T2 used as sensors, what kind of photocurrent will be output when they are exposed to what degree of light, this is known, and a table can even be listed in a small step to show the two The specific value and corresponding relationship.

The photocurrent reaches the drain terminal current of the first P transistor (P1) and the second P transistor (P2) through the transmission and amplification of the first P transistor (P1) and the second P transistor (P2). The ratio of the widths of the first P transistor (P1) to the second P transistor (P2) determines the magnification of the photocurrent. In this embodiment, the width of the first P transistor (P1) or the second N transistor (N2) is 1-20 times the width of the second P transistor (P2). Moreover, the lengths of the first N transistor (N1) and the second N transistor (N2) are equal.

The sensor circuit in this embodiment can realize the detection of illuminance from 300-30000 lux, and has the characteristics of small area, low power consumption, and sensitive response. All devices in the sensor circuit can be implemented by standard CMOS technology, which can be used in semiconductor chips.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (8)

1. A semiconductor radar sensor, the radar sensor including a plurality of photosensors arranged in a two-dimensional row and column arrangement in vertical and horizontal directions, the photosensor comprising: two triodes, six N transistors and two P transistors;

a collector and an emitter of the first triode (T1) are simultaneously connected to a drain of the first N transistor (N1) and a gate of the fourth N transistor (N4);

the base electrode of the first triode (T1) and the drain electrode of the fourth N transistor (N4) are simultaneously connected with a power supply voltage VDD;

the drain electrode of the fifth N transistor (N5) is connected with the source electrode of the first N transistor (N1), the grid electrode of the fifth N transistor is connected with the grid electrode of the sixth N transistor (N6), and the source electrode of the fifth N transistor is grounded;

the drain electrode of the sixth N transistor (N6) is connected with the source electrode of the second N transistor (N2), the grid electrode of the sixth N transistor (N6) is connected with the grid electrode of the fifth N transistor (N5) and the source electrode of the fourth N transistor (N4), and the source electrode of the sixth N transistor is grounded;

the base electrode of the second triode (T2) is connected with the grid electrode and the drain electrode of the second P transistor (P2) and the grid electrode of the first P transistor (P1), and the collector electrode and the emitter electrode are grounded simultaneously;

the drain electrode of the first P transistor (P1) is connected with the drain electrode of the second N transistor (N2), and the source electrode of the first P transistor (P1) and the source electrode of the second P transistor (P2) are simultaneously connected with a power supply voltage VDD;

the first triode (T1) and the second triode (T2) are phototriodes;

the whole area of the photosensitive area of the first triode (T1) receives light irradiation, and the area of the emitting area of the second triode (T2) receives light irradiation according to a preset proportional value;

the preset proportional value depends on the ratio of the width of the first P transistor (P1) to the width of the second P transistor (P2).

2. The radar sensor according to claim 1, further comprising at least one inverter circuit, wherein the inverter circuit comprises a third P transistor (P3) and a third N transistor (N3), the third P transistor (P3) and the third N transistor (N3) are connected in series between a power supply terminal and ground, a source of the third P transistor (P3) is connected to the power supply terminal, a gate of the third N transistor (N3) and a gate of the third P transistor (P3) are connected to a source of the second N transistor (N2), the source is connected to ground, the drain is connected to a drain of the third P transistor (P3), and the inverter circuit outputs the sensing electrical signal.

3. A radar sensor according to claim 1, characterized in that the conduction level of the first transistor (T1) coincides with the conduction level of the second transistor (T2).

4. The radar sensor of claim 1, characterized in that the first N transistor (N1) and the second N transistor (N2) are of equal length.

5. Radar sensor according to claim 1, characterised in that the width of the first P-transistor (P1) or the second N-transistor (N2) is 1-20 times the width of the second P-transistor (P2).

6. The radar sensor according to any one of claims 1 to 5, wherein the transistor is one or more of a field effect transistor and a bipolar transistor.

7. The radar sensor of claim 6, wherein the first P transistor (P1) and the second P transistor (P2) are PMOS transistors, and the first N transistor (N1), the second N transistor (N2), the fourth N transistor (N4), the fifth N transistor (N5) and the sixth N transistor (N6) are NMOS transistors.

8. The radar sensor of claim 2, wherein the third P transistor (P3) is a PMOS transistor and the third N transistor (N3) is an NMOS transistor.

Images