CN107741523B - A time-domain signal measurement device based on PLL phase-locked loop - Google Patents

Abstract

The invention relates to a time domain signal measurement device based on a PLL phase-locked loop, comprising a normalization module, a VCXO module, a frequency measuring instrument, a single-chip microcomputer, a compensation module and a PLL loop unit; The time-domain signal measurement device, using the signal feedback loop to reduce the PLL frequency shift method, and the improved final VCXO output frequency signal device, will be connected with the measurement system at the user end with a more stable and accurate output signal .

Description

A time-domain signal measurement device based on PLL phase-locked loop

technical field

The invention relates to the field of signal measurement, in particular to a time-domain signal measurement device based on a PLL phase-locked loop.

Background technique

Phase locked loop (phase locked loop), as the name suggests, is a loop that locks the phase. Anyone who has studied the principle of automatic control knows that this is a typical feedback control circuit, which uses the externally input reference signal to control the frequency and phase of the oscillating signal inside the loop, and realizes the automatic tracking of the frequency of the output signal to the frequency of the input signal. For closed-loop tracking circuits. It is a method to make the frequency more stable in radio transmission, mainly including VCXO (voltage controlled oscillator) and PLL IC (phase locked loop integrated circuit). Compare the phase between the frequency and the local oscillator signal generated by the PLL IC. In order to keep the frequency unchanged, it is required that the phase difference does not change. If there is a change in the phase difference, the voltage of the voltage output terminal of the PLL IC changes to control the VCXO. Until the phase difference is recovered, the purpose of phase locking is achieved. A closed-loop electronic circuit that maintains a controlled oscillator's frequency and phase in a deterministic relationship to the input signal.

In the actual PLL circuit environment, we will ignore another key parameter, that is, the influence of the amplitude of the signal in the entire PLL circuit and the accuracy of the output frequency of the final voltage-controlled oscillator VCXO. At present, there is no detailed research on this technology in the relevant domestic literature reports, resulting in the phenomenon that most PLL phase-locked loops have poor working stability.

Frequency stability evaluation of time-domain frequency signals is an important aspect of time-frequency research work. For a signal source, its output signal is usually expressed by the following formula:

表示信号源输出信号的相位(也即是频率)随时间的随机起伏，Δ·t表示信号源输出信号的频率随时间的微小单向变化，称之为频率漂移，现在比较好的VCXO一般在几×10^-12－×10^-14量级。Among them, a(t) represents the random amplitude fluctuation of the output signal of the signal source with time,

It represents the random fluctuation of the phase (that is, the frequency) of the output signal of the signal source with time, and Δ t represents the small one-way change of the frequency of the output signal of the signal source with time, which is called frequency drift. Now the better VCXO is generally in Several × 10 ^-12 - × 10 ^-14 magnitude.

Δ·t originates from the internal aging of the signal source over time, and the introduced output frequency changes in one direction.

源于组成信号源的各部件噪声对整机频率稳定度的贡献，通常认为，组成信号源的各部件噪声引起的整机输出频率起伏是各态历经的，因此它可以用随机统计理论中的方差表征。

From the contribution of the noise of each component that composes the signal source to the frequency stability of the whole machine, it is generally believed that the fluctuation of the output frequency of the whole machine caused by the noise of each component that composes the signal source is ergodic, so it can be used in random statistical theory. Variance representation.

In the early days, the standard deviation of the relative frequency offset fluctuation was used to characterize the frequency stability of the signal source. If f0 is the average frequency of the signal source, then within the sampling time τ, the relative frequency offset of the output frequency is:

Studies have shown that for the output signals of various signal sources, the magnitude and speed of the relative frequency offset fluctuation y _τ (t) of the output frequency are affected by the five kinds of noises listed in the power-law spectrum noise model. The noise model is:

In the formula, α=-2,-1,0,1,2; 0<f<f _h , h _α is a constant, the size depends on the specific signal source; f _h is the high cut-off frequency of the system.

The actual use shows that the frequency of the measured frequency source has a limited range when entering the measuring instrument, which is one of the defects; secondly, the frequency instability of the external reference clock itself will also bring errors to the system measurement.

The above problems need to be solved.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to propose a time-domain signal measurement device based on a PLL phase-locked loop with a more stable and accurate output signal.

The technical scheme proposed by the present invention to solve the above technical problems is: a time-domain signal measurement device based on a PLL phase-locked loop, comprising a normalization module, a VCXO module, a frequency measuring instrument, a single-chip microcomputer, a compensation module and a PLL loop unit;

The VCXO module is suitable for outputting a high-stability external reference source clock signal, and the external reference source clock signal is respectively sent to the normalization module and the frequency measuring instrument;

The normalization module is suitable for normalizing the measured frequency signal under the action of the external reference source clock to obtain a standard 1MHz verification frequency signal and output it to the frequency measuring instrument;

The frequency measuring instrument is suitable for performing time-domain frequency measurement on the signal frequency output by the normalization module according to the sampling time T=10 seconds under the action of an external reference source clock, and sending the measurement result to an external computer;

The compensation module is adapted to compensate and control the output error frequency of the VCXO module;

The single chip microcomputer is suitable for parameter control of the normalization module, the frequency measuring instrument and the compensation module;

The PLL unit is adapted to close-loop control the accuracy of the output frequency of the VCXO module through a precise signal frequency.

Further, the PLL loop unit includes a PLL loop module, a pre-amplifier module, a signal feedback module and a final-stage amplifier module, and the frequency signal obtained by the PLL loop module passes through the pre-stage before the synchronous phase detection process is performed. Amplify the RF signal and send it to the signal feedback module for processing;

The single-chip microcomputer obtains the relevant parameter information of the radio frequency signal through the access to the signal feedback module. The relevant parameter information includes the maximum amplitude, minimum amplitude and peak-to-peak value of the signal. Under the control of the single-chip microcomputer, it will be sent to the pre-amplifier of the final amplifier module. The parameters of the signal are repaired, and the synchronous phase detection function of the traditional PLL phase-locked loop is completed;

After synchronous phase discrimination, the voltage-controlled voltage signal is obtained and then acts on the VCXO module to complete the PLL phase-locked loop.

Further, the normalization module includes a first isolation amplifier, a first DDS module and a second DDS frequency dividing unit, and the reference frequency signal f0 of the external reference source clock is sent to the first DDS after passing through the first isolation amplifier. The external clock input end of the module is used as the working external reference clock of the first DDS module, and the external communication port of the first DDS module is connected to the single-chip microcomputer for receiving control word commands from the single-chip computer and bidirectional data transmission;

The second DDS frequency dividing unit includes a second isolation amplifier, a second DDS module, a travel time counter, a latch, a third DDS module and a filter module; the second isolation amplifier is respectively connected to the second DDS module and the filter module. The third DDS module, the second DDS module, the first time counter and the first latch form a signal connection in sequence, the third DDS module is connected to the filtering module; the second DDS module and the third DDS The external communication ports of the module are respectively connected to the single-chip microcomputer to receive the control word command from the single-chip microcomputer and bidirectional data transmission.

Further, the frequency measuring instrument includes a third isolation amplifier, a second travel time counter, a second latch, a fourth isolation amplifier, a third travel time counter and a third latch; the third isolation amplifier, the second The travel time counter and the second latch form a signal connection in sequence; the fourth isolation amplifier, the third travel time counter and the third latch form a signal connection in sequence; the third isolation amplifier and the fourth isolation amplifier are also respectively connected to In the single-chip microcomputer, the controlled ends of the second travel-time counter and the third travel-time counter are respectively connected to the control end of the single-chip microcomputer, and the read end of the single-chip microcomputer is also connected to the second latch and the third Latches.

Further, the compensation module includes a first voltage reference module, a second voltage reference module, a D/A module and a temperature control module;

The first voltage reference module is suitable for providing a stable voltage output to the VCXO module;

The second voltage reference module is suitable for providing a stable voltage reference to the external voltage reference terminal of the D/A module;

The temperature control module is arranged on the outer wall of the VCXO module and includes a temperature control chip and a second thermistor, and the temperature control module is adapted to detect the working temperature of the VCXO module and send the result to the single-chip microcomputer;

The D/A module is adapted to output a variable-sized DC voltage value under the control of the single-chip microcomputer, and send it to the VCXO module.

The beneficial effects of the present invention are:

The present invention adopts the time-domain signal measurement device based on PLL phase-locked loop, uses the signal feedback loop to reduce the PLL frequency shift method, and provides an improved final VCXO output frequency signal device, which will be more stable and accurate. The output signal is connected with the measurement system of the user end.

Description of drawings

The time domain signal measuring device based on the PLL phase-locked loop of the present invention will be further described below with reference to the accompanying drawings.

1 is a structural block diagram of a time domain signal measuring device based on a PLL phase-locked loop in the present invention;

Fig. 2 is the structural block diagram and working principle diagram of the PLL loop unit;

Fig. 3 is the structural block diagram of the normalization module;

Fig. 4 is the structural block diagram of the second DDS frequency dividing unit;

Figure 5 is a block diagram of the structure and working principle of the compensation module;

6 is a circuit diagram of a temperature control module;

Figure 7 is a schematic diagram of the compensation module;

Fig. 8 is the frequency measurement schematic diagram of the signal;

Fig. 9 is the structural principle block diagram of the frequency measuring instrument;

FIG. 10 is a circuit scheme diagram of the signal feedback module.

Detailed ways

Example

As shown in FIG. 1 , the time domain signal measurement device based on the PLL phase-locked loop in the present invention includes a normalization module, a VCXO module, a frequency measuring instrument, a single-chip microcomputer, a compensation module and a PLL loop unit.

The VCXO module is suitable for outputting a high-stability external reference source clock signal, and the external reference source clock signal is sent to the normalization module and the frequency measuring instrument respectively;

The normalization module is suitable for normalizing the measured frequency signal under the action of the external reference source clock to obtain a standard 1MHz verification frequency signal and output it to the frequency measuring instrument.

As shown in FIG. 3 , it may be preferred that the normalization module includes a first isolation amplifier, a first DDS module and a second DDS frequency dividing unit.

The reference frequency signal f0 is sent to the external clock input terminal of the first DDS module after passing through the first isolation amplifier, as the external reference clock of the first DDS module operation. MCU control word command and bidirectional data transmission. The actually selected DDS chip has two 48-bit frequency control registers (F0, F1). For this device, the reference frequency signal f0 is 10MHz. When the DDS internal PLL frequency multiplication function is not used, the 48-bit frequency control register F0 is fully filled. When 1, the DDS will output a 10MHz frequency signal, so in order to obtain the standard sampling time period signal T (such as 1 second, 10 seconds), it is necessary to set the corresponding frequency division value in the frequency control register F0 in the DDS. The specific calculation method is :

Among them, D is the specific frequency division value that needs to be calculated, f0 is the reference signal frequency, f0 in this device is 10MHz, f is the sampling time signal frequency of the frequency division required, for f is 1Hz (1 second) and 0.1Hz ( 10 seconds), the frequency division value D should be 248×10-7 or 248×10-8. The specific sampling time T is set by the user through the PC software according to the needs of the actual sampling process, and the frequency division value is obtained after the single-chip microcomputer communicates with the PC through the RS232 serial interface to obtain the sampling time T set by the user, using formula (4 ) is calculated. According to the serial communication sequence corresponding to the first DDS module, the microcontroller writes the frequency division value D into the corresponding buffer of the first DDS module to obtain the final first DDS module terminal sampling time signal T for output.

When the frequency of the measured signal is hundreds of megahertz or even hundreds of megahertz, considering the limitation of the time counter on the measured frequency range, as shown in Figure 4, the second DDS frequency dividing unit includes a second isolation amplifier, a second DDS module , travel time counter, latch, third DDS module and filter module; the second isolation amplifier is connected to the second DDS module and the third DDS module respectively, the second DDS module, the first travel time counter and the first latch are formed in turn Signal connection, the third DDS module is connected to the filtering module; the external communication ports of the second DDS module and the third DDS module are respectively connected to the single-chip microcomputer for receiving control word commands from the single-chip microcomputer and bidirectional data transmission.

In this patent, the second DDS module is designed to perform 1/100 frequency division processing on the measured frequency signal. The measured signal is directly sent to the external clock input terminal of the second DDS module after passing through the second isolation amplifier, and is used as the reference clock when the second DDS module is working. The external communication port of the second DDS module is connected to the single-chip microcomputer, and the 248×10-2 frequency division value obtained by the single-chip microcomputer according to the formula (4) is written into the buffer area of the second DDS module through the serial communication sequence, and the 1 obtained by the second DDS module is 1. After the frequency signal is divided by 100, it is sent to the first travel counter for rough frequency measurement. After reading the value sampled by the first latch on the first travel counter, the single-chip microcomputer records the frequency value at this time and multiplied by 100. Obtain the coarse frequency value F of the measured signal.

其中F为通过第一走时计数器计数、单片机运算得到的被测信号的粗频率值，f取1MHz，并通过串行通讯时序将所得的具体分频数值写入第三DDS模块缓存区，经第三DDS模块后得到1MHz的频率信号，将所得的频率信号再送至低通滤波模块后得到最终的1MHz频率信号输出。The signal under test passing through the second isolation amplifier is sent to the external clock input end of the third DDS module as a reference clock when the third DDS module works. At the same time, the external communication port of the third DDS module is connected to the single-chip microcomputer, and the single-chip microcomputer calculates the frequency division value for communication with the third DDS module according to formula (4):

Among them, F is the rough frequency value of the measured signal obtained by the first travel counter and the operation of the single-chip microcomputer, f is 1MHz, and the specific frequency division value obtained is written into the third DDS module buffer area through the serial communication sequence After the three DDS modules, a 1MHz frequency signal is obtained, and the obtained frequency signal is sent to the low-pass filter module to obtain the final 1MHz frequency signal output.

The compensation module is suitable for compensating and controlling the output error frequency of the VCXO module.

As shown in FIG. 5 , it may be preferred that the compensation module includes a first voltage reference module, a second voltage reference module, a D/A module and a temperature control module. The first voltage reference module is adapted to provide a stable voltage output to the VCXO module. The second voltage reference module is adapted to provide a stable voltage reference to the external voltage reference terminal of the D/A module. The temperature control module is arranged on the outer wall of the VCXO module and includes a temperature control chip and a second thermistor. The temperature control module is suitable for detecting the working temperature of the VCXO module and sending the result to the single-chip microcomputer. The D/A module is suitable for outputting a variable DC voltage value under the control of the single-chip microcomputer, and sends it to the VCXO module.

As shown in Figure 6, the two R and R1 are resistors with the same temperature coefficient, and their resistance values should be selected to be equivalent to Rk. The value of R1 here reflects the actual working environment temperature T of the VCXO. Rk is a thermistor, which is attached to the surface of the VCXO to sense the actual working ambient temperature T of the VCXO. Therefore, when the working environment temperature T of the VCXO does not change, the bridge in the above figure is in balance, and the temperature compensation voltage sent to the voltage-controlled conversion module is 0. Once the working environment temperature T of the VCXO changes, the resistance value of the thermistor Rk will become smaller (temperature rises) or becomes larger (temperature drops), then there is a voltage difference across the bridge, after differential amplification by operational amplifier A A temperature compensated voltage is delivered to the voltage source and output to the conventional heating wire coil loop. The amplification gain of the whole circuit is adjusted by the negative feedback resistor Rw of the operational amplifier, Rw is a digital potentiometer, and the above-mentioned circuit compensation factor changing function can be achieved by adjusting the resistance value of Rw.

In the compensation module setup, we performed component screening:

Voltage reference 1 and voltage reference 2 have the same temperature coefficient, that is, for every 10C change in temperature, the corresponding voltage reference reference value changes are the same, for example: -1E-3 (V/0C).

According to the temperature characteristic curve of VCXO, the specific operating temperature point of VCXO is set by the microcontroller, so that the VCXO has the opposite temperature characteristics to the above-mentioned 1 voltage reference around this operating point (the above is a negative temperature coefficient, then correspondingly select VCXO as a positive temperature coefficient), for example, select the specific value: +1E-10/0C, that is, every 10C change in temperature will cause the VCXO output signal frequency to change +1E-10.

Combined with the above 1, select the corresponding VCXO voltage control slope value, such as 1E-7/V, because the voltage reference acts on the VCXO to make it output different frequencies, then after combining with 1, we can obtain the voltage reference change caused by the corresponding temperature change. The frequency change rate of the output signal caused by acting on the VCXO is:

-1E-3(V/0C)×1E-7(V)=-1E-10/0C

Select a VCXO with a smaller aging drift rate, for example: -1E-6/year, which is converted to 365 days a year: -2.7E-9/day.

As shown in Figure 7, the curve part (VCXO output) expresses the frequency sampling curve of the traditional VCXO output. It can be seen from the curve part of the figure that in the whole sampling process, the VCXO output will have a large fluctuation point: the upper limit of frequency fluctuation and the lower limit of frequency fluctuation. This is extremely unfavorable for some occasions that have strict requirements on the absolute value of frequency, such as missile precision guidance and GPS precision navigation. The specific compensation embodiments of this patent are as follows:

1. On the basis of the traditional VCXO process, first make VCXO, voltage reference 1 and voltage reference 2 all work at the operating temperature point required by the solution, such as T=200C, then VCXO will have a positive temperature coefficient +1E-10/0C , the voltage reference 1 and the voltage reference 2 will have a negative temperature coefficient -1E-3/0C, and the corresponding frequency change rate of the VCXO output signal is: -1E-10/0C. During the normal operation of the VCXO, due to the limitation of the temperature control effect, the internal working modules VCXO, voltage reference 1, and voltage reference 2 will be affected by temperature fluctuations, but according to the implementation of the above scheme 1, the temperature-induced VCXO positive frequency The change value will and the temperature-induced voltage reference act on the negative frequency change value of the VCXO to neutralize to 0. The problem of VCXO output frequency change caused by temperature change is solved here.

2. The voltage control slope data of the VCXO is recorded inside the single-chip microcomputer, and the relationship of "voltage-frequency" is established, that is, to achieve the expected range of f1 and f2 in the figure, the processor records the corresponding voltage values V1 and V2. Here, it is realized that the VCXO output frequency is controlled within a small range, that is, the expected value box shown in the figure is realized.

3. Combined with the selected VCXO aging drift data: -2.7E-9/day, and the voltage control slope value of VCXO: 1E-7/V, the single-chip microcomputer makes the corresponding main adjustment to the correction voltage V according to the day, that is, the correction voltage is made every day. On the basis of the above 2 technologies, plus a fixed correction value, such as: 27mV, then the corresponding VCXO output frequency increases by 1E-7/V×27mV=+-2.7E-9, which can compensate the VCXO because The effect of frequency changes due to aging drift. The solution here will enable the above-mentioned 2 to obtain a better implementation effect.

The frequency measuring instrument is suitable for measuring the frequency of the signal output by the normalization module according to the sampling time T=10 seconds under the action of the external reference source clock, and sending the measurement result to the external computer.

As shown in FIG. 8 and FIG. 9 , it can be preferred that the frequency measuring instrument includes a third isolation amplifier, a second travel time counter, a second latch, a fourth isolation amplifier, a third travel time counter and a third latch . The third isolation amplifier, the second travel time counter and the second latch form a signal connection in sequence; the fourth isolation amplifier, the third travel time counter and the third latch form a signal connection in sequence; the third isolation amplifier and the fourth isolation amplifier also They are respectively connected to the microcontroller, the controlled ends of the second travel counter and the third travel counter are respectively connected to the control end of the microcontroller, and the read end of the microcontroller is also connected to the second latch and the third latch respectively.

The 1MHz frequency signal and 10MHz reference clock signal obtained after the measured frequency signal is processed by the DDS frequency division unit are sent to the frequency measuring instrument respectively. As shown in Figure 4 and Figure 5, the single-chip microcomputer enables two frequency signals to measure according to the rising edge of the sampling time signal T obtained after the reference clock signal is processed by the first DDS module. Specifically: after the rising edge of one sampling signal T , when the rising edge of the measured signal and the external reference clock signal arrives, the microcontroller enables the second travel counter and the third travel counter to count the frequency respectively. After a falling edge of the sampling signal T, when the measured signal and the rising edge of the external reference clock signal arrive, the single-chip microcomputer enables the second time counter and the third time counter to end frequency counting, and obtains a complete sample in the above figure. The total number of pulses N1 and N2 of the signal under test and the external reference clock signal within the signal T time. The second latch and the third latch are enabled to latch the count values of the second travel counter and the third travel counter respectively. Suppose the frequency of the measured signal is Fx, the frequency of the reference time base is fo (10MHz in practice), and within the gate time T, the counts of the measured signal and the reference time base by the counter are N1 and N2, respectively, there are:

It can be known from the formula (5) that the frequency fx of the measured signal is related to the reference time base frequency fo and the count values N1 and N2 of the two counters. During a complete sampling period T, the reading values N1 and N2 of the second travel-time counter and the third travel-time counter saved by the second latch and the third latch are transmitted to the microcontroller. In formula (5), we consider the reference The clock source frequency fo is constant, that is, 10MHz, so we can easily obtain the frequency value fx of the signal under test.

The PLL unit is suitable for closed-loop control of the accuracy of the output frequency of the VCXO module through precise signal frequency. Among them, it can be preferred that: as shown in FIG. 2 , the PLL loop unit includes a PLL loop module, a pre-amplifier module, a signal feedback module and a final-stage amplifier module, and the frequency signal obtained by the PLL loop module is not synchronized. Before the phase detection process, the RF signal is obtained through the pre-amplification and sent to the signal feedback module for processing.

The frequency signal output by the VCXO module is sent to the calibration module, and the signal frequency is corrected under the control of the single-chip microcomputer and then output to the user end.

Regarding the signal feedback module, as shown in Figure 10, the pre-amplified signal is sent to the operational amplifiers A1 and A3 respectively, and the pre-amplified signal is sent to A2 after A3. A4 and A5 are voltage followers, and the voltage amplitudes of their output terminals V11 and V12 are the same as the voltages on capacitors C1 and C2 (the function of adding a first-level follower is to use this follower to provide current support). V11 and V12 are respectively sent to the inverting and non-inverting terminals of A6 to complete the N(V12-V11) operation.

Among them, A1 and A4 complete the detection of the maximum peak value of the pre-amplification signal:

When the voltage of the pre-amplified signal is greater than the voltage of the capacitor C1, a voltage drop occurs on the resistor Rf, and the current flows from left to right. According to the virtual break rule of the op amp, D11 will not be turned on. At this time, the charging current goes through D12 to C1. When the voltage of the pre-amplified signal is lower than the voltage of the capacitor C1, a voltage drop occurs on the resistor R2, and the current flows from right to left. According to the virtual break rule of the op amp, D12 will not be turned on, at this time, the current only enters A1 through D11. Since the output voltage of the voltage follower A4 is the same as the voltage on the capacitor C1, the diode D11 is turned off, the capacitor cannot discharge through D11, and the voltage is protected, that is, the output V11 of the capacitor C1 and A4 records the maximum peak value of the pre-amplified signal. Capacitor C1 has a discharge resistor R1, and the discharge time constant τ of RC is set according to the actual cycle of the pre-amplified signal. For example, the frequency of the pre-amplified signal is 79Hz, then τ can be taken as 1S. At the same time, V11 is sent to A/D sampling 1 to obtain the corresponding voltage value and transfer it to the microcontroller.

A3 completes the pre-amplification signal inversion:

The operational amplifier A3 first inverts the input pre-amplification signal, and then superimposes a negative amplitude DC level Vref, and finally completes the high-level and low-level conversion of the pre-amplification signal, and outputs the signal to the operational amplifier A2.

A2 and A5 complete the detection of the minimum peak value of the pre-amplification signal:

The pre-amplified signal is processed by A3 and sent to the non-inverting end of the operational amplifier A2. The principles of A2 and A5 are the same as those of A1 and A3 above, except that at this moment, since the pre-amplified signal has been processed by the operational amplifier A3, A2 and A5 complete the detection of the minimum value of the pre-amplified signal. At the same time, V12 is sent to A/D sampling 2 to obtain the corresponding voltage value and transfer it to the microcontroller.

A6 completes peak-to-peak detection:

The high level V11 and low level V12 of the pre-amplified signal after the aforementioned processing are respectively sent to the differential amplifier A6, and the ratio of Ry and Rx is adjusted to output (V12-V11)*(Ry/Rx). At the same time, it is sent to the A/D sampling 3 to obtain the corresponding voltage value and transmit it to the microcontroller.

The voltage values obtained by the above A/D sampling 1, 2, and 3 can determine the amplitude characteristics of the frequency signal output by the pre-amplifier signal module. These signals are fed back to the final-stage amplifying signal module through the single-chip microcomputer to complete synchronous phase detection. There is a very important technology here: in fact, according to the main schematic diagram, we only process the (V12-V11)*(Ry/Rx) information obtained above into the voltage-controlled voltage VX for correction and the traditional synchronous phase discrimination voltage. The control voltage VY is summed and sent to VCXO, we denote (V12-V11)=V _PP , (Ry/Rx)=K. Here K is an amplification gain, which depends on the ratio of the feedback gain Ry and Rx of the operational amplifier A6 in the signal feedback module. KV _PP directly determines the voltage control voltage for correction applied to the VCXO, so VX must be based on the specific VCXO. The voltage control slope and the traditional synchronous phase discrimination are set with the voltage control voltage VY magnitude. We generally take the patent implementation benefits obtained by the VX=VY/20 to VX=VY/10 magnitude above scheme:

According to the above principle, the voltage control voltage we apply to VCXO is:

VY+VX=VY+(V12-V11)*(Ry/Rx)=VY+KV _PP (6)

Here VY is the synchronous phase detection and voltage control obtained by the traditional PLL phase-locked loop; K is the feedback gain of the signal feedback circuit (it has been fixed in design); V _PP is the peak-to-peak value of the pre-amplified signal.

In the same time-domain frequency signal output system, as the frequency of the output signal increases, the peak-to-peak value of the signal will become smaller, as shown in the figure above. Therefore, when the frequency of the signal generated by the traditional PLL phase-locked loop circuit becomes smaller, the peak-to-peak value of the obtained pre-stage signal will become larger, and the voltage-controlled voltage VY+KV _PP obtained through the implementation of this patent will become larger (actually V _PP becomes larger), after acting on the VCXO, the frequency of the signal output by the VCXO will increase (because the VCXO with a positive voltage control slope is actually selected), which plays a role in compensation.

The present invention is not limited to the above-mentioned embodiments. The technical solutions of the above-mentioned embodiments of the present invention can be combined with each other to form new technical solutions. In addition, any technical solutions formed by using equivalent replacements fall within the protection scope of the present invention. .

Claims (4)

1. A time domain signal measuring device based on a PLL (phase locked Loop) is characterized in that: the device comprises a normalization module, a VCXO module, a frequency measuring instrument, a single chip microcomputer, a compensation module and a PLL loop unit;

the VCXO module is suitable for outputting a high-stability external reference source clock signal, and the external reference source clock signal is respectively sent to the normalization module and the frequency measuring instrument;

the normalization module is suitable for performing normalization processing on the frequency signal to be measured under the action of the external reference source clock to obtain a standard frequency signal for 1MHz verification and outputting the frequency signal to the frequency measuring instrument;

the frequency measuring instrument is suitable for measuring the time domain frequency of the signal frequency output by the normalization module according to the sampling time T =10 seconds under the action of an external reference source clock, and sending the measuring result to an external computer;

the compensation module is suitable for performing compensation control on the output error frequency of the VCXO module;

the single chip microcomputer is suitable for performing parameter control on the normalization module, the frequency measuring instrument and the compensation module;

the PLL loop unit is suitable for controlling the accuracy of the output frequency of the VCXO module through accurate signal frequency closed-loop, the PLL loop unit comprises a PLL loop module, a preceding stage amplification module, a signal feedback module and a final stage amplification module, and before synchronous phase discrimination processing, a frequency signal obtained by the PLL loop module is amplified by the preceding stage amplification module to obtain a radio frequency signal which is sent to the signal feedback module for processing;

the single chip microcomputer obtains relevant parameter information of the radio frequency signal through accessing the signal feedback module, the relevant parameter information comprises a maximum amplitude value, a minimum amplitude value and a peak-to-peak value of the signal, the parameter of the pre-stage amplification signal sent to the final-stage amplification module is repaired under the control of the single chip microcomputer, and the synchronous phase discrimination function of the traditional PLL is completed;

after the synchronous phase discrimination, the voltage-controlled voltage signal is obtained and then used for the VCXO module to complete the PLL phase-locked loop.

2. The PLL phase locked loop based time domain signal measuring apparatus of claim 1, wherein:

the normalization module comprises a first isolation amplifier, a first DDS module and a second DDS frequency division rate unit, a reference frequency signal f0 of the external reference source clock passes through the first isolation amplifier and then is sent to an external clock input end of the first DDS module to serve as a working external reference clock of the first DDS module, and an external communication port of the first DDS module is connected to the single chip microcomputer and used for receiving control word commands from the single chip microcomputer and carrying out bidirectional data transmission;

the second DDS frequency division unit comprises a second isolation amplifier, a second DDS module, a travel time counter, a latch, a third DDS module and a filtering module; the second isolation amplifier is respectively connected to the second DDS module and a third DDS module, the second DDS module, the first travel time counter and the first latch sequentially form signal connection, and the third DDS module is connected to the filtering module; and the external communication ports of the second DDS module and the third DDS module are respectively connected to the singlechip and used for receiving control word commands from the singlechip and carrying out bidirectional data transmission.

3. The PLL phase locked loop based time domain signal measuring apparatus of claim 2, wherein: the frequency measuring instrument comprises a third isolation amplifier, a second travel time counter, a second latch, a fourth isolation amplifier, a third travel time counter and a third latch; the third isolation amplifier, the second travel time counter and the second latch form signal connection in sequence; the fourth isolation amplifier, the third travel time counter and the third latch form signal connection in sequence; the third isolation amplifier and the fourth isolation amplifier are further respectively connected to the single chip microcomputer, controlled ends of the second travel time counter and the third travel time counter are respectively connected to a control end of the single chip microcomputer, and a reading end of the single chip microcomputer is further respectively connected to the second latch and the third latch.

4. The PLL phase locked loop based time domain signal measuring apparatus of claim 3, wherein: the compensation module comprises a first voltage reference module, a second voltage reference module, a D/A module and a temperature control module;

the first voltage reference module is suitable for providing a stable voltage output to the VCXO module;

the second voltage reference module is suitable for providing a stable voltage reference and sending the stable voltage reference to an external voltage reference end of the D/A module;

the temperature control module is arranged on the outer wall of the VCXO module and comprises a temperature control chip and a thermistor, and the temperature control module is suitable for detecting the working temperature of the VCXO module and sending the result to the single chip microcomputer;

the D/A module is suitable for outputting a direct current voltage value with variable size under the control of the single chip microcomputer and sending the direct current voltage value to the VCXO module.

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