CN107785248B - A kind of semiconductor device and its manufacturing method, electronic device - Google Patents
A kind of semiconductor device and its manufacturing method, electronic device Download PDFInfo
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- CN107785248B CN107785248B CN201610726727.7A CN201610726727A CN107785248B CN 107785248 B CN107785248 B CN 107785248B CN 201610726727 A CN201610726727 A CN 201610726727A CN 107785248 B CN107785248 B CN 107785248B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明提供一种半导体器件及其制造方法、电子装置，所述方法包括：提供半导体衬底，在半导体衬底上形成有伪栅极结构，在伪栅极结构的两侧形成有侧壁结构，在侧壁结构外侧的半导体衬底上形成有层间介电层；回蚀刻侧壁结构和伪栅极结构中的牺牲栅极材料层，形成沟槽；在侧壁结构的顶部靠近层间介电层的一侧形成牺牲侧墙；去除部分牺牲栅极材料层；回蚀刻未被牺牲侧墙遮蔽的侧壁结构；去除残余的牺牲栅极材料层，形成倒T形凹槽；在倒T形凹槽中形成金属栅极结构。根据本发明，形成的高k介电层/金属栅极结构呈倒T形，倒T形的台阶部分可以改善功函数设定金属层的沉积质量，从而提升高k介电层/金属栅极结构的电学性能。
The present invention provides a semiconductor device, a manufacturing method thereof, and an electronic device. The method includes: providing a semiconductor substrate, forming a dummy gate structure on the semiconductor substrate, and forming sidewall structures on both sides of the dummy gate structure , an interlayer dielectric layer is formed on the semiconductor substrate outside the sidewall structure; the sacrificial gate material layer in the sidewall structure and the dummy gate structure is etched back to form a trench; the top of the sidewall structure is close to the interlayer A sacrificial spacer is formed on one side of the dielectric layer; part of the sacrificial gate material layer is removed; the sidewall structure not covered by the sacrificial spacer is etched back; the remaining sacrificial gate material layer is removed to form an inverted T-shaped groove; A metal gate structure is formed in the T-shaped groove. According to the present invention, the formed high-k dielectric layer/metal gate structure has an inverted T shape, and the step portion of the inverted T shape can improve the deposition quality of the work function setting metal layer, thereby improving the high-k dielectric layer/metal gate. The electrical properties of the structure.
Description
Technical Field
The invention relates to a semiconductor manufacturing process, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
In the fabrication process of the next generation integrated circuit, a gate-last (gate-last) process is generally used for the fabrication of the gate of a Complementary Metal Oxide Semiconductor (CMOS). A typical gate last process includes: first, a dummy gate structure, which is generally composed of an interface layer, a high-k dielectric layer, a capping layer (capping layer), and a sacrificial gate electrode layer stacked from bottom to top, is formed on a semiconductor substrate; then, forming side wall structures on two sides of the dummy gate structure, and removing the sacrificial gate electrode layer in the dummy gate structure; then, a work function setting metal layer (work function metal layer), a barrier layer (barrier layer) and a wetting layer (wetting layer) are sequentially deposited in the left groove; finally, a metal gate (usually aluminum) is filled.
The transistor structure manufactured by the above process is generally called a high-k dielectric layer/metal gate transistor, and the quality of the work function setting metal layer in the high-k dielectric layer/metal gate transistor has a significant influence on the electrical properties of the high-k dielectric layer/metal gate transistor. In the gate-last process, the quality of the work function setting metal layer deposited in the trench left after removing the sacrificial gate electrode layer in the dummy gate structure is poor, thereby causing the electrical performance of the high-k dielectric layer/metal gate transistor to be unexpected.
Therefore, a method is needed to solve the above problems.
Disclosure of Invention
In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, forming a pseudo gate structure on the semiconductor substrate, forming side wall structures on two sides of the pseudo gate structure, and forming an interlayer dielectric layer on the semiconductor substrate outside the side wall structures; etching back the sacrificial gate material layer in the side wall structure and the dummy gate structure to form a groove; forming a sacrificial side wall on one side, close to the interlayer dielectric layer, of the top of the side wall structure; removing part of the sacrificial gate material layer; etching back the side wall structure which is not shielded by the sacrificial side wall; removing the residual sacrificial gate material layer to form an inverted T-shaped groove; and forming a metal gate structure in the inverted T-shaped groove.
In one example, the dummy gate structure includes a high-k dielectric layer and the sacrificial gate material layer stacked from bottom to top.
In one example, an interface layer is also formed between the high-k dielectric layer and the semiconductor substrate.
In one example, the etch back is performed using a dry etch process, and the trench has a depth of 5nm to 10 nm.
In one example, the step of forming the sacrificial sidewall spacer includes: and firstly forming an oxide layer on the bottom and the side wall of the groove, and then etching the oxide layer.
In one example, the oxide layer is formed using an atomic layer deposition process, the oxide layer having a thickness of 3nm to 5 nm.
In one example, the thickness of the remaining sacrificial gate material layer after removing the portion of the sacrificial gate material layer is 10nm-20 nm.
In one example, the etch back removes the sidewall structure to the same thickness as the removed portion of the sacrificial gate material layer.
In one example, the metal gate structure includes a workfunction setting metal layer and a metal gate material layer stacked from bottom to top.
In one embodiment, the present invention also provides a semiconductor device manufactured by the above method, wherein the top width of the metal gate structure in the semiconductor device is larger than the bottom width.
In one embodiment, the present invention also provides an electronic apparatus including the semiconductor device.
According to the invention, the formed high-k dielectric layer/metal gate structure is in an inverted T shape, and the step part of the inverted T shape can improve the deposition quality of the work function setting metal layer, thereby improving the electrical property of the high-k dielectric layer/metal gate structure.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 is a schematic cross-sectional view of a device obtained after implementation according to the prior art;
fig. 2A-2H are schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention;
FIG. 3 is a flowchart illustrating sequential steps performed by a method according to a first exemplary embodiment of the present invention;
fig. 4 is a schematic diagram of an electronic device according to a third exemplary embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
As shown in fig. 1, which is a schematic cross-sectional view of a device obtained after implementation according to the prior art. A high-k dielectric layer/metal gate structure is formed on the semiconductor substrate 100, and includes, as an example, a high-k dielectric layer 101a, a work function setting metal layer 101b, and a metal gate material layer 101c stacked from bottom to top. Sidewall structures 102 are formed on both sides of the high-k dielectric layer/metal gate structure, and an interlayer dielectric layer 103 is formed on the semiconductor substrate 100 outside the sidewall structures 102.
According to the existing gate-last process, after the sacrificial gate electrode layer in the dummy gate structure is removed, the side wall of the formed groove is nearly vertical, and the quality of the work function setting metal layer formed on the nearly vertical side wall through the deposition process is poor, thereby causing the electrical performance of the high-k dielectric layer/metal gate structure to be unexpected.
In order to solve the above problem, as shown in fig. 3, the present invention provides a method of manufacturing a semiconductor device, the method including:
in step 301, a semiconductor substrate is provided, a dummy gate structure is formed on the semiconductor substrate, sidewall structures are formed on two sides of the dummy gate structure, and an interlayer dielectric layer is formed on the semiconductor substrate outside the sidewall structures;
in step 302, etching back the sacrificial gate material layer in the sidewall structure and the dummy gate structure to form a trench;
in step 303, forming a sacrificial spacer on the top of the sidewall structure near one side of the interlayer dielectric layer;
in step 304, portions of the sacrificial gate material layer are removed;
in step 305, the sidewall structure not shielded by the sacrificial sidewall is etched back;
in step 306, removing the residual sacrificial gate material layer to form an inverted T-shaped groove;
in step 307, a metal gate structure is formed in the inverted T-shaped recess.
According to the manufacturing method of the semiconductor device, the formed high-k dielectric layer/metal gate structure is in the shape of the inverted T, and the deposition quality of the work function setting metal layer can be improved by the step part of the inverted T, so that the electrical performance of the high-k dielectric layer/metal gate structure is improved.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed. [ exemplary embodiment one ]
Referring to fig. 2A-2H, there are shown schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention.
First, as shown in fig. 2A, a semiconductor substrate 200 is provided, and the semiconductor substrate 200 may be formed of undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is monocrystalline silicon.
An isolation structure is formed in the semiconductor substrate 200, and the isolation structure is, for example, a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. Various well structures are also formed in the semiconductor substrate 200, and are omitted from the drawings for simplicity.
A dummy gate structure is formed on the semiconductor substrate 200, and includes, as an example, a high-k dielectric layer 201a and a sacrificial gate material layer 201b stacked from bottom to top. The material of high-k dielectric layer 201a may include hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc., with hafnium oxide, zirconium oxide, and aluminum oxide being particularly preferred. The material of the sacrificial gate material layer 201b may include polysilicon, monocrystalline silicon, etc. The material of the sacrificial gate material layer 201b includes polysilicon, silicon nitride or amorphous carbon, preferably polysilicon.
As another example, an interface layer is further formed between the high-k dielectric layer 201a and the semiconductor substrate 200, and a capping layer (capping layer) is further formed between the high-k dielectric layer 201a and the sacrificial gate material layer 201b, which are omitted for simplicity.
The interfacial layer can improve the adhesion between the high-k dielectric layer 201a and the semiconductor substrate 200The interfacial properties, the capping layer, may inhibit diffusion of the metal gate material (typically aluminum) in the subsequently formed metal gate structure into the high-k dielectric layer 201 a. The material of the interfacial layer may include silicon oxide (SiO)x). The material of the capping layer may include titanium nitride and tantalum nitride.
The above layers may be formed using any suitable process techniques known to those skilled in the art, such as forming an interface layer using a thermal oxidation process, forming the high-k dielectric layer 201a and the sacrificial gate material layer 201b using a chemical vapor deposition process, and forming a capping layer using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
For PMOS, an embedded sige layer is formed in the semiconductor substrate 200 outside the sidewall structures 202, which typically includes the following steps: forming a sigma-shaped groove in the semiconductor substrate 200 outside the side wall structure 202 by adopting a process of firstly performing dry etching and then performing wet etching; and forming an embedded germanium-silicon layer by adopting a selective epitaxial growth process so as to completely fill the sigma-shaped groove.
The embedded silicon germanium layer formed may be doped with boron and the selective epitaxial growth process may employ one of Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Ultra High Vacuum Chemical Vapor Deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE).
The process for forming the sigma-shaped groove comprises the following specific steps of: the semiconductor substrate 200 outside the sidewall structure 202 is etched longitudinally to form a trench by a dry etching process, in this embodiment, CF is used4HBr is used as main etching gas, the temperature is 40-60 ℃, the power is 200-; then adopting isotropic dry etching process to continuously etch the grooveAn oval groove is formed below the groove, namely a bowl-shaped groove is formed, and in the embodiment, Cl is adopted2And NF3As main etching gas, the temperature is 40-60 ℃, the power is 100-; and finally, expanding and etching the bowl-shaped groove by adopting a wet etching process to form the sigma-shaped groove, wherein the temperature of the wet etching is 30-60 ℃, the time is determined according to the expected size of the sigma-shaped groove and is generally 100-300s, and in the embodiment, a tetramethylammonium hydroxide (TMAH) solution is adopted as an etching solution of the wet etching.
A cap layer may also be formed atop the embedded sige layer to facilitate subsequent implementations of salicide formation on the embedded sige layer. In this embodiment, the cap layer is formed by an in-situ epitaxial growth process, that is, an epitaxial growth process used for forming the cap layer and an epitaxial growth process used for forming the embedded sige layer are performed in the same reaction chamber.
The self-aligned silicide forming process can be carried out before the dummy gate structure is removed, or can be carried out after the dummy gate structure is removed to form the metal gate structure.
An interlayer dielectric layer 203 completely covering the dummy gate structure is formed on the semiconductor substrate 200, and the material of the interlayer dielectric layer 203 is preferably an oxide formed by a plasma enhanced chemical vapor deposition process. Then, chemical mechanical polishing is performed to expose the top of the dummy gate structure.
Before the formation of the interlayer dielectric layer 203, a contact hole etch stop layer is formed on the semiconductor substrate 200 so as to completely cover the dummy gate structure, and the contact hole etch stop layer is preferably made of silicon nitride and is not shown for simplicity.
Next, as shown in fig. 2B, the sacrificial gate material layer 201B in the sidewall structure 202 and the dummy gate structure is etched back to form a trench. As an example, the etch back is performed using a dry etching process whose plasma has a high selectivity to the constituent materials of the sidewall structure 202 and the sacrificial gate material layer 201 b. The depth of the trench may be 5nm to 10 nm.
Next, as shown in fig. 2C, an oxide layer 204 is formed on the bottom and sidewalls of the trench. As an example, the oxide layer 204 is formed using an atomic layer deposition process, and the thickness of the oxide layer 204 may be 3nm to 5 nm.
Next, as shown in fig. 2D, the oxide layer 204 is etched to form a sacrificial spacer on the top of the sidewall structure 202 near the inter-layer dielectric 203. As an example, oxide layer 204 is etched using an anisotropic dry etch process.
Next, as shown in fig. 2E, a portion of the sacrificial gate material layer 201b is removed, and the thickness of the remaining sacrificial gate material layer 201b may be 10nm to 20 nm. As an example, the removal is performed by a dry etching process, and the process parameters include: the flow rate of the etching gas HBr is 20sccm to 500sccm, the pressure is 2mTorr to 40mTorr, and the power is 100W to 2000W, wherein mTorr represents milli-millimeter mercury column and sccm represents cubic centimeter per minute.
Next, as shown in fig. 2F, the sidewall structure 202 not shielded by the sacrificial sidewall spacers is etched back. As an example, the etch-back is performed using a dry etching process, the plasma of which has a high selectivity to the constituent material of the sidewall structure 202. The thickness of the sidewall structure 202 removed by the etch-back is the same as the thickness of the portion of the sacrificial gate material layer 201b previously removed.
Next, as shown in fig. 2G, the remaining sacrificial gate material layer 201b is removed to form an inverted T-shaped groove. As an example, the removal is performed by a dry etching process, and the process parameters include: the flow rate of the etching gas HBr is 20sccm to 500sccm, the pressure is 2mTorr to 40mTorr, and the power is 100W to 2000W, wherein mTorr represents milli-millimeter mercury column and sccm represents cubic centimeter per minute.
Next, as shown in fig. 2H, a metal gate structure is formed in the inverted T-shaped groove. Then, a chemical mechanical polishing is performed until the top of the sidewall structure 202 is exposed.
As an example, the metal gate structure includes a work function setting metal layer 201c and a metal gate material layer 201d stacked from bottom to top. The work function setting metal layer 201c includes one or more layers of metal or metal compound, and in the case of NMOS, the constituent material of the work function setting metal layer 201c is a metal material suitable for NMOS, and includes titanium, tantalum, aluminum, zirconium, hafnium, and an alloy thereof, and further includes a carbide, a nitride, and the like of the above-mentioned metal element, and in the case of PMOS, the constituent material of the work function setting metal layer 201c is a metal material suitable for PMOS, and includes titanium, ruthenium, palladium, platinum, tungsten, and an alloy thereof, and further includes a carbide, a nitride, and the like of the above-mentioned metal element. The constituent material of the metal gate material layer 201d includes aluminum.
As an example, before the metal gate material layer 201d is formed, a step of sequentially forming a barrier layer and a wetting layer on the work function setting metal layer 201c is further included, the material of the barrier layer includes tantalum nitride or titanium nitride, the material of the wetting layer includes titanium or a titanium-aluminum alloy, and the illustration is omitted for simplicity.
To this end, the process steps performed by the method according to the first exemplary embodiment of the present invention are completed. It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above steps, but also other steps as needed before, during or after the above steps, which are included in the scope of the method for manufacturing the semiconductor device.
Compared with the prior art, according to the method provided by the invention, the formed high-k dielectric layer/metal gate structure is in an inverted T shape, and the deposition quality of the work function setting metal layer 201c can be improved by the step part of the inverted T shape, so that the electrical property of the high-k dielectric layer/metal gate structure is improved.
[ second exemplary embodiment ]
First, a semiconductor device obtained by the process steps implemented by the method according to the first exemplary embodiment of the present invention is provided, as shown in fig. 2H, including: the semiconductor substrate 200 has an isolation structure formed in the semiconductor substrate 200, and various well structures (wells), for example, a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure.
A high-k dielectric layer/metal gate structure having an inverted T shape formed on the semiconductor substrate 200, the gate structure including, as an example, a high-k dielectric layer 201a, a work function setting metal layer 201c, and a metal gate material layer 201d stacked from bottom to top.
And a sidewall structure 202 formed on both sides of the gate structure and abutting against the gate structure, wherein the sidewall structure 202 is made of oxide, nitride or a combination of the two.
The source/drain regions formed in the semiconductor substrate 200 outside the sidewall structures 202 are omitted from the illustration for simplicity.
An interlayer dielectric layer 203 is formed on the semiconductor substrate 200 outside the sidewall structures 202. Before the formation of the interlayer dielectric layer 203, a contact hole etching stop layer is formed, and is omitted in the drawing for simplicity.
Then, the fabrication of the whole semiconductor device is completed through the following processes, including: forming another interlayer dielectric layer on the interlayer dielectric layer 203 to cover the high-k dielectric layer/metal gate structure; forming a contact hole in the interlayer dielectric layer to expose the top of the metal gate material layer 201d and the top of the source/drain region; filling metal (usually tungsten) in the contact hole to form a contact plug; forming a plurality of interconnection metal layers, which are usually completed by adopting a dual damascene process; and forming a metal bonding pad for wire bonding in the subsequent device packaging process.
[ exemplary embodiment III ]
The present invention also provides an electronic device including the semiconductor device according to the second exemplary embodiment of the present invention. The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, a PSP, or any intermediate product including the semiconductor device.
Wherein figure 4 shows an example of a handset. The exterior of the cellular phone 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.
The internal components of the electronic device include the semiconductor device described in the second exemplary embodiment, and thus have better performance.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
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| CN110854023B (en) * | 2019-11-21 | 2021-02-02 | 海光信息技术股份有限公司 | Method for removing pseudo gate |
| CN113053739B (en) * | 2019-12-27 | 2024-08-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113539829B (en) * | 2020-04-20 | 2025-04-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming the same |
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