CN107861050B - A method of On-wafer measurement is carried out using vector network analyzer - Google Patents

Abstract

The invention discloses a kind of methods for carrying out On-wafer measurement using vector network analyzer comprising following steps: s1. carries out full dual-port SOLT or TRL calibration in the port that vector network analyzer test cable is connected with fixture first；S2. vector network analyzer test cable is connected with two fixtures, carries out the calibration that frequency time domain combines in clip end；S3. it is measured in clip end connection measured piece.The present invention dexterously introduces two fixtures in vector network analyzer end face, and cumbersome chip testing is converted, simple and convenient.In addition, the present invention is based on vector network analyzers to carry out chip testing, by completely analyzing, modeling, the error introduced in chip testing has been fully considered, and removed by algorithm, therefore measuring accuracy is high.

Description

A method of on-chip testing using a vector network analyzer

technical field

The invention relates to a method for on-chip testing by using a vector network analyzer.

Background technique

Microwave integrated circuits work in the microwave and millimeter wave bands, and are integrated on a substrate by microwave passive active components, transmission lines and interconnection lines. With the development of microwave integrated circuit technology and manufacturing process, integrated circuits are more integrated and the substrate area is smaller. As a general-purpose microwave measuring instrument, it is more difficult to use the vector network analyzer to perform on-chip testing of microwave integrated circuits, that is, directly perform S-parameter testing of microwave integrated circuits on a large wafer. Because microwave integrated circuits and vector network analyzers cannot be directly connected, the measurement needs to introduce fixtures or probe stations, or packages, or use bonding wires, etc.

At present, the mainstream on-chip test method is to use the fixture de-embedding function of the vector network analyzer. This technique utilizes fixtures. Two test fixtures are used, which can be connected to the vector network analyzer at one end and to the chip at the other end. In this way, the fixture manufacturer provides the finished fixture and supporting characteristic data.

Fixture de-embedding technology uses a set of characterized fixtures. As the number of fixtures used increases, the wear of the fixture will widen the gap between the fixture characteristic data and the actual characteristics, resulting in inaccurate testing.

Secondly, the user designs and manufactures calibration parts suitable for use on the fixture side, and performs traditional two-port calibration directly on the fixture side, including SOLT, TRL calibration, etc. Since the open-circuit part in the SOLT calibration kit is not easy to realize, and requires that all standard characteristics must be known and precisely defined, users often make TRL calibration kits, because they can use the characteristic impedance of the transmission line as an impedance reference, and there are certain differences in use. Advantage. However, because the same base material as the microwave integrated circuit must be selected, and for new users, it is difficult to design by themselves, and the low-end needs to be used in conjunction with SOLT or LRM.

Contents of the invention

The object of the present invention is to propose a method for on-chip testing using a vector network analyzer, which fully considers the errors introduced in chip testing and removes them through an algorithm to improve testing accuracy.

In order to achieve the above object, the present invention adopts the following technical solutions:

A method for performing on-chip testing using a vector network analyzer, comprising the steps of:

s1. Vector network analyzer full two-port calibration

Firstly, full two-port SOLT or TRL calibration is performed at the port where the test cable of the vector network analyzer is connected to the fixture to remove the systematic error in the test cable of the vector network analyzer;

s2. The test cable of the vector network analyzer is connected to two fixtures, and the frequency-time domain combined calibration is performed at the fixture end

Set the two fixtures connected to the test cable of the vector network analyzer as fixture one and fixture two; among them, the error items of fixture one are L ₀₀ , L ₀₁ , L ₁₀ , L ₁₁ ; the error items of fixture two are N ₀₀ , N ₀₁ , N ₁₀ , N ₁₁ ;

Connect calibration pieces at both ends of fixture one and fixture two to obtain the above error term;

s3. Connect the DUT at the fixture end for measurement

Connect the test piece at the ends of the two fixtures, set the true characteristics of the test piece as: _{S 11A} , _{S 21A} , _{S 12A} , _{S 22A} ; Get the characteristics of the two fixtures to get the real characteristics of the tested part, namely:

Wherein, ΔS=S _12M S _21M -S _11M S _22M , ΔL=L ₀₁ L ₁₀ -L ₀₀ L ₁₁ , ΔN=N ₀₁ N ₁₀ -N ₀₀ N ₁₁ .

Preferably, in the step s2, the steps of obtaining the error terms of fixture 1 and fixture 2 are as follows:

1) Fixture 1 and fixture 2 are air-connected for measurement

Separate fixture 1 and fixture 2 by a distance, measure S ₁₁ and S ₂₂ respectively, and observe the curve in the time domain. It can be seen that there are two peaks in the whole curve, which are the reflection characteristics of fixture 1 and fixture 2 respectively. Each measurement uses the time-domain gate card to get the first wave peak, and converts it to the frequency domain to obtain the measurement data respectively, which are L ₀₀ and N ₀₀ ;

2) Connect the short circuit between the two fixtures, and calculate the reflection coefficient T _s of the short circuit;

The measurement data T _M1 , T _M2 and the single-port error formula obtained after the reflection measurement after connecting the short-circuit bar to the fixture 1 and the fixture 2 respectively are obtained:

3) Fixtures directly docked

Connect fixture 1 and fixture 2 directly to form a straight-through connection, and test four S parameters respectively. At this time, the straight-through length is 0, that is, the transmission coefficient is 1;

According to the direct data flow diagram, S _11M , S _21M , S _12M , and S _22M can be obtained by measuring the reflection and transmission in the forward and reverse directions respectively, and:

Since then, all eight error terms have been obtained for both fixtures.

Preferably, the thickness and material of the short circuit are known; if the material of the short circuit is known, its dielectric constant, magnetic permeability, and propagation velocity can be obtained, and the reflection coefficient T _s of the short circuit can be obtained.

Preferably, the material and thickness of the short circuit cannot be determined. Select a straight line, then connect the short circuit, test S ₁₁ or S ₂₂ , find the second closest peak in the time domain, and then use the time domain gate to intercept and convert it into a frequency domain, the measured value is T _s .

Compared with prior art, the present invention has following advantage:

(1) The present invention cleverly introduces two fixtures on the end face of the vector network analyzer, cleverly transforms the complicated chip test, and is simple and convenient to operate. (2) The present invention carries out the chip test based on the vector network analyzer, through complete analysis and modeling, fully considers the error introduced in the chip test, and removes it through the algorithm, so the test accuracy is high.

Description of drawings

Fig. 1 is the signal flow diagram after the two ends of the fixture are connected to the calibration piece in the present invention;

Fig. 2 is the signal flow diagram of short-circuit chip calibration part in the present invention;

Fig. 3 is a schematic diagram of the signal of the short-circuit calibrator after the port of the vector network analyzer in the present invention.

Detailed ways

The basic idea of the present invention is: the vector network analyzer obtains the systematic error of the vector network analyzer after full dual-port calibration, on this basis, two fixtures are introduced to extend the calibration plane to the fixture end, and the The calibration algorithm performs secondary calibration on the entire test system, and finally obtains the real characteristics of the chip under test.

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

The whole calibration process needs to establish two calibration planes: one is the end face of the vector network analyzer. After the traditional full two-port SOLT or TRL calibration of the vector network analyzer, the measurement end face is determined on the calibration end face. The second is to calibrate the end face of the fixture. The test end face is translated from the end face of the vector network analyzer to the end face of the fixture by using the frequency-time domain combined calibration method. Therefore, the characteristic data obtained by placing the tested chip in the test end face is the real characteristic of the tested chip after removing the system error of the vector network analyzer, the characteristics of the introduced fixture, and the connection error between the fixture and the vector network analyzer.

Therefore, the entire calibration test process consists of three parts:

s1. Vector network analyzer full two-port calibration

Firstly, a full two-port SOLT or TRL calibration is performed at the port where the test cable of the vector network analyzer is connected to the fixture, and the systematic error of the vector network analyzer in the test cable is removed. In subsequent calibrations, the VNA will show that the calibration is turned on, and the acquired measurement data has been corrected based on SOLT or TRL calibration.

s2. The test cable of the vector network analyzer is connected to two fixtures, and the frequency-time domain combined calibration is performed at the fixture end

Set the two fixtures connected to the test cable of the vector network analyzer as fixture one and fixture two; among them, the error items of fixture one are L ₀₀ , L ₀₁ , L ₁₀ , L ₁₁ ; the error items of fixture two are N ₀₀ , N ₀₁ , N ₁₀ , N ₁₁ .

The signal flow diagram of the entire connection device is shown in Figure 1. The main purpose of calibration is to obtain the four errors corresponding to the two fixtures shown in Figure 1. The present invention has carried out the following several calibrations to obtain respectively:

1) Fixture 1 and fixture 2 are air-connected for measurement

Separate fixture 1 and fixture 2 by a certain distance, measure S ₁₁ and S ₂₂ respectively, and observe the curve in the time domain. It can be seen that there are two peaks in the whole curve, which are the reflection characteristics of fixture 1 and fixture 2 respectively. Each measurement uses the time-domain gate card to get the first wave peak, and converts it to the frequency domain to obtain the measurement data respectively, which are L ₀₀ and N ₀₀ ;

2) A short circuit is connected between the two fixtures, and the reflection coefficient T _s of the short circuit is calculated.

A short circuit of known thickness and material can be used for this measurement. As shown in Fig. 2, if the material of the short circuit is known, its dielectric constant, magnetic permeability, propagation velocity, etc. can be obtained, and the reflection coefficient T _s of the short circuit can be obtained through calculation.

The formula used in calculating the reflection coefficient T _s of the short circuit is as follows:

Among them, T represents time, Γ represents the reflection coefficient, and _γ0 represents the vacuum gyromagnetic ratio;

γ _γ represents the gyromagnetic ratio of the medium, μ ₀ represents the air permeability, ω represents the frequency, c represents the light propagation speed, L represents the thickness of the short circuit, μ _γ represents the magnetic permeability of the short circuit, and ε _γ represents the dielectric constant of the short circuit.

If the material and thickness of the short circuit cannot be determined, but there is a suitable probe station or other suitable type of fixture, you can choose a straight line, then connect the short circuit, test S ₁₁ or S ₂₂ , and find the closest distance in the time domain The second peak is intercepted by the time domain gate and transformed into the frequency domain, and the measured value is T _s .

The sample diagram is shown in Figure 3, intercept the second peak pointed by the time-domain gate cursor, and perform time-frequency domain conversion.

Using the measurement data T _M1 , T _M2 and the single-port error formula obtained after the reflection measurement after the short-circuit bar is connected to the fixture 1 and the fixture 2 respectively, the formula (1) and formula (2) can be obtained, as follows:

3) Fixtures directly docked

Connect fixture 1 and fixture 2 directly to form a straight-through connection, and test four S parameters respectively. At this time, the straight-through length is 0, that is, the transmission coefficient is 1;

According to the direct data flow diagram, S _11M , S _21M , S _12M , and S _22M can be obtained by measuring the reflection and transmission in the forward and reverse directions respectively, and:

Since then, all eight error terms have been obtained for both fixtures.

s3. Connect the DUT at the fixture end for measurement

Connect the test piece at the ends of the two fixtures, and set the true characteristics of the test piece as: S _11A , S _21A , S _12A , S _22A .

Assuming that the measured data T matrix of the tested part is T _M , the actual measured characteristic data T matrix is T _x ; the real characteristic T matrices of fixture 1 and fixture 2 are T _L and T _N respectively, then: [ _TM ]= [T _L ][T _x ][T _N ].

After simplification, we can get:

After simplification and calculation, the real characteristics of the tested part are:

Wherein, ΔS=S _12M S _21M -S _11M S _22M , ΔL=L ₀₁ L ₁₀ -L ₀₀ L ₁₁ , ΔN=N ₀₁ N ₁₀ -N ₀₀ N ₁₁ .

The invention utilizes the time-domain characteristics of the vector network analyzer to analyze the specific input and output responses of the special calibration parts introduced by secondary calibration, and obtains the real characteristics of the tested chip by using the calibration algorithm through the characteristic analysis of the special calibration parts.

Although the present invention uses a fixture or probe station, it is not necessary to characterize the fixture. In addition, a special calibration piece is also used, but the calibration piece is simple to manufacture, and the calibration technology involved in this method has unique advantages in waveguide calibration.

Of course, the above descriptions are only preferred embodiments of the present invention, and the present invention is not limited to the above-mentioned embodiments. It should be noted that all equivalent substitutions made by any person skilled in the art under the teaching of this specification , obvious deformation forms, all fall within the essential scope of this specification, and should be protected by the present invention.

Claims (3)

1. a kind of method for carrying out On-wafer measurement using vector network analyzer, which comprises the steps of:

S1. the full dual-port calibration of vector network analyzer

Full dual-port SOLT or TRL calibration is carried out in the port that vector network analyzer test cable is connected with fixture first, is moved In addition to systematic error of the vector network analyzer in test cable；

S2. vector network analyzer test cable is connected with two fixtures, carries out the calibration that frequency time domain combines in clip end

Setting two fixtures being connected with vector network analyzer test cable is respectively fixture one and fixture two；Wherein, fixture One error term is L₀₀、L₀₁、L₁₀、L₁₁；The error term of fixture two is N₀₀、N₀₁、N₁₀、N₁₁；

Calibration component is connected to obtain above-mentioned error term with the both ends of fixture two in fixture one；

The step of obtaining fixture one and two error term of fixture is as follows:

1) fixture one and two sky of fixture connect and measure

Fixture one and fixture two are separated a distance, measure S respectively₁₁And S₂₂, observing curve under time domain can see, entirely Curve measures all there are two wave crests, the respectively reflection characteristic of the reflection characteristic of fixture one and fixture two with time domain door twice Block first wave crest out, and is transformed under frequency domain that respectively obtain measurement data be L₀₀And N₀₀；

2) short-circuit piece is connected between two fixtures, calculates the reflection coefficient T of short-circuit piece_s；

The measurement data T for carrying out obtaining after reflection measurement respectively after fixture one and fixture two is connected to using short-circuit piece_M1、T_M2And list Port error formula obtains:

3) fixture directly docks

Fixture one and fixture two are directly docking together, straight-through connection type is formed, carries out the test of four S parameters respectively, At this point, straight-through length is 0, i.e., transmission coefficient is 1；

According to straight-through data flow diagram, forward and reverse reflection of survey respectively and transmission obtain S_11M、S_21M、S_12M、S_22M, and:

Since then, eight error terms of two fixtures all acquire；

S3. it is measured in clip end connection measured piece

Measured piece is connected in the end of two fixtures, sets the genuine property of measured piece are as follows: S_11A、S_21A、S_12A、S_22A；Pass through by Measured data S_11M、S_21M、S_12M、S_22MWith the characteristic of two fixtures of acquisition, the genuine property of measured piece is obtained, it may be assumed that

Wherein, Δ S=S_12MS_21M-S_11MS_22M, Δ L=L₀₁L₁₀-L₀₀L₁₁, Δ N=N₀₁N₁₀-N₀₀N₁₁。

2. a kind of method for carrying out On-wafer measurement using vector network analyzer according to claim 1, which is characterized in that Short-circuit piece thickness and material obtain short-circuit piece reflection coefficient T it is known that obtain its dielectric constant, magnetic conductivity, spread speed_s。

3. a kind of method for carrying out On-wafer measurement using vector network analyzer according to claim 1, which is characterized in that Short-circuit piece material and thickness can not determine, select one section of direct-through line, connect short-circuit piece later, test S₁₁Or S₂₂, looked under time domain Second peak value nearest to distance recycles the interception of time domain door, is converted into frequency domain, measured value is T_s。