CN107861757B - Arithmetic device and related product - Google Patents

Abstract

The present invention provides an arithmetic device for executing an operation according to an extended instruction, the arithmetic device including: a memory, an arithmetic unit and a control unit; the extended instruction includes: an opcode and an operation field, a memory to store a vector; the control unit is used for acquiring an extended instruction, analyzing the extended instruction to obtain a vector operation instruction and a second operation instruction, determining the calculation sequence of the vector operation instruction and the second operation instruction according to the vector operation instruction and the second operation instruction, and reading an input vector corresponding to the input vector address from a memory; and the operation unit is used for executing the vector operation instruction and the second operation instruction to the input vector according to the calculation sequence to obtain the result of the extended instruction. The technical scheme provided by the invention has the advantages of low power consumption and low calculation overhead.

Description

Computing devices and related products

technical field

The present invention relates to the field of communication technologies, in particular to a computing device and related products.

Background technique

In modern general-purpose and special-purpose processors, computational instructions (eg, vector instructions) are increasingly introduced to perform operations. Vector instructions are instructions that cause the processor to perform vector or matrix operations, such as addition and subtraction of vectors, inner product of vectors, matrix multiplication, matrix convolution, and the like. At least one input to a vector instruction is a vector or matrix or the result of the operation is a vector or matrix. The vector instruction can perform parallel computation by calling the vector processing unit inside the processor to improve the operation speed. In the existing vector instructions, the vectors or matrices in the operands or results are generally of fixed size. For example, the vector instructions in the vector extension structure Neon in the ARM processor can process a 32-bit floating-point vector with a length of 4 at a time. 16-bit fixed-point vector of length 8.

Therefore, the existing vector operation instructions cannot implement variable-scale vector or matrix operations, and the current vector operation instructions can only implement one operation. For example, a vector instruction can only implement one operation in multiplication and addition, and a vector Instructions cannot implement more than two kinds of operations, so the existing vector operations have high computational overhead and high energy consumption.

SUMMARY OF THE INVENTION

The embodiments of the present invention provide an operation device and related products, which can realize the purpose of realizing multiple operations with a single operation instruction, reduce operation overhead, and reduce the power consumption of modules.

In a first aspect, an embodiment of the present invention provides a method for implementing an extended instruction, and the method includes the following steps:

An arithmetic device for performing an operation according to an extended instruction, the arithmetic device comprising: a memory, an arithmetic unit and a control unit;

The extended instruction includes: an operation code and an operation field, the operation code includes: an identifier for identifying the vector calculation instruction; the operation field includes: the input vector address of the vector calculation instruction, the output vector address of the vector calculation instruction, the second calculation instruction The identifier of the instruction, the input data of the second calculation instruction, the data type, and the data length N;

memory, for storing vectors;

The control unit is used to obtain the extended instruction, parse the extended instruction to obtain the vector operation instruction and the second operation instruction, determine the calculation order of the vector operation instruction and the second operation instruction according to the vector operation instruction and the second operation instruction, and obtain the vector operation instruction and the second operation instruction from the memory. reading the input vector corresponding to the input vector address;

an operation unit, configured to execute the vector operation instruction and the second operation instruction on the input vector in the calculation order to obtain the result of the extended instruction.

Optionally, the computing device further includes:

A register unit for storing extended instructions to be executed.

Optionally, the control unit includes:

an instruction fetch module, used for acquiring extended instructions from the register unit;

a decoding module for decoding the acquired extended instruction to obtain a vector operation instruction, a second operation instruction and a calculation sequence;

The instruction queue is used for storing the decoded vector operation instructions and the second operation instructions in the calculation order.

Optionally, the computing device further includes:

The dependency relationship processing unit is used to determine whether the extended instruction and the previous extended instruction access the same vector before the control unit acquires the extended instruction, and if so, wait for the execution of the previous extended instruction to complete, and then convert the vector of the current extended instruction The operation instruction and the second operation instruction are provided to the operation unit; otherwise, the vector operation instruction of the vector operation instruction and the second operation instruction are provided to the operation unit.

Optionally, when the current extended instruction accesses the same vector as the previous extended instruction, the dependency processing unit stores the current extended instruction in a storage queue, and after the execution of the previous extended instruction is completed, stores the current extended instruction in the storage queue. of this current extended instruction is provided to the control unit.

Optionally, the memory is a cache memory.

Optionally, the operation unit includes a vector addition circuit, a vector multiplication circuit, a size comparison circuit, a nonlinear operation circuit, a vector scalar multiplication circuit and an activation circuit.

Optionally, the operation unit is a multi-pipeline structure, wherein the vector multiplication circuit and the vector scalar multiplication circuit are in the first pipeline stage, the size comparison component and the vector addition circuit are in the second pipeline stage, and the nonlinear operation is performed. The components and the activation circuit are in a third pipeline stage, wherein the output data of the first pipeline stage is the input data of the second pipeline stage, and the output data of the second pipeline stage is the input data of the third pipeline stage.

Optionally, the control unit is specifically configured to identify whether the output data of the vector operation instruction is the same as the input data of the second calculation instruction, if they are the same, determine that the calculation order is positive-order calculation; identify the vector operation Whether the input data of the instruction and the output data of the second calculation instruction are the same, if they are the same, determine that the calculation sequence is reverse order calculation; identify whether the input data of the vector operation instruction is related to the output data of the second calculation instruction, if not, determine the calculation sequence for unordered computation.

A second aspect provides a chip that integrates the computing device provided in the first aspect.

In a third aspect, an electronic device is provided, and the electronic device includes the chip provided in the second aspect.

It can be seen that, through the extended instruction provided by the embodiment of the present invention, the function of the instruction is strengthened, and the original multiple instructions are replaced by one instruction. This reduces the number of instructions required for complex vector and matrix operations, and simplifies the use of vector instructions; compared with multiple instructions, there is no need to store intermediate results, which not only saves storage space, but also avoids additional read and write overhead.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are some embodiments of the present invention.

FIG. 1A is a schematic structural diagram of a computing device provided by the present invention.

FIG. 1 is a flow chart of a method for implementing an extended instruction according to the present invention.

FIG. 2 is a schematic structural diagram of an arithmetic unit provided by the present invention.

FIG. 3A is a schematic structural diagram of a control unit provided by the present invention.

FIG. 3 is a schematic structural diagram of a neural network processor board according to an embodiment of the present application;

4 is a schematic structural diagram of a neural network chip packaging structure provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a neural network chip provided by an embodiment of the present application;

6 is a schematic diagram of a neural network chip packaging structure provided by an embodiment of the present application;

FIG. 6A is a schematic diagram of another neural network chip packaging structure provided by an embodiment of the present application.

Parts in dashed lines in the drawings represent optional features.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The terms "first", "second", "third" and "fourth" in the description and claims of the present invention and the accompanying drawings are used to distinguish different objects, rather than to describe a specific order. . Furthermore, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices. "/" in the text can mean "or".

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

The following uses the CPU as an example to illustrate the method of vector dot product. For vector dot product, the dot product of vector and vector is calculated. Function description: Given a vector x, y and a scalar r of length n, perform the following vector-vector operations , and its calculation formula is as follows:

For the vector dot product, the instruction of the vector dot product can be "DOT TYPE,N,X,Y,R"; DOT represents the vector dot product instruction, and type represents the operable data type (such as real number or complex number), N represents the length of the vector, X represents the first address of the vector X, y represents the first address of the vector Y, and R is a scalar. As mentioned in the above vector dot product, its vector dot product instruction can only implement one type of operation, that is, the operation of vector dot product, and cannot implement multiple operations, such as the inability to implement both vector dot product and discrete data reading. an operation.

As shown in FIG. 1A, the operation device includes: a memory 111, a register 112 (optional), an operation unit 114, a control unit 115, and a dependency relationship processing unit 116 (optional);

Wherein, the operation unit 114 is shown in FIG. 2 : including: a conversion circuit (optional), a vector addition circuit, a vector multiplication circuit, a size comparison circuit, a nonlinear operation circuit, a vector scalar multiplication circuit and an activation circuit.

The operation unit has a multi-pipeline structure, specifically as shown in FIG. 2 , the first pipeline stage includes but is not limited to: a vector multiplication circuit, a vector scalar multiplication circuit, and the like.

The second pipeline stage includes, but is not limited to, size comparison calculators (eg, comparators), vector addition circuits, and the like.

The third pipeline stage includes, but is not limited to, nonlinear operation components (specifically, activation circuits or transcendental function calculation circuits, etc.) and the like.

If the arithmetic unit includes a conversion circuit, the conversion circuit may be in the first pipeline stage, or may be in the third pipeline stage.

The output data of the first pipeline stage is the input data of the second pipeline stage, and the output data of the second pipeline stage is the input data of the third pipeline stage. The input of the first pipeline stage may be input data (eg, an input vector), and the output of the third pipeline stage may be the calculation result.

The present invention also provides an extended instruction, the operation code and an operation field, the operation code includes: an identifier (for example, ROT) for identifying the first operation instruction; the operation field includes: the input data address of the first operation instruction, the first operation field The output data address of a calculation instruction, the identifier of the second calculation instruction, the input data of the second calculation instruction, the data type, and the data length N.

Optionally, the above-mentioned extended instruction may further include: a third calculation instruction and input data of the third calculation instruction.

It should be noted that, the above calculation instruction may be a vector operation instruction or a matrix instruction, and the specific embodiment of the present invention does not limit the specific expression form of the above calculation instruction.

The above-mentioned computing device can be used to execute extended instructions, which can specifically include:

memory, for storing vectors;

The control unit is used to obtain the extended instruction, parse the extended instruction to obtain the vector operation instruction and the second operation instruction, determine the calculation order of the vector operation instruction and the second operation instruction according to the vector operation instruction and the second operation instruction, and obtain the vector operation instruction and the second operation instruction from the memory. reading the input vector corresponding to the input vector address;

an operation unit, configured to execute the vector operation instruction and the second operation instruction on the input vector in the calculation order to obtain the result of the extended instruction.

A register unit for storing extended instructions to be executed.

Optionally, the above-mentioned control unit 115, as shown in FIG. 3A, may include:

an instruction fetch module, used for acquiring extended instructions from the register unit;

a decoding module for decoding the acquired extended instruction to obtain a vector operation instruction, a second operation instruction and a calculation sequence;

The instruction queue is used for storing the decoded vector operation instructions and the second operation instructions in the calculation order.

The dependency relationship processing unit 116 is used to determine whether the extended instruction and the previous extended instruction access the same vector before the control unit acquires the extended instruction, and if so, wait for the execution of the previous extended instruction to complete, and then convert the current extended instruction to the same vector. The vector operation instruction and the second operation instruction are provided to the operation unit; otherwise, the vector operation instruction and the second operation instruction of the vector operation instruction are provided to the operation unit.

The dependency relationship processing unit 116 is further configured to store the current extended instruction in a storage queue when the current extended instruction accesses the same vector as the previous extended instruction, and store the current extended instruction in a storage queue after the execution of the previous extended instruction is completed. The current extended instruction is provided to the control unit.

Optionally, the above-mentioned memory is a high-speed temporary storage memory.

Referring to FIG. 1, FIG. 1 provides a method for implementing an extended instruction. The extended instruction in the method may include: an operation code and an operation domain, and the first operation instruction may be a vector operation instruction, such as AXPY. The operation code includes: an identifier (for example, AXPY) that identifies the first operation instruction; the operation field includes: the input data address of the first operation instruction, the output data address of the first operation instruction, the identifier of the second operation instruction, the first operation instruction. 2. The input data, data type and data length N of the calculation instruction (which is a value set by the user, and the present invention does not limit the specific form of N); the method is executed by a computing device or a computing chip, and the computing device is shown in FIG. 1A . Show. The method, as shown in Figure 1, includes the following steps:

Step S101, the computing device obtains an extended instruction, and parses the extended instruction to obtain a first calculation instruction and a second calculation instruction;

Step S102 , the computing device determines a calculation sequence according to the first calculation instruction and the second calculation instruction, and executes the first calculation instruction and the second calculation instruction in the calculation sequence to obtain the result of the extended instruction.

The technical solution provided by the present invention provides an implementation method of an extended instruction, so that the computing device can perform the calculation of two calculation instructions on the extended instruction, so that a single extended instruction can realize two types of calculations, which reduces the calculation overhead and reduces the power consumption.

Optionally, the above calculation sequence may specifically include: any one of out-of-order calculation, forward-order calculation, or reverse-order calculation. During out-of-order calculation, that is, the first calculation instruction and the second calculation instruction do not have a corresponding order requirement, the normal calculation In sequential calculation, the first calculation instruction is executed first, and then the second calculation instruction is executed. In reverse order calculation, the second calculation instruction is executed first, and then the first calculation instruction is executed.

The specific implementation of the above-mentioned computing device determining the calculation sequence according to the first calculation instruction and the second calculation command may be: It is a forward-order calculation, otherwise, the computing device identifies whether the input data of the first computing instruction and the output data of the second computing instruction are the same. Whether the output data of the calculation instruction is related, if not, the calculation sequence is determined as unordered calculation.

Specifically, an actual example is used to illustrate, such as F=A*B+C, the first calculation instruction is a matrix multiplication instruction, and the second calculation instruction is a matrix addition instruction. Since the matrix addition instruction of the second calculation instruction needs to be applied to the first calculation instruction The result of a calculation instruction is output data, so it is determined that the calculation sequence is positive sequence calculation. For another example, F=OP(A)*OP(B), where the first operation instruction is a matrix multiplication instruction, and the second operation instruction is a transformation, such as transposition or conjugation, since the first operation instruction uses the second operation instruction The output of the operation instruction, so its operation order is calculated in reverse order. If there is no corresponding association, that is, the output data of the first calculation instruction is not the same as the input data of the second calculation instruction, and the input data of the first calculation instruction and the input data of the second calculation instruction are also different, it is determined not to be associated.

The extension of the vector instruction provided by the present invention strengthens the function of the instruction, and replaces the original multiple instructions with one instruction. This reduces the number of instructions required for complex vector and matrix operations, and simplifies the use of vector instructions; compared with multiple instructions, there is no need to store intermediate results, which not only saves storage space, but also avoids additional read and write overhead.

If the first calculation instruction is a vector instruction, for the input vector or matrix in the vector instruction, the instruction adds the function of scaling it, that is, adding an operand representing the scaling factor in the operation field, and when reading the vector, first adjust the scaling factor according to the scaling factor. It scales (ie the second calculation instruction is a scaling instruction). If there are multiple input vector or matrix multiplication operations in the vector instruction, the scaling coefficients corresponding to these input vectors or matrices can be combined into one.

If the first calculation instruction is a vector instruction, for the input matrix in the vector instruction, the instruction adds a function of transposing it (that is, the second calculation instruction is a transposition instruction). Add an operand indicating whether to transpose it in the instruction, indicating whether to transpose the matrix before the operation.

If the first calculation instruction is a vector instruction, for the output vector or matrix in the vector instruction, the instruction adds the function of adding the original output vector or matrix (ie, the second calculation instruction is an addition instruction). Adding a coefficient indicating scaling of the original output vector or matrix to the instruction (that is, adding a third calculation instruction, which can be a scaling instruction), the instruction indicates that after the vector or matrix operation is performed, the result is scaled with the The original outputs are added as the new output.

If the first calculation instruction is a vector instruction, for the input vector in the vector instruction, the instruction adds the function of reading according to a fixed step size. An operand representing the read step size of the input vector is added to the instruction (that is, the second calculation instruction is to read the vector at a fixed step size), which represents the difference between the addresses of two adjacent elements in the vector.

If the first calculation instruction is a vector instruction, for the result vector in the vector instruction, the instruction adds the function of writing the result according to a fixed step size (that is, the second calculation instruction writes a vector according to a fixed step size). An operand representing the read step size of the result vector is added to the instruction, representing the difference between the addresses of two adjacent elements in the vector. If a vector is both an input and a result, the same stride is used for both the input and the result.

If the first calculation instruction is a vector instruction, for the input matrix in the vector instruction, the instruction adds the function of reading row or column vectors according to a fixed step size (that is, the second calculation instruction is to read multiple vectors according to a fixed step size). An operand representing the matrix read step size is added to the instruction, representing the difference between the first addresses of the matrix row or column vectors.

If the first calculation instruction is a vector instruction, for the result matrix in the vector instruction, the instruction adds the function of reading row or column vectors according to a fixed step size (that is, the second calculation instruction is to write multiple vectors according to a fixed step size). An operand representing the matrix read step size is added to the instruction, representing the difference between the first addresses of the matrix row or column vectors. If a matrix is both an input and a result matrix, the same stride is used as the input and as the result.

The actual structures of the above-mentioned extended instructions are described below with some actual extended instructions.

vector multiplication

Calculate the product of a vector and a scalar and add the result to another vector

Function description:

Given a vector x, y and a scalar a, perform the following vector-vector operations

Y:=a*x+y

The command format is shown in Table 1-1:

Table 1-1:

The length of the vector in the instruction format shown in Table 1-1 is variable, which can reduce the number of instructions and simplify the use of instructions.

Supports the vector format stored at certain intervals, avoiding the execution overhead of transforming the vector format and the space occupied by the storage of intermediate results.

Vector dot product

Calculates the dot product of a vector and a vector

Functional description: Given a vector x, y and a scalar r of length n, perform the following vector-vector operations

The command format is shown in Table 1-2:

Table 1-2:

The length of the vector in the instruction format shown in Table 1-2 is variable, which can reduce the number of instructions and simplify the use of instructions.

Supports the vector format stored at certain intervals, avoiding the execution overhead of transforming the vector format and the space occupied by the storage of intermediate results.

vector norm

Calculate the Euclidean norm of a vector

Function description:

This instruction performs the following vector reduction operations:

The command format is shown in Table 1-3:

Table 1-3

The length of the vector in the instruction format shown in Table 1-3 is variable, which can reduce the number of instructions and simplify the use of instructions. Supports the vector format stored at certain intervals, avoiding the execution overhead of transforming the vector format and the space occupied by the storage of intermediate results.

vector sum

Calculate the sum of all elements of a vector

Function description:

This instruction performs the following vector reduction operations:

The command format is shown in Table 1-4:

Table 1-4:

The length of the vector in the instruction format shown in Table 1-4 is variable, which can reduce the number of instructions and simplify the use of instructions.

Supports the vector format stored at certain intervals, avoiding the execution overhead of transforming the vector format and the space occupied by the storage of intermediate results.

vector maximum

Calculate the position of the largest element among all elements of a vector

Function description:

For a vector x of length n, this instruction writes the position of the largest element in the vector into a scalar i

The command format is shown in Table 1-5:

Table 1-5:

The length of the vector in the instruction format shown in Table 1-5 is variable, which can reduce the number of instructions and simplify the use of instructions. Supports the vector format stored at certain intervals, avoiding the execution overhead of transforming the vector format and the space occupied by the storage of intermediate results.

vector minimum

Calculate the position of the smallest element among all elements of a vector

Function description:

For a vector x of length n, this instruction writes the position of the smallest element in the vector into a scalar i

The command format is shown in Table 1-6:

Table 1-6

The length of the vector in the instruction format shown in Table 1-6 is variable, which can reduce the number of instructions and simplify the use of instructions. Supports the vector format stored at certain intervals, avoiding the execution overhead of transforming the vector format and the space occupied by the storage of intermediate results.

Outer product of vectors

Calculate the tensor product (outer product) of two vectors

Function description:

This instruction performs the following matrix-vector operations

A:=α*x*y ^T +A

The command format is shown in Table 1-7:

Table 1-7

The scalar alpha in the instruction format shown in Table 1-7 scales the result matrix, which increases the flexibility of the instruction and avoids the extra overhead of scaling with the scaling instruction. The variable size of vectors and matrices can reduce the number of instructions and simplify the use of instructions. Can handle matrices of different storage formats (row-major and column-major order), avoiding the overhead of transforming the matrix. Supports the vector format stored at certain intervals, avoiding the execution overhead of transforming the vector format and the space occupation of storing intermediate results.

For the computing device shown in FIG. 1 , the specific structure of the extended instruction is calculated when the extended instruction is implemented, that is, the combination of multiple computing instructions is implemented through the execution of one extended instruction. The extended instruction is not split into multiple computation instructions when extending the instruction.

Please refer to FIG. 3 , which is a schematic structural diagram of a neural network processor board according to an embodiment of the present application. As shown in FIG. 3 , the above-mentioned neural network processor board 10 includes a neural network chip package structure 11 , a first electrical and non-electrical connection device 12 and a first substrate 13 .

This application does not limit the specific structure of the neural network chip packaging structure 11. Optionally, as shown in FIG. 4, the neural network chip packaging structure 11 includes: a neural network chip 111, a second electrical and non-electrical connection device 112, a first Two substrates 113 .

The specific form of the neural network chip 111 involved in this application is not limited. The above-mentioned neural network chip 111 includes but is not limited to a neural network chip that integrates a neural network processor. The above-mentioned chip can be made of silicon materials, germanium materials, quantum materials or molecular materials. materials etc. According to the actual situation (for example: harsh environment) and different application requirements, the above neural network chip can be packaged, so that most of the neural network chip is wrapped, and the pins on the neural network chip are passed through gold wires. The other conductors are connected to the outside of the package structure for circuit connection with the outer layers.

The present application does not limit the specific structure of the neural network chip 111 . Optionally, please refer to FIG. 1A , which is a schematic structural diagram of a computing device in a neural network chip provided by an embodiment of the present application. As shown in FIG. 1A , the above computing device includes: a memory 111 , a register 112 (optional), an arithmetic unit 114 , a control unit 115 and a dependency relationship processing unit 116 (optional). For the specific functions or structures of the above units, reference may be made to the embodiment shown in FIG. 1A .

The application does not limit the types of the first substrate 13 and the second substrate 113, which may be printed circuit boards (PCBs) or printed wiring boards (PWBs), and may also be other circuit boards. The material for making the PCB is also not limited.

The second substrate 113 involved in the present application is used to carry the above-mentioned neural network chip 111 , and the neural network chip package structure 11 is obtained by connecting the above-mentioned neural network chip 111 and the second substrate 113 through the second electrical and non-electrical connection device 112 . , which is used to protect the neural network chip 111 and facilitate further packaging of the neural network chip packaging structure 11 and the first substrate 13 .

The packaging method and the structure corresponding to the packaging method of the above-mentioned specific second electrical and non-electrical connection device 112 are not limited, and an appropriate packaging method can be selected according to the actual situation and different application requirements and can be simply improved, for example: flip chip Ball Grid Array Package (Flip Chip Ball Grid Array Package, FCBGAP), Low-profile Quad Flat Package (LQFP), Quad Flat Package with Heat Sink (HQFP), No Lead Quad Flat Package (Quad Flat Non-lead Package, QFN) or Small Pitch Quad Flat Package (Fine-pitch Ball Grid Package, FBGA) and other packaging methods.

Flip Chip is suitable for situations where the area after the package is high or is sensitive to the inductance of the wire and the transmission time of the signal. In addition, a wire bonding (Wire Bonding) packaging method can be used to reduce the cost and improve the flexibility of the packaging structure.

Ball Grid Array (Ball Grid Array) can provide more pins, and the average lead length of the pins is short, which has the function of high-speed signal transmission. Among them, the package can be packaged with Pin Grid Array (PGA) , zero insertion force (Zero Insertion Force, ZIF), single edge contact connection (Single Edge Contact Connection, SECC), contact array (Land Grid Array, LGA), etc. instead.

Optionally, the neural network chip 111 and the second substrate 113 are packaged in a flip chip ball grid array (Flip Chip Ball Grid Array) packaging method. Refer to FIG. 6 for a schematic diagram of a specific neural network chip packaging structure. As shown in FIG. 6 , the above-mentioned neural network chip package structure includes: a neural network chip 21 , pads 22 , solder balls 23 , a second substrate 24 , connection points 25 and pins 26 on the second substrate 24 .

Wherein, the pad 22 is connected to the neural network chip 21, and solder balls 23 are formed by welding between the pad 22 and the connection point 25 on the second substrate 24, and the neural network chip 21 and the second substrate 24 are connected. Packaging of the neural network chip 21 .

The pin 26 is used to connect with the external circuit of the package structure (for example, the first substrate 13 on the neural network processor board 10 ), which can realize the transmission of external data and internal data, and is convenient for the neural network chip 21 or the neural network chip 21 The corresponding neural network processor processes the data. The type and quantity of pins are not limited in this application, and different pin forms can be selected according to different packaging technologies, and they are arranged in accordance with certain rules.

Optionally, the above-mentioned neural network chip package structure further includes insulating fillers, which are placed in the gaps between the pads 22 , the solder balls 23 and the connection points 25 , to prevent interference between the solder balls and the solder balls.

Wherein, the material of the insulating filler may be silicon nitride, silicon oxide or silicon oxynitride; the interference includes electromagnetic interference, inductive interference, and the like.

Optionally, the above-mentioned neural network chip packaging structure further includes a heat dissipation device for dissipating heat during operation of the neural network chip 21 . Wherein, the heat dissipation device may be a metal sheet, a heat sink or a heat sink with good thermal conductivity, such as a fan.

For example, as shown in FIG. 6A , the neural network chip package structure 11 includes: a neural network chip 21 , pads 22 , solder balls 23 , a second substrate 24 , connection points 25 on the second substrate 24 , pins 26 , Insulation filler 27, thermal paste 28 and metal shell heat sink 29. Among them, the heat dissipation paste 28 and the metal shell heat dissipation fins 29 are used to dissipate the heat of the neural network chip 21 during operation.

Optionally, the above-mentioned neural network chip package structure 11 further includes a reinforcing structure, which is connected to the pads 22 and embedded in the solder balls 23 to enhance the connection strength between the solder balls 23 and the pads 22 .

Wherein, the reinforcing structure may be a metal wire structure or a columnar structure, which is not limited herein.

This application also does not limit the specific form of the first electrical and non-electrical device 12, and can refer to the description of the second electrical and non-electrical device 112, that is, the neural network chip package structure 11 is packaged by welding, or a connection can be used. The way of connecting the second substrate 113 and the first substrate 13 by wire connection or plugging is convenient for subsequent replacement of the first substrate 13 or the neural network chip package structure 11 .

Optionally, the first substrate 13 includes an interface and the like for a memory unit used to expand the storage capacity, for example: a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM), a double-rate synchronous dynamic random access memory (Double Date Rate SDRAM, DDR), etc., the processing power of the neural network processor is improved by expanding the memory.

The first substrate 13 may further include a Peripheral Component Interconnect-Express (PCI-E or PCIe) interface, a Small Form-factor Pluggable (SFP) interface, an Ethernet interface, and a controller. A local area network bus (Controller Area Network, CAN) interface, etc., is used for data transmission between the package structure and the external circuit, which can improve the operation speed and the convenience of operation.

The neural network processor is packaged as a neural network chip 111, the neural network chip 111 is packaged as a neural network chip package structure 11, and the neural network chip package structure 11 is packaged as a neural network processor board 10, through the interface ( socket or ferrule) for data interaction with an external circuit (eg, computer motherboard), that is, directly using the neural network processor board 10 to realize the function of the neural network processor and protect the neural network chip 111 . In addition, other modules can be added to the neural network processor board 10, which improves the application scope and operation efficiency of the neural network processor.

In one embodiment, the present disclosure discloses an electronic device including the above-mentioned neural network processor board 10 or neural network chip package structure 11 .

Electronic devices include data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cameras, video cameras, projectors, watches, headphones, mobile storage , wearable devices, vehicles, home appliances, and/or medical devices.

The vehicles include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lamps, gas stoves, and range hoods; the medical equipment includes nuclear magnetic resonance instruments, B-ultrasound and/or electrocardiograph.

It should be noted that, for the sake of simple description, the foregoing method embodiments are all expressed as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence. As in accordance with the present invention, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present invention.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components may be combined or Integration into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

The embodiments of the present invention have been introduced in detail above, and specific examples are used to illustrate the principles and implementations of the present invention. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present invention; at the same time, for Persons of ordinary skill in the art, according to the idea of the present invention, will have changes in the specific embodiments and application scope. To sum up, the contents of this specification should not be construed as limiting the present invention.

Claims (11)

1. An arithmetic device for performing an operation in accordance with an extended instruction, the arithmetic device comprising: a memory, an arithmetic unit and a control unit;

the extended instruction includes: an opcode and an operation domain, the opcode comprising: identifying an identification of a vector computation instruction; the operation domain includes: an input vector address of the vector calculation instruction, an output vector address of the vector calculation instruction, an identifier of the second calculation instruction, input data of the second calculation instruction, a data type and a data length N;

a memory for storing vectors;

the control unit is used for acquiring an extended instruction, analyzing the extended instruction to obtain a vector operation instruction and a second operation instruction, determining the calculation sequence of the vector operation instruction and the second operation instruction according to the vector operation instruction and the second operation instruction, and reading an input vector corresponding to the input vector address from a memory;

the control unit is specifically configured to identify whether output data of the vector operation instruction is the same as input data of the second calculation instruction, and if so, determine that the calculation order is a positive order calculation; identifying whether the input data of the vector operation instruction is the same as the output data of the second calculation instruction, and if so, determining that the calculation sequence is reverse calculation; identifying whether input data of the vector operation instruction is associated with output data of the second calculation instruction or not, and if not, determining that the calculation sequence is unordered calculation;

the arithmetic unit is used for executing the vector arithmetic instruction and a second arithmetic instruction to the input vector according to the calculation sequence to obtain the result of the extended instruction, wherein the calculation sequence is positive order calculation, the vector arithmetic instruction is executed firstly, and then the second arithmetic instruction is executed; the calculation sequence is reverse order calculation, the second operation instruction is executed firstly, and then the vector operation instruction is executed; the calculation order is out-of-order calculation, and the vector operation instruction and the second operation instruction do not have the corresponding order requirement.

2. The arithmetic device of claim 1, further comprising:

and the register unit is used for storing the extended instruction to be executed.

3. The arithmetic device according to claim 2, wherein the control unit includes:

the instruction fetching module is used for acquiring an extended instruction from the register unit;

the decoding module is used for decoding the obtained extended instruction to obtain a vector operation instruction, a second operation instruction and a calculation sequence;

and the instruction queue is used for storing the decoded vector operation instruction and the second operation instruction according to the calculation sequence.

4. The arithmetic device of claim 3, further comprising:

the dependency relationship processing unit is used for judging whether the expansion instruction and a previous expansion instruction access the same vector or not before the control unit acquires the expansion instruction, and if so, after the previous expansion instruction is completely executed, providing the vector operation instruction and a second operation instruction of the current expansion instruction to the operation unit; otherwise, the vector operation instruction and the second operation instruction of the vector operation instruction are provided to the operation unit.

5. The computing device of claim 4, wherein the dependency processing unit is configured to store a current extended instruction in a store queue when the current extended instruction and a previous extended instruction access the same vector, and to provide the current extended instruction in the store queue to the control unit after the previous extended instruction is executed.

6. The computing device of any of claims 1-5, wherein the memory is a scratch pad memory.

7. The arithmetic device of claim 1, wherein the arithmetic unit comprises a vector addition circuit, a vector multiplication circuit, a size comparison circuit, a non-linear arithmetic circuit, and a vector scalar multiplication circuit.

8. The arithmetic device according to claim 7, wherein the arithmetic unit has a multi-pipeline structure, wherein the vector multiplication circuit and the vector scalar multiplication circuit are in a first pipeline stage, the magnitude comparison unit and the vector addition circuit are in a second pipeline stage, and the non-linear operation unit is in a third pipeline stage, wherein output data of the first pipeline stage is input data of the second pipeline stage, and output data of the second pipeline stage is input data of the third pipeline stage.

9. The arithmetic device according to claim 8, wherein the arithmetic unit further comprises: the conversion circuit is positioned at the first flowing water level and the third flowing water level, or the conversion circuit is positioned at the first flowing water level, or the conversion circuit is positioned at the third flowing water level.

10. A chip incorporating an arithmetic device as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that the electronic device comprises a chip according to claim 10.

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