CN107863964A - Accurately control the fully differential charge transfer circuit of common mode charge amount - Google Patents

Abstract

The present invention relates to a kind of fully differential charge transfer circuit for accurately controlling common mode charge amount, and it includes the first numerical model analysis control type charge transfer circuit and the second numerical model analysis control type charge transfer circuit；Also include the first common mode charge detection circuit, common mode feed forward circuit, the second common mode charge detection circuit, detection process circuit, common mode charge adjustment circuit, M positions adjustment register and controller calibration；The present invention can be in the charge-domain pipelined analog-digital converter of automatic detection common mode charge error, and the common mode charge error is accurately compensated, to overcome limitation of the common mode charge error to the dynamic property of existing charge-domain pipelined analog-digital converter, the conversion performance of existing charge-domain pipelined analog-digital converter is further improved.

Description

Fully Differential Charge Transfer Circuit with Precise Control of Common-Mode Charge Amount

technical field

The present invention relates to a signal transmission circuit of an analog-to-digital converter, in particular to a fully differential charge transmission circuit that can precisely control the amount of common-mode charge, specifically for the precisely controllable charge-domain pipelined analog-to-digital converter The invention relates to a fully differential charge transmission circuit of common-mode charge, which belongs to the technical field of microelectronics.

Background technique

With the continuous development of digital signal processing technology, the digitization and integration of electronic systems is an inevitable trend. However, the signals in reality are mostly continuously changing analog quantities, which need to be converted into digital signals by analog-to-digital conversion before they can be input into digital systems for processing and control. Therefore, analog-to-digital converters (ADC) are important in future digital system design. Indispensable component. In applications such as broadband communications, digital high-definition television, and radar, systems require analog-to-digital converters with both very high sampling rates and resolutions. Portable terminal products in these application fields require not only high sampling rate and high resolution for analog-to-digital converters, but also minimum power consumption.

At present, the analog-to-digital converter structure capable of simultaneously realizing high sampling rate and high resolution is a pipeline-structured analog-to-digital converter. The pipeline structure is a multi-stage conversion structure. Each stage uses an analog-to-digital converter with a low-precision basic structure. The input signal is processed by one stage, and finally the result of each stage is combined to generate a high-precision output. The basic idea is to evenly distribute the conversion precision required by the whole to each level, and combine the conversion results of each level to get the final conversion result. Since the pipeline structure ADC can achieve the best compromise in speed, power consumption and chip area, it can still maintain high speed and low power consumption when realizing higher precision analog-to-digital conversion.

The existing relatively mature way to realize the analog-to-digital converter of the pipeline structure is the pipeline structure based on the switched capacitor technology. Operational amplifiers with high gain and wide bandwidth must be used in the sampling and holding circuit and each sub-level circuit in the pipeline analog-to-digital converter based on this technology. The use of these high-gain and wide-bandwidth operational amplifiers limits the speed and accuracy of switched-capacitor pipelined ADCs, and becomes the main bottleneck limiting the performance improvement of this type of ADC. The consumption level increases linearly with the increase of speed. The most straightforward way to reduce the power consumption of a pipelined A/D converter based on switched capacitor circuits is to reduce or eliminate the use of high-gain and ultra-wide bandwidth operational amplifiers.

The charge-domain pipelined ADC is an analog-to-digital converter that does not use an operational amplifier with high gain and ultra-wide bandwidth. This structure of the analog-to-digital converter has the characteristics of low power consumption and can achieve high speed and high precision at the same time. The charge-domain pipelined analog-to-digital converter uses charge-domain signal processing techniques. In the circuit, the signal is expressed in the form of a charge packet, and the size of the charge packet represents a semaphore of different sizes, and the storage, transmission, addition/subtraction, comparison, etc. of the charge packets of different sizes between different storage nodes realize the signal processing function. The analog-to-digital conversion function can be realized by using a periodic clock to drive and control the signal processing of charge packets of different sizes between different storage nodes. However, a prominent issue is that its performance is susceptible to performance degradation due to common-mode charge errors.

Among the many factors affecting the common-mode charge, the influence of the charge transfer circuit block between sub-circuits is crucial. For the realization of high-efficiency charge transfer circuits, the existing technical implementation methods typically include the following documents: The patent document of US2007/0279507A1 proposes a basic enhanced charge transfer circuit, which can greatly improve the charge transfer technology. The document with the publication number CN102394650A proposes a pseudo-differential auxiliary charge transfer circuit, which can suppress the influence of PVT fluctuations on common-mode charge errors caused by charge transfer. The document with the publication number CN101882929A proposes a digital-analog hybrid compensation technology for input common-mode errors to solve the impact of common-mode errors caused by input signals on the performance of charge-domain ADCs. Therefore, in order to further improve the accuracy of the charge-domain pipeline ADC, it is meaningful to design a differential charge transfer circuit that can precisely control the amount of common-mode charge.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art and provide a fully differential charge transmission circuit that can precisely control the amount of common-mode charge, which can improve the performance of the charge-domain pipeline analog-to-digital converter, and is safe and reliable.

According to the technical solution provided by the present invention, the fully differential charge transfer circuit that can precisely control the amount of common-mode charge includes a first digital-analog hybrid control type charge transfer circuit and a second digital-analog hybrid control type charge transfer circuit; A common-mode charge detection circuit, a common-mode feedforward circuit, a second common-mode charge detection circuit, a detection processing circuit, a common-mode charge adjustment circuit, an M-bit adjustment register, and a calibration controller;

The differential input terminal Qin _,p and the differential input terminal Qin _,n are respectively connected to the differential charge input terminal of the first common-mode charge detection circuit, and the output terminal of the first common-mode charge detection circuit is connected to the input of the common-mode feedforward circuit end; the output terminal Vf of the common-mode feedforward circuit is simultaneously connected to the first common-mode adjustment signal input terminal FF of the first digital-analog hybrid control type charge transfer circuit, and the first common-mode input terminal FF of the second digital-analog hybrid control type charge transfer circuit. The adjustment signal input terminal FF; the output terminal of the first digital-analog hybrid control type charge transmission circuit and the output terminal of the second digital-analog hybrid control type charge transmission circuit are respectively connected to the differential charge input terminal of the second common-mode charge detection circuit. The output end of the two common-mode charge detection circuits is connected to the input end of the detection processing circuit; the output end of the detection processing circuit is connected to the detection signal input end of the calibration controller; the M-bit compensation code output end of the calibration controller is connected to the M-bit adjustment The signal input end of the register and the signal output end of the M-bit adjustment register are connected to the control signal input end of the common-mode charge adjustment circuit; the control signal output end of the common-mode charge adjustment circuit is simultaneously connected to the first digital-analog hybrid control type charge transmission circuit The second common-mode adjustment signal input terminal FB of the second digital-analog hybrid control type charge transfer circuit and the second common-mode adjustment signal input terminal FB of the second digital-analog hybrid control type charge transfer circuit.

Calibration controller can control to enter into calibration mode or normal working mode;

First enter the calibration mode, the calibration controller connects the differential input terminals corresponding to the first analog-digital hybrid control type charge transfer circuit and the second digital-analog hybrid control type charge transfer circuit to the input reference voltage; then the first common-mode charge detection is turned on circuit and the second common-mode charge detection circuit, the output of the second common-mode charge detection circuit is sequentially statistically processed by the detection processing circuit, and then the calibration controller performs calculations to assign values to the M-bit adjustment register; the common-mode charge adjustment circuit according to The M-bit digital code of the M-bit adjustment register generates a compensation voltage Vadj, and under the action of the compensation voltage Vadj, the corresponding output common of the first digital-analog hybrid control type charge transmission circuit and the second digital-analog hybrid control type charge transmission circuit is controlled. Finally, the calibration controller turns on the common-mode feed-forward circuit, and makes the differential charge input terminal of the first digital-analog hybrid control type charge transmission circuit and the differential charge input terminal of the second digital-analog hybrid control type charge transmission circuit re- Connect the differential input terminal Q _in,N and the differential input terminal Q _in,P ;

After completing the above, the calibration control enters the normal transmission mode; after entering the normal transmission mode, the calibration controller and the detection processing circuit enter the sleep mode.

The second common-mode charge detection circuit includes a first charge detector, a second charge detector, a third charge detector and a fourth charge detector;

The first charge detector and the fourth charge detector are respectively connected to the differential charge output terminal Q _out,p and the full differential charge output terminal Q _outKn ; the output terminal of the first charge detector is connected to one end of the sampling switch S1, and the output terminal of the sampling switch S1 The other end is connected with one end of the capacitor C1 and one end of the sampling switch S2, the other end of the sampling switch S2 is connected with the output end of the second charge detector, the input end of the second charge _detector is connected with the reference signal Rp , and the third charge The input end of the detector is connected with the reference signal Rn, the output end of the third charge detector is connected with one end of the sampling switch S3, the other end of the sampling switch S3 is connected with one end of the capacitor C2 and one end of the sampling switch S4, and the sampling switch S4 The other end is connected to the output end of the fourth charge detector, the other end of the capacitor C1 is connected to one end of the sampling switch S5 and the positive input end of the full differential amplifier, and the other end of the capacitor C2 is connected to the sampling switch S6 and the negative input end of the full differential amplifier The other end of the sampling switch S6 is connected to the other end of the sampling switch S5, and the other end of the sampling switch S5 and the other end of the sampling switch S6 are connected to the voltage VSet;

The first charge detector, the fourth charge detector, the sampling switch S1, the sampling switch S4 are connected to the second clock Φ ₂ , the second charge detector, the third charge detector, the sampling switch S2, the sampling switch S3, the sampling switch S5 and The sampling switch S6 is connected to the first clock Φ ₁ , and the first clock Φ ₁ and the second clock Φ ₂ do not overlap with each other.

The common mode feedforward circuit includes a PMOS current mirror circuit, a differential input pair, and a current mirror bias circuit;

The PMOS current mirror circuit includes a PMOS transistor M3 and a PMOS transistor M4, the gate terminal of the PMOS transistor M3 is connected to the drain terminal of the PMOS transistor M3 and the gate terminal of the PMOS transistor M4, and the source terminals of the PMOS transistor M3 and the PMOS transistor M4 are connected to each other. connected to the power supply; the gate terminal of the PMOS transistor M3 and the drain terminal of the PMOS transistor M3 are connected to the drain terminal of the reset MOS transistor Ms1, and the drain terminal of the PMOS transistor M4 is connected to the drain terminal of the reset MOS transistor Ms2; the drain terminal of the reset MOS transistor Ms1 The gate terminal and the gate terminal of the reset MOS transistor Ms2 are connected to the _second clock Φ2;

The differential input pair includes a MOS transistor M1 and a MOS transistor M2; the drain terminal of the MOS transistor M1 is connected to the source terminal of the reset MOS transistor Ms1; the drain terminal of the MOS transistor M2 is connected to the source terminal of the reset MOS transistor Ms2; The source terminal of MOS transistor M1 is connected to the drain terminal of MOS transistor M5 through source resistor R1, and the source terminal of MOS transistor M2 is connected to the drain terminal of MOS transistor M5 through source resistor R2; the gate terminal of MOS transistor M5 is connected to the drain terminal of MOS transistor M5. The gate terminal of M8 is connected to the drain terminal of MOS transistor M8, the source terminal of MOS transistor M5 is connected to the drain terminal of MOS transistor M6, the drain terminal of MOS transistor M6 is grounded, the source terminal of MOS transistor M8 is grounded, and the gate terminal of MOS transistor M6 It is connected to the gate terminal of the MOS transistor M7 and the drain terminal of the MOS transistor M7, and the source terminal of the MOS transistor M7 and the source terminal of the MOS transistor M8 are both grounded. The drain terminal of the MOS transistor M8 is connected to the bias current Ib1, and the drain terminal of the MOS transistor M7 is connected to the bias current Ib2;

The gate terminal of the MOS transistor M1 receives the first output error signal CM, the gate terminal of the MOS transistor M2 is connected to the second output error signal CMn, and the drain terminal of the MOS transistor M2 is connected to the source terminal of the reset MOS transistor Ms2.

The advantages of the present invention: can automatically detect the common-mode charge error in the charge-domain pipeline analog-to-digital converter, and accurately compensate the common-mode charge error, so as to overcome the common-mode charge error’s impact on the existing charge-domain pipeline analog-to-digital converter The limitation of dynamic performance further improves the conversion performance of existing charge-domain pipelined ADCs.

Description of drawings

FIG. 1 is a structural principle diagram of a fully differential charge transmission circuit capable of precisely controlling the amount of common-mode charges in the present invention.

FIG. 2 is a schematic diagram of an implementation of a digital-analog hybrid control type charge transfer circuit in the present invention.

FIG. 3 is a schematic circuit diagram of the common-mode charge detection circuit of the present invention.

Fig. 4 is a schematic circuit diagram of the common mode feedforward circuit of the present invention.

FIG. 5 is a schematic circuit diagram of the common mode adjustment circuit of the present invention.

Fig. 6 is a schematic circuit diagram of the detection processing circuit in the present invention.

Description of reference numerals: 1-first common-mode charge detection circuit, 2-common-mode feedforward circuit, 3-first digital-analog hybrid control type charge transmission circuit, 4-second digital-analog hybrid control type charge transmission circuit, 5 -second common-mode charge detection circuit, 6-common-mode charge adjustment circuit, 7-detection processing circuit, 8-M-bit adjustment register, 9-calibration controller, 10-basic enhanced charge transfer circuit, 11-mirror control circuit , 12-first charge detector, 13-second charge detector, 14-third charge detector, 15-fourth charge detector, 16-fully differential operational amplifier, 17-output buffer operational amplifier, 18-DAC Module, 19-K:1 selector, 20-first 8:1 selector, 21-16-bit counter with pulse swallowing, 22-16:1 selector, 23-signal comparison circuit, 24-readout control device, 25-window signal generator, 26-scan sequence generator, 27-swallow control circuit, 28-reset signal generation circuit, 29-first 8:1 selector, 30-16-bit counter and 31-error amplifier.

Detailed ways

The present invention will be further described below in conjunction with specific drawings and embodiments.

The error of the common-mode charge of the pipeline sub-level circuits of the charge domain ADC at all levels comes from three aspects: 1), the common-mode charge caused by the turn-off point voltage of the BCT (digital-analog hybrid control type charge transfer circuit) at all levels with the change of PVT Charge error; 2), common-mode charge error caused by input common-mode level fluctuations; 3), capacitance mismatch in each pipeline sub-level circuit and common-mode charge error fluctuation caused by reference voltage changes with PVT.

As shown in Figure 1, the present invention includes a first common-mode charge detection circuit 1, a common-mode feedforward circuit 2, a first digital-analog hybrid control type charge transfer circuit 3, a second digital-analog hybrid control type charge transfer circuit 4, a second Two common-mode charge detection circuit 5 , common-mode charge adjustment circuit 6 , detection processing circuit 7 , M-bit adjustment register 8 and calibration controller 9 , wherein M-bit is a positive integer greater than 1.

Specifically, the differential input terminal Qin _,p and the differential input terminal Qin _,n are respectively connected to the differential charge input terminal of the first common-mode charge detection circuit 1, and the output terminal of the first common-mode charge detection circuit 1 is connected to the common-mode The input terminal of the feedforward circuit 2; the output terminal Vf of the common mode feedforward circuit 2 is simultaneously connected to the first common mode adjustment signal input terminal FF of the first digital-analog hybrid control type charge transfer circuit 3, the second digital-analog hybrid control type The first common-mode adjustment signal input terminal FF of the charge transfer circuit 4; the output end of the first digital-analog hybrid control type charge transfer circuit 3, and the output end of the second digital-analog hybrid control type charge transfer circuit 4 are connected to the second common mode respectively. The differential charge input end of the analog charge detection circuit 5, the output end of the second common mode charge detection circuit 5 is connected to the input end of the detection processing circuit 7; the output end of the detection processing circuit 7 is connected to the detection signal input end of the calibration controller 9 The M bit compensation code output end of the calibration controller 9 is connected to the signal input end of the M bit adjustment register 8, and the signal output end of the M bit adjustment register 8 is connected to the control signal input end of the common mode charge adjustment circuit 6; the common mode charge The control signal output terminal of the adjustment circuit 6 is simultaneously connected to the second common mode adjustment signal input terminal FB of the first digital-analog hybrid control type charge transfer circuit 3, and the second common mode adjustment signal of the second digital-analog hybrid control type charge transfer circuit 4. Signal input terminal FB.

In the embodiment of the present invention, the above-mentioned circuit has two working modes, that is, a calibration mode and a normal transmission mode. When starting to work, first enter the calibration mode, the calibration controller 9 connects the differential input terminals corresponding to the first analog-digital hybrid control type charge transfer circuit 3 and the second digital-analog hybrid control type charge transfer circuit 4 to the input reference voltage; Then the first common-mode charge detection circuit 1 and the second common-mode charge detection circuit 5 are turned on, the output of the second common-mode charge detection circuit 5 is sequentially statistically processed by the detection processing circuit 7, and then calculated by the calibration controller 9, to The M-bit adjustment register 8 is assigned; the calibration controller 9 only generates 1-digit value for each operation, so the calibration controller 9 needs to calculate M times to complete the assignment of one M-bit adjustment register 8, and the search method followed by the M-bit operations is binary method search mode; the common-mode charge adjustment circuit 6 generates a compensation voltage Vadj according to the M-bit digital code of the M-bit adjustment register 8, and under the action of the compensation voltage Vadj, controls the first digital-analog hybrid control type charge transmission circuit 3, the second The corresponding output common-mode charge of the two digital-analog hybrid control type charge transfer circuits 4; finally, the calibration controller 9 turns on the common-mode feedforward circuit 2, and makes the differential charge input terminal of the first digital-analog hybrid control type charge transfer circuit 3 . The differential charge input terminal of the second digital-analog hybrid control type charge transfer circuit 4 is reconnected to the differential input terminal Qin _,N and the differential input terminal Qin _,P . At this point, the calibration is completed, that is, the calibration mode ends, and the normal transmission mode enters. After entering the normal transmission mode, the calibration controller 9 and the detection processing circuit 7 enter into a sleep mode to reduce power consumption. In the normal working mode, the first common-mode charge detection circuit 1 and the common-mode feedforward circuit 2 are in working state.

As shown in Figure 2, the first digital-analog hybrid control type charge transfer circuit 3 and the second digital-analog hybrid control type charge transfer circuit 4 adopt the same circuit structure, and the first digital-analog hybrid control type charge transfer circuit 3 includes basic Enhanced charge transfer circuit 10, mirror control circuit 11, error amplifier 31, and common-mode feed-forward adjustment NMOS transistor M _1FF .

Specifically, the basic enhanced charge transfer circuit 10 is composed of a charge transfer transistor M _T , an NMOS transistor M ₂₁ , an NMOS transistor M ₂₂ and a PMOS transistor M ₂₃ ; the source of the NMOS transistor M ₂₁ is grounded, and the gate of the NMOS transistor M ₂₁ is connected to Input the charge signal Q _IN , the drain of the NMOS transistor M ₂₁ is connected to the source of the NMOS transistor M ₂₂ and the drain of the common mode feedforward adjustment NMOS transistor M _1FF , the substrate of the NMOS transistor M ₂₁ is connected to the control voltage V _BD ; The drain of M ₂₂ is connected to the gate of charge transfer transistor _MT and the drain of PMOS transistor M ₂₃ ; the source of PMOS transistor M ₂₃ and the substrate of PMOS transistor M ₂₃ are connected to power supply voltage; the source of charge transfer transistor _MT is The pole is connected to the gate terminal of the NMOS transistor M21, the drain of the charge transfer transistor M _T is the output charge signal Q _OUT ; the source of the common-mode feed-forward adjustment NMOS transistor M _1FF and the substrate of the common-mode feed-forward adjustment NMOS transistor M _1FF are both grounded, and the gate of the common-mode feedforward adjustment NMOS transistor M _1FF is connected to the first common-mode adjustment signal Vf. The first common-mode adjustment signal Vf is output by the common-mode feedforward circuit 2 .

The mirror control circuit 11 is composed of NMOS transistor M _21R , NMOS transistor M _22R and PMOS transistor M _23R ; the source of the NMOS transistor M _21R is grounded, the gate of the NMOS transistor M _21R is connected to the positive input signal terminal of the error amplifier 31, and the NMOS The drain of the tube M _21R is connected to the source of the NMOS tube M _22R , the substrate of the NMOS tube M _21R is connected to the control voltage V _BD ; the drain of the NMOS tube M _22R is connected to the drain of the PMOS tube M _23R ; the source of the PMOS tube M _23R The pole and the substrate of the PMOS transistor M _23R are both connected to the power supply voltage; the negative input signal terminal of the error amplifier 31 is connected to the compensation voltage Vadj, and the output signal terminal of the error amplifier is connected to the substrate to the control voltage V _BD .

As shown in FIG. 3 , the first common-mode charge detection circuit 1 and the second common-mode charge detection circuit 5 adopt the same circuit structure, wherein the first common-mode charge detection circuit 1 adopts a fully differential structure. Taking the second common-mode charge detection circuit 5 as an example, the second common-mode charge detection circuit 5 includes a first charge detector 12, a second charge detector 13, a third charge detector 14, and a fourth charge detector 15. A charge detector 12 and a fourth charge detector 15 are respectively connected to the differential charge output terminal Q _out,p and the full differential charge output terminal Q _outKn ; the output terminal of the first charge detector 12 is connected to one end of the sampling switch S1, and the sampling switch The other end of S1 is connected to one end of the capacitor C1 and one end of the sampling switch S2, the other end of the sampling switch S2 is connected to the output end of the second charge detector 13, and the input end of the second charge detector 13 is connected to the reference signal R _p , the input end of the third charge detector 14 is connected to the reference signal Rn, the output end of the third charge detector 14 is connected to one end of the sampling switch S3, the other end of the sampling switch S3 is connected to one end of the capacitor C2 and one end of the sampling switch S4 connected, the other end of the sampling switch S4 is connected to the output end of the fourth charge detector 15, the other end of the capacitor C1 is connected to one end of the sampling switch S5 and the positive input end of the full differential amplifier 13, and the other end of the capacitor C2 is connected to the sampling switch S6 is connected to the negative input terminal of the fully differential amplifier 13, the other end of the sampling switch S6 is connected to the other end of the sampling switch S5, and the other end of the sampling switch S5 and the other end of the sampling switch S6 are connected to the voltage VSet.

The first charge detector 12, the fourth charge detector 15, the sampling switch S1, and the sampling switch S4 are connected to the second clock Φ ₂ , the second charge detector 13, the third charge detector 14, the sampling switch S2, the sampling switch S3, The sampling switch S5 and the sampling switch S6 are connected to the first clock Φ ₁ , and the first clock Φ ₁ and the second clock Φ ₂ do not overlap with each other.

Specifically, for the sampling of the charge signal, if the traditional switched capacitor voltage sampling is used, one end of the MOS sampling switch will be directly connected to the differential charge storage node. Once there is a charge injection and discharge channel at the other end of the sampling switch, the differential The charge stored on the charge storage node will share the charge through the MOS sampling switch tube and the circuit at the other end of the sampling switch, so that the charges Q _outKp and Q _out,n on the differential charge storage node will change, thereby causing detection errors.

In order to avoid the detection error, in the embodiment of the present invention, the charge detector is used to detect the charge signal, so as to ensure that there is no charge injection and discharge channel in the charge storage node, and realize accurate sampling and amplification of the charge signal. After detecting the charge signal Q _out,p , the charge signal Q _out,n and the reference signal R _p , the reference signal R _n to obtain the voltage signal, further sampling is performed through the corresponding sampling switch and the capacitor C1 and capacitor C2 to obtain the differential The voltage signals V _i + and V _i − are amplified and compared by the fully differential amplifier 16 to obtain a first output error signal CM and a second output error signal CMn.

The specific schematic diagram of the fourth charge detector 15 is shown in the dotted line box in Fig. 3, is a source follower circuit controlled by the clock, of course, the first charge detector 12, the second charge detector 13, the third charge detector The charge detector 14 adopts the same circuit structure as the fourth charge detector 15 . The fourth charge detector 15 includes an NMOS transistor M31, an NMOS transistor M32, and an NMOS transistor M33. The source terminal of the NMOS transistor M31 is grounded, the drain terminal of the NMOS transistor M31 is connected to the source terminal of the NMOS transistor M32, and the drain terminal of the NMOS transistor M32 is connected to the NMOS transistor M32. The source terminal of the tube M33 is connected, the drain terminal of the NMOS tube M33 is connected to the power supply, the gate terminal of the NMOS tube M31 is connected to the bias voltage Vb, the gate terminal of the NMOS tube M32 is connected to the second clock Ф ₂ , and the gate terminal of the NMOS tube M33 Receive the charge signal Q _out,n . The drain terminal of the NMOS transistor M31 is connected to the source terminal of the NMOS transistor M22 to form an output terminal.

In the embodiment of the present invention, when the _second clock Φ2 is high, the fourth charge detector 15 is in the conduction normal detection state, and the change of the charge signal Q _out,n will be responded by the source follower to obtain the output voltage signal V _outn ; when the second clock Φ ₂ is low, the fourth charge detector 15 is in an off state, and the output voltage signal V _outn is pulled to ground. Considering the voltage drop generated by the source follower, the NMOS transistor M33 is realized by using a low-threshold NMOS transistor. As for the fully differential amplifier 13, it can be completed by using the existing very mature differential voltage comparator.

As shown in FIG. 4 , it is a schematic circuit diagram of an implementation of the common-mode feedforward circuit 2 of the present invention. The common-mode feedforward circuit 2 includes a PMOS current mirror circuit, a differential input pair, and a current mirror bias circuit.

The PMOS current mirror circuit includes a PMOS transistor M3 and a PMOS transistor M4, the gate terminal of the PMOS transistor M3 is connected to the drain terminal of the PMOS transistor M3 and the gate terminal of the PMOS transistor M4, and the source terminals of the PMOS transistor M3 and the PMOS transistor M4 are connected to each other. connected to the power supply; the gate terminal of the PMOS transistor M3 and the drain terminal of the PMOS transistor M3 are connected to the drain terminal of the reset MOS transistor Ms1, and the drain terminal of the PMOS transistor M4 is connected to the drain terminal of the reset MOS transistor Ms2; the drain terminal of the reset MOS transistor Ms1 The gate terminal and the gate terminal of the reset MOS transistor Ms2 are connected to the second clock Φ ₂ .

The differential input pair includes a MOS transistor M1 and a MOS transistor M2; the drain terminal of the MOS transistor M1 is connected to the source terminal of the reset MOS transistor Ms1; the drain terminal of the MOS transistor M2 is connected to the source terminal of the reset MOS transistor Ms2; The source terminal of MOS transistor M1 is connected to the drain terminal of MOS transistor M5 through source resistor R1, and the source terminal of MOS transistor M2 is connected to the drain terminal of MOS transistor M5 through source resistor R2; the gate terminal of MOS transistor M5 is connected to the drain terminal of MOS transistor M5. The gate terminal of M8 is connected to the drain terminal of MOS transistor M8, the source terminal of MOS transistor M5 is connected to the drain terminal of MOS transistor M6, the drain terminal of MOS transistor M6 is grounded, the source terminal of MOS transistor M8 is grounded, and the gate terminal of MOS transistor M6 It is connected to the gate terminal of the MOS transistor M7 and the drain terminal of the MOS transistor M7, and the source terminal of the MOS transistor M7 and the source terminal of the MOS transistor M8 are both grounded. The drain terminal of the MOS transistor M8 is connected to the bias current Ib1, and the drain terminal of the MOS transistor M7 is connected to the bias current Ib2.

The gate terminal of the MOS transistor M1 receives the first output error signal CM, the gate terminal of the MOS transistor M2 is connected to the second output error signal CMn, and the drain terminal of the MOS transistor M2 is connected to the source terminal of the reset MOS transistor Ms2. In the embodiment of the present invention, the input differential pair MOS transistor M1 and MOS transistor M2 are operated in the linear region, the MOS transistor M5 and the MOS transistor M6 form an NMOS current mirror, and the MOS transistor M7 and the MOS transistor M8 form an NMOS current.

The detection processing circuit 7 selects the result of the second common-mode charge detection circuit 5, and then processes it according to a set processing method, and stores the result in its internal register. During common-mode calibration, the calibration controller 9 reads the values of the two registers, and judges the level of the common-mode charge of the detected common-mode point through the value of the flag signal SGN, thereby adjusting the corresponding control voltage, thereby To achieve the purpose of common-mode charge calibration.

As shown in Figure 5, the circuit schematic diagram of the common-mode charge adjustment circuit 7, the basic structure of the common-mode charge adjustment circuit 7 is similar to an LDO circuit, including a working state control switch M51, an output buffer operational amplifier 17, and a voltage output adjustment PMOS Tube M50, a resistor string for dividing the output compensation voltage VadjK, an M-bit DAC module 18 for adjusting the output voltage, a capacitor C52 for decoupling and filtering the output reference signal VadjK, and an output buffer operational amplifier 17 Resistor R51 and capacitor C51 for stable compensation.

When starting to enter the normal working mode, the control signal is set to 1, and the working state control switch M51 is turned on. Due to the negative feedback effect of the output buffer operational amplifier 17, the reference voltage VREF is obtained by dividing the voltage through the resistor string under the control of the voltage output adjustment PMOS transistor M50 An initial voltage output VR(0), and at the same time, the DAC module 18 will also generate an adjustment current Ic to the ground, and the adjustment current Ic flows through the end resistance to the ground, so that a ⊿V=Ic×R324 will be superimposed on the resistance The amount of voltage, the voltage output to the reference signal output circuit VR = VR (0) + ⊿V. After VR is changed, the output compensation voltage VadjK will correspondingly increase by a voltage of ⊿V according to the voltage division relationship of the resistors. Therefore, the purpose of changing the output reference voltage can be achieved only by controlling the M-bit adjustment code. The DAC module 26 generates the adjustment current Ic according to the M-bit adjustment code. The specific process of generating the adjustment current Ic is well known to those skilled in the art and will not be repeated here. For other common-mode adjustment circuits 7, reference may be made to the above description, which will not be repeated here.

As shown in Figure 6, it is a functional block diagram of the detection processing circuit 7 of the present invention, the detection processing circuit 7 includes a 16-bit counter 30, a 16-bit counter 21 with pulse swallowing, a K:1 selector 19, the first 8: 1 selector 29, the second 8:1 selector 20, 16:1 selector 22, a swallow pulse control circuit 27, a reset signal generating circuit 28, a scan sequence generator 26, a window signal generator 25, a Signal comparison circuit 23 and a readout controller 24.

Specifically: the input reset signal is connected to the first reset terminal of the 16-bit counter 21 with pulse swallowing and the reset terminal of the reset signal generation circuit 28; the K input terminals of the K:1 selector 19 are respectively connected to the second common mode charge The output terminal of the detection circuit 5, the output terminal of the K:1 selector 19 is connected to the data input terminal of the second 8:1 selector 20; the control input terminal of the second 8:1 selector 20 is connected to the common mode selection control signal , the enabling end of the second 8:1 selector 20 is connected to the second reset end of the 16-bit counter 21 with pulse swallowing; the third input end of the 16-bit counter 21 with pulse swallowing is connected to the swallowing pulse control circuit 27 Output terminal, the fourth input terminal of the 16-bit counter 21 with pulse swallowing is connected to the input clock, the output terminal of the 16-bit counter 21 with pulse swallowing is connected to the data input terminal of the 16:1 selector 22 and the readout controller 24 The data input end of 16:1 selector 22 is connected to the output end of scan sequence generator 26, and the data output end of 16:1 selector 22 is connected to the first data input end of signal comparison circuit 23; The second data input terminal of signal comparison circuit 23 is connected to the output terminal of window signal generator 25, and the output terminal of signal comparison circuit 18 promptly outputs sign signal SGN; 18 output terminals of readout controller promptly output state signal B3; Reset signal The output end of generating circuit 28 is connected to the reset signal input end of swallowing pulse control circuit 27, the reset signal input end of scan sequence generator 26 and the reset signal input end of 16-bit counter 30 simultaneously; The first input end of 16-bit counter 30 Connected to the input clock, the low 4-bit output of the 16-bit counter 30 is connected to the control signal input of the swallowing pulse control circuit 27, and the high 8-bit output of the 16-bit counter 30 is connected to the first 8:1 selector 23 data signal Input terminal; the output terminal of the first 8:1 selector 23 is connected to the data input terminal of the reset signal generating circuit 28 .

The 16-bit counter 30 is the main counter, and when the input reset signal changes from 0 to 1, the 16-bit counter 30 starts counting. Its high 8-bit output is used to control the reset generation circuit 22 after being selected by the first 8:1 selector 29, as long as the output of the first 8:1 selector 29 is high level, the reset signal generation circuit 28 outputs the reset signal, The reset signals mentioned above are all generated and output by the reset signal generation circuit 28 ; the lower 4 bits of the 16-bit counter 30 are input to the swallowing pulse control circuit 27 .

The 16-bit counter 21 with pulse swallowing must be in the counting state, and the following three conditions must be met at the same time: 1), the reset signal is at a high level; 2), the swallowing control pulse signal is at a high level; 3), the second The signal selected by the 8:1 selector 20 is at high level. When a signal selected by the second 8:1 selector 20 is at a high level, the output of a certain common-mode charge detection circuit 4 described above is at a high level.

The working sequence of the detection processing circuit 2 is as follows: 1), the reset signal changes from 0 to 1, and the 16-bit counter 30 is started; 2), the swallowing pulse control circuit 27 also starts to work, and outputs a frequency divided by 16 from the main clock, and occupies The clock of the empty ratio bit 0.5;, 3), the 16-bit counter 21 with pulse swallowing begins to count, but the value of the 16 counter 15 with pulse swallowing is 1/16 of the 16-bit counter 30 count value (due to pulse swallowing causes ); 4), after the 16-bit counter 30 is full (the output of the first 8:1 selector 29 becomes high level), the reset signal generating circuit 28 outputs a reset signal, and the 16-bit counter 30 and the swallowing pulse control circuit 27 are reset , output low level; 5), the scan sequence generator 26 starts to work, outputs 4 scan pulses, and outputs 0~15 in total 16 states in turn, so that each bit in the 16-bit counter 21 with pulse swallowing is scanned output, and is read into the reading controller 24 in four times; 6), the window signal generator 25 generates an observation window signal, which is matched with the scanning sequence and used to judge the 16-bit counter 21 with pulse swallowing Whether a certain bit is high level, if the bit selected by the window signal in the 16-bit counter 21 with pulse swallowing is high level, then the flag signal SGN is high level, otherwise it is low level. 16-bit counter 30, 16-bit counter with pulse swallowing 21, K:1 selector 19, first 8:1 selector 29, second 8:1 selector 20, 16:1 selector 22, swallowing pulse control circuit 27. The reset signal generation circuit 28, the scan sequence generator 26, the window signal generator 25, the signal comparison circuit 23 and the readout controller 24 can all adopt existing commonly used circuit structures, which are well known to those skilled in the art. I won't repeat them here.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (4)

1. a kind of fully differential charge transfer circuit for accurately controlling common mode charge amount, including the first numerical model analysis control type electric charge Transmission circuit（3）And the second numerical model analysis control type charge transfer circuit（4）；It is characterized in that：Also include the first common mode charge Detect circuit（1）, common mode feed forward circuit（2）, the second common mode charge detection circuit（5）, detection process circuit（7）, common mode charge Adjustment circuit（6）, M positions adjustment register（8）And controller calibration（9）；

Differential input endQ _in,p , differential input endQ _in,n It is connected respectively to the first common mode charge detection circuit（1）Differential charge it is defeated Enter end, the first common mode charge detection circuit（1）Output end be connected to common mode feed forward circuit（2）Input；Fed before common mode Road（2）Output end Vf simultaneously be connected to the first numerical model analysis control type charge transfer circuit（3）The first common mode adjustment signal Input FF, the second numerical model analysis control type charge transfer circuit（4）The first common mode adjustment signal input part FF；First digital-to-analogue Mix control type charge transfer circuit（3）Output end, the second numerical model analysis control type charge transfer circuit（4）Output end point The second common mode charge detection circuit is not connected to（5）Differential charge input, the second common mode charge detection circuit（5）Output End is connected to detection process circuit（7）Input；Detection process circuit（7）Output end be connected to controller calibration（9）'s Detection signal input；Controller calibration（9）M positions compensation codes output end be connected to M positions adjustment register（8）Signal input End, M positions adjustment register（8）Signal output part be connected to common mode charge adjustment circuit（6）Control signal input；Common mode Electric charge adjustment circuit（6）Control signal output simultaneously be connected to the first numerical model analysis control type charge transfer circuit（3）'s Second common mode adjustment signal input part FB, the second numerical model analysis control type charge transfer circuit（4）The second common mode adjustment signal Input FB.

2. the fully differential charge transfer circuit according to claim 1 for accurately controlling common mode charge amount, it is characterized in that：School Collimator controller（9）It can control and enter calibration mode or normal mode of operation；

Initially enter calibration mode, controller calibration（9）By the first modulus mixing control type charge transfer circuit（3）, second number Mould mixing control type charge transfer circuit（4）Corresponding differential input end is connected to input reference voltage；And then first is opened Common mode charge detects circuit（1）And second common mode charge detection circuit（5）, the second common mode charge detection circuit（5）Output Process circuit is detected successively（7）Statistical disposition is carried out, then by controller calibration（9）Computing is carried out, register is adjusted to M positions （8）Carry out assignment；Common mode charge adjustment circuit（6）Register is adjusted according to M positions（8）M digit numeric codes produce offset voltage Vadj, in the presence of the offset voltage Vadj, control the first numerical model analysis control type charge transfer circuit（3）, second number Mould mixing control type charge transfer circuit（4）The corresponding output common mode quantity of electric charge；Finally, controller calibration（9）Before opening common mode Current feed circuit（2）, and cause the first numerical model analysis control type charge transfer circuit（3）Differential charge input, the second digital-to-analogue mixes Close control type charge transfer circuit（4）Differential charge input reconnect differential input endQ _in,N , differential input endQ _in,P ；

Complete it is above-mentioned after, calibration control（9）Control enters normal transmission mode；After normal transmission mode is entered, calibration control Device（9）With detection process circuit（7）Into park mode.

3. the fully differential charge transfer circuit according to claim 1 for accurately controlling common mode charge amount, it is characterized in that：The Two common mode charges detect circuit（5）Including the first electric charge detector（12）, the second electric charge detector（13）, tricharged detector （14）And the 4th electric charge detector（15）；

First electric charge detector（12）, the 4th electric charge detector（15）Differential charge output end is connected respectivelyQ _out,p , fully differential electricity Lotus output endQ _outKn ；First electric charge detector（12）Output end be connected with sampling switch S1 one end, sampling switch S1's is another One end is connected with electric capacity C1 one end and sampling switch S2 one end, the sampling switch S2 other end and the second electric charge detector （13）Output end connection, the second electric charge detector（13）Input and reference signalR _pConnection, tricharged detector （14）Input be connected with reference signal Rn, tricharged detector（14）Output end and sampling switch S3 one end connect Connect, the sampling switch S3 other end is connected with one end of electric capacity C2 one end and sampling switch S4, and sampling switch S4's is another End and the 4th electric charge detector（15）Output end connection, the electric capacity C1 other end and sampling switch S5 one end and fully differential Amplifier（13）Positive input terminal connection, the electric capacity C2 other end and sampling switch S6 and fully-differential amplifier（13）It is negative defeated Enter end connection, the sampling switch S6 other end is connected with the sampling switch S5 other end, and the sampling switch S5 other end and Sampling switch S6 another termination voltage VSet；

First electric charge detector（12）, the 4th electric charge detector（15）, sampling switch S1, sampling switch S4 connection second clocks Φ₂, the second electric charge detector（13）, tricharged detector（14）, sampling switch S2, sampling switch S3, sampling switch S5 with And sampling switch S6 the first clocks of connection Φ₁, the first clock Φ₁With second clock Φ₂It is mutually non-overlapping.

4. the fully differential charge transfer circuit according to claim 1 for accurately controlling common mode charge amount, it is characterized in that：Altogether Mould feed forward circuit（2）Including PMOS current mirroring circuits, Differential Input to, current-mirror bias circuit；

The PMOS current mirroring circuits include PMOS M3 and PMOS M4, the PMOS M3 gate terminal with PMOS M3's Drain electrode end, PMOS M4 gate terminal are connected, and PMOS M3, PMOS M4 source terminal are connected with each other and are followed by power supply；PMOS M3 gate terminal, PMOS M3 drain electrode end are connected with resetting metal-oxide-semiconductor Ms1 drain electrode end, and PMOS M4 drain electrode end is with answering Position metal-oxide-semiconductor Ms2 drain electrode end is connected；When the gate terminal for resetting metal-oxide-semiconductor Ms1 and the gate terminal for resetting metal-oxide-semiconductor Ms2 are connected to second Clock Ф₂；

Differential Input is to including metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2；The drain electrode end of the metal-oxide-semiconductor M1 and the source terminal for resetting metal-oxide-semiconductor Ms1 It is connected；The drain electrode end of the metal-oxide-semiconductor M2 is connected with resetting metal-oxide-semiconductor Ms2 source terminal；The source terminal of the metal-oxide-semiconductor M1 passes through source Electrode resistance R1 is connected with metal-oxide-semiconductor M5 drain electrode end, and metal-oxide-semiconductor M2 source terminal passes through source resistance R2 and metal-oxide-semiconductor M5 drain electrode End is connected；Metal-oxide-semiconductor M5 gate terminal is connected with metal-oxide-semiconductor M8 gate terminal, metal-oxide-semiconductor M8 drain electrode end, metal-oxide-semiconductor M5 source terminal with Metal-oxide-semiconductor M6 drain electrode end connection, metal-oxide-semiconductor M6 drain electrode end ground connection, metal-oxide-semiconductor M8 source terminal ground connection, metal-oxide-semiconductor M6 gate terminal Gate terminal, metal-oxide-semiconductor M7 drain electrode end with metal-oxide-semiconductor M7 are connected, and metal-oxide-semiconductor M7 source terminal, metal-oxide-semiconductor M8 source terminal are grounded；

Metal-oxide-semiconductor M8 drain electrode termination bias current Ib1, metal-oxide-semiconductor M7 drain electrode termination bias current Ib2；

Metal-oxide-semiconductor M1 gate terminal receives the first output error signal CM, metal-oxide-semiconductor M2 gate terminal and the second output error signal CMn is connected, and metal-oxide-semiconductor M2 drain electrode end is connected with resetting metal-oxide-semiconductor Ms2 source terminal.