CN107910270B - Power semiconductor device and method for manufacturing the same - Google Patents

Abstract

The application discloses a power semiconductor device and a method of manufacturing the same. The method comprises the following steps: forming a plurality of trenches in a semiconductor substrate; forming split gate structures in the first trench and the second trench; forming a shield wiring in the third trench; a body region in the semiconductor substrate; forming a source region in the body region; and forming a source electrode, a gate electrode, and a shield electrode electrically connected to the source region, the gate conductor, and the shield wiring, respectively, wherein the shield wiring is electrically connected to the shield conductor, and the shield wiring includes a first portion filling the third trench and a second portion extending laterally at the surface of the semiconductor substrate, the second portion being for rewiring. The method improves charge balance effect by using shielding wiring of independent extraction electrodes, and uses shielding wiring for rewiring to improve device yield and reliability.

Description

Power semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the technical field of electronic devices, and more particularly to a power semiconductor device and a method for manufacturing the same.

Background technique

Power semiconductor devices are also called power electronic devices, including power diodes, thyristors, VDMOS (vertical double diffused metal oxide semiconductor) field effect transistors, LDMOS (lateral diffused metal oxide semiconductor) field effect transistors, and IGBTs (insulated gate bipolar transistors). VDMOS field effect transistors include source and drain regions formed on opposite surfaces of a semiconductor substrate, and in the on state, current flows mainly along the longitudinal direction of the semiconductor substrate.

In the high-frequency application of power semiconductor devices, lower conduction loss and switching loss are important indicators for evaluating device performance. Based on the VDMOS field effect transistor, the trench MOS field effect transistor was further developed, in which a gate conductor is formed in the trench, and a gate dielectric is formed on the sidewall of the trench to separate the gate conductor and the semiconductor layer, thereby forming a channel in the semiconductor layer along the direction of the trench sidewall. The trench process changes the channel from horizontal to vertical, eliminating the influence of the parasitic JFET resistance of the planar structure, and greatly reducing the cell size. On this basis, increasing the cell density and increasing the total width of the channel per unit area of the chip can increase the channel width-to-length ratio of the device on a unit silicon wafer, thereby increasing the current, reducing the on-resistance, and optimizing related parameters, achieving the goal of having a smaller die with greater power and high performance. Therefore, the trench process is increasingly used in new power semiconductor devices.

However, as the cell density increases, the inter-electrode resistance will increase, and the switching loss will increase accordingly. The gate-drain capacitance Cgd is directly related to the switching characteristics of the device. In order to reduce the gate-drain capacitance Cgd, a split gate trench (Split Gate Trench, abbreviated as SGT) type power semiconductor device has been further developed, in which the gate conductor extends to the drift region, and the gate conductor and the drain are separated by a thick oxide, thereby reducing the gate-drain capacitance Cgd, improving the switching speed, and reducing the switching loss. At the same time, the shielding conductor under the gate conductor is connected to the source electrode and grounded together, thereby introducing a charge balancing effect, and having a reduced surface field (Reduced Surface Field, abbreviated as RESURF) effect in the vertical direction of the power semiconductor device, further reducing the on-resistance Rdson, thereby reducing the conduction loss.

1a and 1b are cross-sectional views of the main steps of a method for manufacturing an SGT power semiconductor device according to the prior art. As shown in FIG. 1a, a trench 102 is formed in a semiconductor substrate 101. A first insulating layer 103 is formed at the lower portion of the trench 102, and a shield conductor 104 fills the trench 102. At the upper portion of the trench 102, two openings separated by the shield conductor 104 are formed. Further, as shown in FIG. 1b, a gate dielectric 105 is formed on the upper sidewall of the trench 102 and the exposed portion of the shield conductor 104, and then a conductive material is filled in the two openings separated by the shield conductor 104 to form two gate conductors 106.

In the SGT power semiconductor device, a shield conductor 104 is connected to the source electrode of the power semiconductor device to generate a RESURF effect. Two gate conductors 106 are located on both sides of the shield conductor 104. The shield conductor 104 is separated from the drain region of the power semiconductor device by a first insulating layer 103, and is separated from the gate electrode 106 by a gate dielectric 105. The gate conductor 106 is separated from the well region in the semiconductor substrate 101 by the gate dielectric 105, thereby forming a channel in the well region. As shown in the figure, the thickness of the first insulating layer 103 is less than the thickness of the gate dielectric 105.

According to the SGT theory, no matter which SGT structure is used, the material of the shielding conductor 104 needs to be isolated from the second conductive material and the material used for isolation needs to meet certain capacitance parameters, otherwise it is easy to cause failures such as gate-source short circuit and abnormal gate-drain capacitance Cgd. How to optimize the device structure and meet the product's parameter and reliability requirements, while making the wiring method the most efficient and low-cost is what the technical personnel in this field need to study.

Summary of the invention

In view of the above problems, an object of the present invention is to provide a power semiconductor device and a manufacturing method thereof, wherein shielding wiring of independent lead-out electrodes is used to improve the charge balance effect, and an isolation layer is used in the wiring area of the shielding conductor to reduce the process steps.

According to a first aspect of the present invention, a method for manufacturing a power semiconductor device is provided, comprising: forming a plurality of grooves in a semiconductor substrate of a first doping type, the plurality of grooves comprising first to third grooves respectively located in a first region to a third region of the semiconductor substrate; forming a split gate structure in the first groove and the second groove, the split gate structure comprising a shielding conductor, a gate conductor and a second insulating layer sandwiched therebetween; forming at least a portion of a shielding wiring in the third groove; forming a body region of a second doping type in a region of the semiconductor substrate adjacent to the groove, the second doping type being opposite to the first doping type; forming a source region of the first doping type in the body region; and forming a source electrode, a gate electrode and a shielding electrode respectively electrically connected to the source region, the gate conductor and the shielding wiring, wherein the shielding wiring is electrically connected to the shielding conductor, and the shielding wiring comprises a first portion filling the third groove and a second portion extending laterally on the surface of the semiconductor substrate, the second portion being used for rewiring.

Preferably, the step of forming a split gate structure in the first trench and the second trench includes: forming an insulating stack on the sidewalls and bottom of the first trench and the second trench, the insulating stack including a first insulating layer and a second insulating layer, the first insulating layer surrounding the second insulating layer; forming an opening and the shielding conductor at the upper and lower parts of the first trench and the second trench, respectively; removing a portion of the first insulating layer at the upper part of the first trench and the second trench; forming a gate dielectric on the sidewalls of the upper part of the first trench; and forming the gate conductor to fill the opening, wherein the gate conductor and the shielding conductor are isolated from each other by the gate dielectric, the gate conductor and the body region are isolated from each other by the gate dielectric, and the shielding conductor and the semiconductor substrate are isolated from each other by the insulating stack.

Preferably, the step of forming a shielding wiring in the third groove includes: forming an insulating stack on the sidewall and bottom of the third groove, the insulating stack including a first insulating layer and a second insulating layer, the first insulating layer surrounding the second insulating layer; forming the shielding wiring to fill the third groove, wherein the shielding wiring and the semiconductor substrate are isolated from each other by the insulating stack.

Preferably, the shield conductor and the shield wiring are formed of a same conductor layer in the first trench, the second trench, and the third trench.

Preferably, the step of forming the gate conductor includes: forming a conductor layer, a first portion of the conductor layer filling the opening and a second portion extending laterally above the surface of the semiconductor substrate; and etching the conductor layer to remove the second portion of the conductor layer, the first portion of the conductor layer remaining in the first groove and the second groove forming the gate conductor.

Preferably, the source electrode is located in the first region, the gate electrode is located in the second region, the shielding electrode is located in the third region, and the first region, the second region and the third region are separated from each other.

Preferably, the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride or polysilicon.

Preferably, the thickness of the first insulating layer is in the range of 500 to 50,000 angstroms, and the thickness of the second insulating layer is in the range of 50 to 5,000 angstroms.

Preferably, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

Preferably, sidewalls of the plurality of grooves are inclined such that top widths of the plurality of grooves are greater than bottom widths of the plurality of grooves.

Preferably, the step of forming the shield conductor, the step of forming the shield wiring, and the step of forming the gate conductor each include at least one deposition.

According to a second aspect of the present invention, a power semiconductor device is provided, comprising: a plurality of trenches in a semiconductor substrate, the semiconductor substrate being of a first doping type, the plurality of trenches comprising first to third trenches respectively located in a first region to a third region of the semiconductor substrate; a split gate structure located in the first trench and the second trench, the split gate structure comprising a shielding conductor, a gate conductor and a second insulating layer sandwiched therebetween; a shielding wiring at least partially located in the third trench; a body region located in the semiconductor substrate, the body region being adjacent to an upper portion of the first trench and being of a second doping type, the second doping type being opposite to the first doping type; a source region located in the body region, the source region being of the first doping type; and a source electrode, a gate electrode and a shielding electrode electrically connected to the source region, the gate conductor and the shielding wiring, respectively, wherein the shielding wiring is electrically connected to the shielding conductor, and the shielding wiring comprises a first portion filling the third trench and a second portion extending laterally on a surface of the semiconductor substrate, the second portion being used for rewiring.

Preferably, the split-gate structure in the first trench and the second trench includes: an insulating stack located on the lower sidewalls and bottom of the first trench and the second trench, the insulating stack including a first insulating layer and a second insulating layer, the first insulating layer surrounding the second insulating layer; a shielding conductor located in the lower portion of the first trench and the second trench; and a gate conductor located in the upper portion of the first trench and the first trench, wherein the gate conductor and the shielding conductor are isolated from each other by the gate dielectric, the gate conductor and the body region are isolated from each other by the gate dielectric, and the shielding conductor and the semiconductor substrate are isolated from each other by the insulating stack.

Preferably, the source electrode is located in the first region, the gate electrode is located in the second region, the shielding electrode is located in the third region, and the first region, the second region and the third region are separated from each other.

Preferably, the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride or polysilicon.

Preferably, the thickness of the first insulating layer is in the range of 500 to 50,000 angstroms, and the thickness of the second insulating layer is in the range of 50 to 5,000 angstroms.

Preferably, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

Preferably, sidewalls of the plurality of grooves are inclined such that top widths of the plurality of grooves are greater than bottom widths of the plurality of grooves.

Preferably, the power semiconductor device is one selected from a CMOS device, a BCD device, a MOSFET transistor, an IGBT and a Schottky diode.

In the method according to an embodiment of the present invention, an SGT structure is formed in a power semiconductor device, wherein an insulating stack is formed between a shield conductor and a semiconductor substrate, thereby reducing the gate-drain capacitance Cgd. The SGT structure includes a source electrode, a gate electrode and a shield electrode electrically connected to the source region, the gate conductor and the shield wiring respectively, and the shield wiring is electrically connected to the shield conductor. The shield wiring of the independent lead-out electrode is used, for example, to apply a bias voltage separately to the shield conductor, thereby improving the charge balance effect. The use of an isolation layer allows the split gate structure and the shield conductor in different regions to be formed in a common step, thereby reducing the manufacturing cost. The method realizes the SGT structure through relatively simple process steps, solves the problems of complex process, gate-source short circuit, gate-drain capacitance Cgd abnormality, etc. in the conventional process, thereby meeting the parameters and reliability requirements of the product, and combining the specific process steps to make the wiring method the most efficient and low-cost. Compared with the prior art, based on the 0.25-0.35um process, this method can reduce the photoresist mask used in the current manufacturing process by 3-4 photoresist masks.

The split-gate power semiconductor device structure and formation method thereof for reducing source-drain capacitance adopted in the embodiment of the present invention can also be applied to products such as CMOS, BCD, power MOSFET, high-power transistor, IGBT and Schottky.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

1 a and 1 b are cross-sectional views respectively showing main steps of a method for manufacturing a power semiconductor device according to the prior art.

FIG. 2 is a flow chart showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention.

3a to 3i show different stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed ways

The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is adjacent to B, rather than A being located in a doped region formed in B.

In the present application, the term "semiconductor structure" refers to a general term for the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.

Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

Unless otherwise specified below, each part of the semiconductor device may be made of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si and Ge.

Fig. 2 is a flow chart of a method for manufacturing a SGT power semiconductor device according to an embodiment of the present invention, and Fig. 3a to 3i are cross-sectional views at different steps, respectively. The steps of the manufacturing method according to an embodiment of the present invention are described below in conjunction with Fig. 2 and Fig. 3a to 3i.

The method starts with a semiconductor substrate 101. The semiconductor substrate is, for example, a silicon substrate doped into an N-type, the longitudinal doping of the silicon substrate is uniform, and the resistivity is, for example, in the range of 1 to 15 Ω·cm. The semiconductor substrate has a first surface and a second surface relative to each other. Preferably, on the first surface of the semiconductor substrate, a voltage divider ring structure of a power semiconductor is formed by processes such as photolithography, etching, ion implantation, and impurity activation. The voltage divider ring structure is a well-known structural part of the device structure in the art and is not described in detail here. Preferably, the semiconductor substrate 101 used in this embodiment can be formed with semiconductor devices such as MOS field effect transistors, IGBT insulated gate field effect transistors, and Schottky diodes.

In step S101 , trenches 102 are formed in the first region 201 , the second region 202 , and the third region 203 of the semiconductor substrate 101 , respectively, as shown in FIG. 3 a .

The process for forming the trench 102 includes forming a resist mask by photolithography and etching, and removing the exposed portion of the semiconductor substrate 101 by etching through the opening of the resist mask.

In this embodiment, the first region 201 refers to the wiring region of the source region in the SGT structure, the second region 202 refers to the wiring region of the gate conductor in the SGT structure, and the second region 203 refers to the wiring region of the shield conductor in the SGT structure.

The groove 102 extends downward from the surface of the semiconductor substrate 101 and reaches a predetermined depth in the semiconductor substrate 101. In this embodiment, the width of the groove 102 is, for example, 0.2 to 10 microns, and the depth is, for example, 0.1 to 50 microns. The width of the groove of the SGT structure is much wider than the groove of a conventional trench power semiconductor device with the same conduction efficiency level, and the depth of the groove is also much deeper than the groove of a conventional trench power semiconductor device.

Preferably, the sidewalls of the trench 102 are inclined, for example, at an angle of 85 to 89 degrees relative to the top of the vertical trench 102, so that the bottom width of the trench 102 is smaller than the top width. The steeper angle of the trench facilitates the subsequent filling of each dielectric layer and conductive material, and reduces defects caused by filling gaps.

In step S102 , an insulating stack is sequentially formed on the surface of the semiconductor substrate 101 , the insulating stack comprising a conformal first insulating layer 122 and a second insulating layer 123 , as shown in FIG. 3 b .

In the trench 102, the first insulating layer 122 surrounds the second insulating layer 123. The first insulating layer 122 and the second insulating layer 123 are composed of different insulating materials. In this embodiment, the first insulating layer 122 is composed of silicon oxide, for example. The second insulating layer 123 is composed of at least one selected from silicon nitride, oxynitride or polysilicon, for example. Preferably, the second insulating layer 123 is composed of silicon nitride. The thickness of the first insulating layer 122 is, for example, 500 to 50,000 angstroms, and the thickness of the second insulating layer 123 is, for example, 50 to 5,000 angstroms. The greater the thickness of the first insulating layer 122, the smaller the gate-drain capacitance Cgd.

The process for forming the first insulating layer 122 includes forming an oxide layer on the inner wall of the trench 102 by thermal oxidation, chemical vapor deposition (CVD) or high-density plasma chemical vapor deposition. The oxide layer conformally covers the sidewalls and bottom of the trench 102, thereby still retaining a portion of the inner space of the trench 102.

The process for forming the second insulating layer 123 includes forming a nitride layer on the surface of the first insulating layer 122 by chemical vapor deposition (CVD) or high density plasma chemical vapor deposition. The nitride layer conformally covers the surface of the first insulating layer 122, thereby still retaining a portion of the inner space of the trench 102.

In step S103, openings 124 and shield conductors 104 are formed in the upper and lower portions of the trenches 102 in the first and second regions 201 and 202, respectively, and shield wiring 131 is formed in the trenches 102 in the third region 203, as shown in FIG. 3c.

In this embodiment, the shield conductor 104 and the shield wiring 131 are formed by the same conductor layer, for example, they are composed of doped amorphous silicon or polycrystalline silicon. The process for forming the conductor layer includes, for example, depositing polycrystalline silicon by sputtering or other processes, so that the polycrystalline silicon fills the remaining part of the groove 102. Then, in the first area 201 and the second area 202, the conductor layer and the second insulating layer 123 are etched to remove the portion located outside and above the groove 102, thereby forming an opening at the upper part of the groove 102.

Preferably, the conductor layer used to form the shield conductor 104 and the shield wiring 131 is composed of polycrystalline silicon. The deposition rate of the polycrystalline silicon is, for example, 1 to 100 angstroms per minute, the deposition temperature is, for example, 510 to 650 degrees Celsius, and the thickness is, for example, 1000 to 100000 angstroms. By controlling the doping concentration of the conductor layer, its resistance can be adjusted. In this embodiment, the square resistance Rs of the conductor layer is, for example, less than 20 ohms. Further, the smaller the square resistance Rs of the conductor layer, the greater the thickness of the oxide layer formed in the subsequent oxidation process compared with silicon. Further, the material of the conductor layer is selected to be amorphous, and it is easier to form a lower square resistance Rs.

In the above-mentioned deposition step, one or more depositions may be used to form the conductor layer material. In multiple depositions, the rate of the subsequent deposition step is lower than that of the previous deposition step, so that the deposition rate gradually decreases. In the process of trench filling, the slower the deposition rate, the better the filling effect. The bottom of the trench is more difficult to fill than the top of the trench. Therefore, in multiple fillings, the rate of the previous deposition needs to be lower than the rate of any subsequent deposition.

In the etching step, a resist mask is formed by photolithography and etching to expose the first region 201 and the second region 202 of the semiconductor substrate 101, and the third region 203 that blocks the semiconductor substrate 101. In the above-mentioned etching step, wet etching can be used. Due to the selectivity of the etchant, the exposed portion of the conductor layer and the second insulating layer 123 is removed relative to the first insulating layer 122. The etching not only removes the portion of the conductor layer and the second insulating layer 123 located outside the groove 102, but also etches back the portion of the conductor layer and the second insulating layer 123 located inside the groove 102. After etching, the portion of the conductor layer retained in the groove 102 of the first region 201 and the second region 202 forms a shield conductor 104. In the third region 203, the shield wiring 131 includes a first portion in the groove 102 of the third region 203 and a second portion extending laterally on the surface of the semiconductor substrate 101. Preferably, the etching step includes two etchings, using different etchants, in which the exposed portion of the conductor layer relative to the second insulating layer 123 is removed in the first etching, and in the second etching, the exposed portion of the second insulating layer 123 is removed relative to the first insulating layer 122. After the back etching, an opening 124 of a predetermined depth is formed in the trench 102, for example, the depth is 0.2 to 4 microns extending downward from the surface of the semiconductor substrate 101. The opening 124 re-exposes the upper sidewall of the trench 102.

In step S104 , a portion of the first insulating layer 122 is removed by etching in the trenches of the first region 201 and the second region 202 , as shown in FIG. 3 d .

In the etching step, a resist mask is formed by photolithography and etching to expose the first region 201 and the second region 202 of the semiconductor substrate 101, and the third region 203 that blocks the semiconductor substrate 101. The etching process is, for example, wet etching. Due to the selectivity of the etchant, the exposed portion of the first insulating layer 122 is removed relative to the semiconductor substrate 101. The depth of the opening 124 extending downward from the surface of the semiconductor substrate 101 is, for example, 0.5 to 5 microns. The etching removes the portion of the first insulating layer 122 located at the upper portion of the groove 102. After etching, a portion of the first insulating layer 122 located at the lower sidewall and bottom of the groove 102 is retained, so that the lower portion of the shield conductor 104 and the shield wiring 131 are still isolated from each other by the insulating stack between the semiconductor substrate 101.

In step S105 , a gate dielectric 105 is formed on the upper sidewall of the trench 102 and the top of the shield conductor 104 , as shown in FIG. 3 e .

The process for forming the gate dielectric 105 may be thermal oxidation. The temperature of the thermal oxidation is, for example, 950 to 1200 degrees Celsius. The exposed silicon material of the semiconductor substrate 101 and the shield conductor 104 forms silicon oxide during the thermal oxidation process. In the thermal oxidation step, the surface of the semiconductor substrate 101 is also exposed to the atmosphere. The gate dielectric 105 covers not only the upper sidewall of the trench 102, but also the surface of the semiconductor substrate 101.

Compared with the dense semiconductor substrate 101, the shield conductor 104 is a heavily doped amorphous or polycrystalline material with a looser structure and a higher doping concentration. As a result, the thickness of the second portion of the gate dielectric 105 located on the surface of the shield conductor 104 is greater than the thickness of the first portion located on the surface of the semiconductor substrate 101 and in the trench 102. The thickness of the first portion of the gate dielectric 105 is, for example, 50 to 5000 angstroms, and the thickness of the second portion is, for example, 60 to 10000 angstroms.

In step S106 , a gate conductor 106 is formed in the trenches of the first region 201 and the second region 202 , and a body region 107 and a source region 108 are formed in the region of the semiconductor substrate 101 adjacent to the trench 102 , as shown in FIG. 3 f .

The gate conductor 106 is composed of, for example, doped amorphous silicon or polysilicon. The process for forming the gate conductor 106 includes, for example, depositing polysilicon by sputtering or other processes, so that the polysilicon fills the opening at the top of the shield conductor 104 .

The deposition rate of the polysilicon is, for example, 1 to 100 angstroms per minute, the deposition temperature is, for example, 510 to 650 degrees Celsius, and the thickness is, for example, 1000 to 100000 angstroms. By controlling the doping concentration of the gate conductor 106, its resistance can be adjusted. In this embodiment, the square resistance Rs of the gate conductor 106 is, for example, less than 20 ohms. Further, the smaller the square resistance Rs of the gate conductor 106, the greater the thickness of the oxide layer formed in the subsequent oxidation process compared with silicon. Further, the material of the gate conductor 106 is selected to be amorphous, and it is easier to form a lower square resistance Rs.

In the above-mentioned deposition step, the material for forming the gate conductor 106 may be deposited once or multiple times. In multiple depositions, the rate of the subsequent deposition step is lower than that of the previous deposition step, so that the deposition rate gradually decreases. In the process of trench filling, the slower the deposition rate, the better the filling effect. The bottom of the trench is harder to fill than the top of the trench. Therefore, in multiple fillings, the rate of the previous deposition needs to be lower than the rate of any subsequent deposition.

The polysilicon includes a first portion located in the trenches of the first region 201 and the second region 202 , and a second portion extending laterally on the surface of the semiconductor substrate 101 .

Next, in the first region 201 and the second region 202, the second portion of the polysilicon extending laterally above the surface of the semiconductor substrate 101 is etched away, so that the polysilicon only fills the opening 124 at the upper portion of the trench 102 in the first region and the second region of the semiconductor substrate 101, thereby forming the gate conductor 106. In the third region 203, the polysilicon located on the surface of the shielding wiring 131 can be completely removed. Further, the second portion of the shielding wiring 131 may also be partially etched and reduced in thickness. However, the second portion of the shielding wiring 131 will be used for rewiring, and therefore, the second portion of the shielding wiring 131 can be retained by controlling the etching time.

Next, a P-type body region 107 is formed in the semiconductor substrate 101, and an N-type source region is formed in the body region 107. The process for forming the body region 107 and the source region 108 is, for example, multiple ion implantations. Different types of doping regions are formed by selecting appropriate dopants, and then thermal annealing is performed to activate the impurities. In the ion implantation, the gate conductor 106 and the shielding wiring 131 are used as hard masks to define the lateral positions of the body region 107 and the source region 108, thereby eliminating the need for a photoresist mask. The angle of the ion implantation is, for example, zero angle, i.e., vertical implantation relative to the surface of the semiconductor substrate 101. By controlling the energy of the ion implantation, the implantation depth of the body region 107 and the source region 108 can be defined, thereby defining the vertical position.

When forming the body region 107, the dopant used is B11 or BF2, or B11 may be injected first and then BF2, the injection energy is 20 to 100 Kev, the injection dose is 1E14 to 1E16, and the thermal annealing temperature is 500 to 1000 degrees Celsius. When forming the source region 108, the dopant used is P+ or AS+, the injection energy is 60 to 150 Kev, the injection dose is 1E14 to 1E16, and the thermal annealing temperature is 800 to 1100 degrees Celsius.

In this step, an SGT structure is formed in the trench 102 of the first region 201 and the second region 202, including a shield conductor 104 and a gate conductor 106 located in the trench. The gate conductor 106 includes a first portion located in the trench 102 and a second portion extending above the semiconductor substrate 101. The first portion of the gate conductor 106 is formed in the openings 124 on both sides of the shield conductor 104, so that the shield conductor 104 is sandwiched in the middle. The shield conductor 104 and the gate conductor 106 are isolated from each other by the second insulating layer 123. The lower portion of the shield conductor 104 extends to the lower portion of the trench 102, and is isolated from the semiconductor substrate 101 by an insulating stack, which includes a first insulating layer 122 and a second insulating layer 123. The gate conductor 106 is adjacent to the body region 107 and the source region 108, and is isolated from each other by the gate dielectric 105.

In step S107, an interlayer dielectric layer 109 is deposited on the surface of the semiconductor structure, as shown in FIG. 3g.

The interlayer dielectric layer 109 covers the first region and the second region of the semiconductor substrate 101. The interlayer dielectric layer 109 may be composed of at least one selected from silicon dioxide, silicon nitride, and silicon oxynitride, and may be a single layer or a stacked layer structure. In this embodiment, the interlayer dielectric layer 109 may be, for example, borophosphosilicate glass (BPSG) having a thickness of 2000 to 15000 angstroms.

In step S108, a plurality of contact holes 125 reaching the source region 108, the gate conductor 106 and the shielding wiring 131 are formed in the interlayer dielectric layer 109, and contact regions 110 are respectively formed at the bottom of the plurality of contact holes 125 by ion implantation, as shown in FIG. 3h.

The process used to form the contact hole 125 is, for example, dry etching. The sidewalls of the contact hole 125 are inclined, for example, at an angle of 85 to 89.9 degrees relative to the top of the vertical trench 102, so that the bottom width of the contact hole 125 is smaller than the top width. The angle of the contact hole 125 is relatively inclined, which is conducive to the subsequent filling of the conductive material and reduces the defects caused by the filling gap.

In the first region 201 of the semiconductor substrate 101, a first group of contact holes in the plurality of contact holes 125 sequentially penetrates the interlayer dielectric layer 109 and the gate dielectric 105, and extends to a predetermined depth in the shielding wiring 131, and a second group of contact holes sequentially penetrates the interlayer dielectric layer 109, the gate dielectric 105, and the source region 108 to reach a predetermined depth in the body region 107. The predetermined depth is, for example, 0.1 to 1 micrometer.

In the second region 202 of the semiconductor substrate 101 , a second group of contact holes in the plurality of contact holes 125 sequentially penetrates the interlayer dielectric layer 109 and extends to a predetermined depth in the gate conductor 106 .

In the third region 203 of the semiconductor substrate 101 , a third group of contact holes among the plurality of contact holes 125 penetrates the interlayer dielectric layer 109 and extends to a predetermined depth in the shielding wiring 131 .

In the ion implantation, the interlayer dielectric layer is used as a hard mask to define the lateral position of the contact area 110, so that the photoresist mask can be omitted. The dopant used in the ion implantation is B11 or BF2, or B11 is first implanted and then BF2 is implanted. The implantation energy is 20 to 100 KeV, the implantation dose is 1E14 to 1E16, and the thermal annealing temperature is 500 to 1000 degrees Celsius. After the ion implantation, thermal annealing can be performed to activate the dopant.

In step S109 , a source electrode 111 , a gate electrode 112 and a shielding electrode 113 are formed, as shown in FIG. 3 i .

This step includes, for example, depositing a metal layer and patterning. The metal layer is, for example, composed of one selected from Ti, TiN, TiSi, W, Al, AlSi, AlSiCu, Cu, Ni or an alloy thereof. The metal layer is patterned into a source electrode 111, a gate electrode 112 and a shield electrode 113 by etching. As shown in the figure, the source electrode 111, the gate electrode 112 and the shield electrode 113 are isolated from each other.

In the first region 201 of the semiconductor substrate 101 , the source electrode 111 reaches the source region 108 via a first group of contact holes among the plurality of contact holes 125 .

In the second region 202 of the semiconductor substrate 101 , the gate electrode 112 reaches the gate conductor 106 via a second group of contact holes among the plurality of contact holes 125 .

In the third region 203 of the semiconductor substrate 101 , the shield electrode 113 reaches the shield wiring 131 via a third group of contact holes among the plurality of contact holes 125 .

After step S109, the metallization of the power semiconductor device has been achieved. Furthermore, according to the needs of the product, a passivation layer protection can be added to complete the processing of the front structure of the power semiconductor device. After a series of post-processes such as thinning, back gold, and dicing, the device is finally realized.

It should be noted that although in the above cross-sectional view, the shielding conductors 104 and shielding wirings 131 in different grooves are isolated from each other, and the gate conductors 106 are isolated from each other, in an actual power semiconductor device, from the perspective of the planar structure, the shielding conductors 104 and shielding wirings 131 in the above different grooves can be connected to each other, and the gate conductors 106 can also be connected to each other. In one embodiment, the connection method is, for example, that the gate conductors 106 in different grooves 102 are formed as a whole by a single conductive layer, and the shielding conductors 104 and shielding wirings 131 in different grooves 102 are formed as a whole by a single conductive layer. In an alternative embodiment, the connection method is, for example, that the shielding conductors 104 and shielding wirings 131 in different grooves 102 are connected to each other using a common shielding electrode 113, and that the gate conductors 106 in different grooves 102 are connected to each other using a common gate electrode 112.

In this embodiment, the shielding wiring 131 includes not only a first portion filling the groove 102, but also a second portion extending laterally from the groove 102 on the surface of the semiconductor substrate 101. The second portion serves as a wiring layer. This is mainly due to the limited width of the groove of the power semiconductor device. After the shielding conductor 104 in the groove forms the contact holes, the contact holes in the first region 201 and the second region 102 of the semiconductor substrate 101 are dense. In order to improve the electrical isolation between the source region 108, the shielding conductor 104 and the gate conductor 106, the second portion of the shielding wiring 131 is used as the wiring layer, and the contact holes can be far away from each other, thereby reducing the process difficulty and improving the reliability of the power semiconductor device.

It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims (16)

1. A method of manufacturing a power semiconductor device, comprising:

Forming a plurality of trenches in a semiconductor substrate of a first doping type, the plurality of trenches including first to third trenches located in first to third regions of the semiconductor substrate, respectively;

Forming an insulating stack on sidewalls and bottoms of the first and second trenches and on sidewalls, bottoms and outer surfaces of the third trench, wherein the insulating stack comprises a first insulating layer and a second insulating layer, the first insulating layer surrounding the second insulating layer;

Forming a shielding conductor at the lower parts of the first groove and the second groove by adopting the same conductor layer, and filling shielding wiring in the third groove;

forming openings in upper portions of the first and second trenches;

forming a gate dielectric and a gate conductor in openings of the first trench and the second trench, the shield conductor, the gate conductor, and a second insulating layer sandwiched therebetween forming a split gate structure;

Forming a body region of a second doping type in a region of the semiconductor substrate adjacent to the trench, the second doping type being opposite to the first doping type;

Forming a source region of the first doping type in the body region; and

Forming a source electrode, a gate electrode and a shield electrode electrically connected to the source region, the gate conductor and the shield wiring, respectively,

Wherein the shield wiring includes a first portion filling the third trench and a second portion extending laterally on the surface of the semiconductor substrate, the second portion serving as a wiring layer spaced apart from the semiconductor substrate by the insulating stack, the shield electrode is led out through the wiring layer, the insulating stack has a thickness thicker than the gate dielectric,

The wiring layer extends laterally such that the contact hole of the gate electrode is distant from the contact hole of the source electrode, and in the step of forming a source region, the wiring layer serves as a hard mask such that a source region is not formed in the semiconductor substrate under the wiring layer,

The shield conductor and the semiconductor substrate are isolated from each other by the insulating stack.

2. The method of manufacturing of claim 1, wherein forming a gate dielectric and a gate conductor in openings of the first trench and the second trench comprises:

removing a portion of the first insulating layer at upper portions of the first trench and the second trench;

forming a gate dielectric on upper sidewalls of the first trench and the second trench; and

The gate conductor is formed to fill the opening,

Wherein the gate conductor and the shield conductor are isolated from each other by the gate dielectric, and the gate conductor and the body region are isolated from each other by the gate dielectric.

3. The manufacturing method according to claim 1, wherein the source electrode is located in the first region, the gate electrode is located in the second region, the shield electrode is located in the third region, and the first region, the second region, and the third region are spaced apart from each other.

4. The manufacturing method according to claim 1, wherein the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride, or polysilicon.

5. The manufacturing method according to claim 1, wherein a thickness of the first insulating layer is in a range of 500 to 50000 angstroms and a thickness of the second insulating layer is in a range of 50 to 5000 angstroms.

6. The method of manufacturing of claim 1, wherein the first doping type is one of N-type and P-type and the second doping type is the other of N-type and P-type.

7. The manufacturing method of claim 1, wherein sidewalls of the plurality of trenches are sloped such that a top width of the plurality of trenches is greater than a bottom width of the plurality of trenches.

8. The manufacturing method according to claim 1, wherein the step of forming the shield conductor, the step of forming the shield wiring, and the step of forming the gate conductor each include at least one deposition.

9. A power semiconductor device, comprising:

a plurality of trenches in a semiconductor substrate, the semiconductor substrate being of a first doping type, the plurality of trenches comprising first to third trenches in first to third regions of the semiconductor substrate, respectively;

An insulating stack on the first trench and the second trench lower sidewalls and bottom, and on the third trench sidewalls, bottom, and outer semiconductor substrate surface, the insulating stack comprising a first insulating layer and a second insulating layer, the first insulating layer surrounding the second insulating layer;

A shield conductor located at a lower portion of the first trench and the second trench, and a shield wiring filling the third trench, the shield conductor and the shield wiring being formed of the same conductor layer;

a gate dielectric and a gate conductor located at upper portions of the first trench and the second trench, the shield conductor, the gate conductor, and a second insulating layer sandwiched therebetween forming a split gate structure;

a body region in the semiconductor substrate, the body region being adjacent to an upper portion of the first trench and being of a second doping type, the second doping type being opposite to the first doping type;

the source region is positioned in the body region and is of the first doping type; and

A source electrode, a gate electrode, and a shield electrode electrically connected to the source region, the gate conductor, and the shield wiring, respectively,

Wherein the shield wiring includes a first portion filling the third trench and a second portion extending laterally on the surface of the semiconductor substrate, the second portion serving as a wiring layer spaced apart from the semiconductor substrate by the insulating stack, the shield electrode is led out through the wiring layer, the insulating stack has a thickness thicker than the gate dielectric,

The wiring layer extends laterally such that the contact hole of the gate electrode is distant from the contact hole of the source electrode, and in the step of forming a source region, the wiring layer serves as a hard mask such that a source region is not formed in the semiconductor substrate under the wiring layer,

The shield conductor and the semiconductor substrate are isolated from each other by the insulating stack.

10. The power semiconductor device of claim 9 wherein said gate dielectric is located on upper sidewalls of said first trench and said second trench,

Wherein the gate conductor and the shield conductor are isolated from each other by the gate dielectric, and the gate conductor and the body region are isolated from each other by the gate dielectric.

11. The power semiconductor device of claim 9 wherein the source electrode is located in the first region, the gate electrode is located in the second region, the shield electrode is located in the third region, and the first region, the second region, and the third region are spaced apart from one another.

12. The power semiconductor device according to claim 9, wherein the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride, or polysilicon.

13. The power semiconductor device of claim 9 wherein the first insulating layer has a thickness in the range of 500 to 50000 angstroms and the second insulating layer has a thickness in the range of 50 to 5000 angstroms.

14. The power semiconductor device of claim 9 wherein the first doping type is one of N-type and P-type and the second doping type is the other of N-type and P-type.

15. The power semiconductor device of claim 9 wherein sidewalls of the plurality of trenches are sloped such that a top width of the plurality of trenches is greater than a bottom width of the plurality of trenches.

16. The power semiconductor device of claim 9, wherein the power semiconductor device is one selected from the group consisting of a CMOS device, a BCD device, a MOSFET transistor, an IGBT, and a schottky diode.