CN107957541B - A method and system for screening parallel chips inside a power semiconductor module - Google Patents

Abstract

The invention discloses a method and system for screening parallel chips inside a power semiconductor module. The method includes: obtaining transfer characteristic curves of a plurality of chips; discretizing each transfer characteristic curve, obtaining a plurality of discrete points of the transfer characteristic curve to form a chip discrete point set; obtaining chips of any two chips among the plurality of chips Discrete point set; calculate several relative phase difference values of the two chips, the relative phase difference value is the relative phase difference value of the drain current or the relative phase difference value of the gate-source voltage; calculate the average relative phase difference value of the two chips, and the average relative phase difference value is the relative phase difference value of the two chips The average value of several relative phase difference values; comparing all the average relative phase difference values in multiple chips to determine the minimum average relative phase difference value; determining the two chips corresponding to the minimum average relative phase difference value as the target screening chip. The present invention can obtain two parallel-connected chips with small dispersion of threshold voltage and transconductance coefficient, so that the transient current sharing effect of the parallel-connected chips is better.

Description

A method and system for screening parallel chips inside a power semiconductor module

technical field

The invention relates to the technical field of parallel connection of power semiconductors, in particular to a method and system for screening parallel chips inside a power semiconductor module.

Background technique

In recent years, with the acceleration of the commercialization of silicon carbide power semiconductor devices, the good market prospects have promoted the continuous development of technology. Compared with the silicon preparation process that has been accumulated for decades, silicon carbide power devices still have many shortcomings in terms of current level, reliability and cost. The ever-increasing demand for high-power applications and the physical limitations of the current density of existing silicon carbide devices have forced equipment developers to use parallel connection of devices as an alternative solution. However, even in the case of completely symmetrical circuit layout, due to the unavoidable differences in chip parameters during the fabrication process, there will be unbalanced current distribution among parallel units, which brings great challenges to the parallel application of SiC chips. challenge.

During the chip preparation process, due to differences in the manufacturing process, environment, and personnel or equipment operations, the parameters of different chips will be inconsistent. Similar to the concept of electronic component tolerance, chip parameter dispersion refers to the characteristic that the characteristic parameters of different devices are not consistent, but distributed within a certain range. For mature silicon-based devices, after years of development, the existing process technology is still difficult to ensure that the device parameters are completely consistent, and for the silicon carbide device technology that is still immature, the dispersion of device parameters will be greater. Therefore, before parallel packaging, the screening of chip parameters is particularly important.

At present, the screening of chips usually adopts the classification method. For example, in 1993, Ch. Keller of Germany's AEG Company pointed out that chip manufacturers usually provide different levels of insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) chips, and the conduction voltage drop dispersion of these chips generally does not exceed 0.5V , so that the unbalance of the on-state current can be controlled between 10%-20%; in 1995, D. Medaule of Mitsubishi Corporation of Japan proposed to divide and screen the conduction voltage drop of all IGBT chips prepared for parallel connection, The conduction voltage drop range of each level is 0.25V or 0.3V, and it is pointed out that when the chips of the same level are used for parallel connection, the parallel current imbalance of the chips can be guaranteed within 15%; Takeharu Koga of Fuji Electric Company in 1998 In the research on the robustness and reliability of the 2.5kV/1.8kA press-connect IGBT module, it is pointed out that in addition to screening the conduction voltage drop of the IGBT chip, it is also necessary to check the dynamic parameters of the chip such as turn-off The storage time and fall time are screened, and the screening indicators such as the difference of the conduction voltage drop not exceeding ±0.1V and the difference of the storage time not exceeding ±5% are given; in the 2014 Fuji Electric Technical Manual, the company's Super FAP series Taking MOSFET as an example, the threshold voltage screening standard has been formulated, and the threshold voltage of all batches of products is classified according to different grades. For logic series devices, the grades are divided by 0.35V, and for power device series, 0.4V is used as a class. Division level.

The existing method of chip screening is to collect a certain parameter of the chip, such as conduction voltage drop or threshold voltage, and then classify according to the collected parameters. This method can only be roughly screened, and the screened parallel The chip's transient current sharing effect is not good, and although theoretically, the number of screening parameters can be appropriately increased to improve the transient current sharing effect of the screened parallel chips, but in fact, as the number of screening parameters increases, according to The device labels screened out by the intervals divided by different parameters may be different. The intersection of these intervals will be very small, and it is difficult to take into account multiple parameters at the same time. Therefore, the existing chip screening method can only realize rough screening of parallel chips, and the transient current sharing effect of the screened parallel chips is not good.

Contents of the invention

Based on this, it is necessary to provide a method and system for screening parallel chips inside a power semiconductor module, so as to realize accurate screening of parallel chips and improve the transient current sharing effect of the screened parallel chips.

To achieve the above object, the present invention provides the following scheme:

A method for screening parallel-connected chips inside a power semiconductor module, comprising:

Acquiring transfer characteristic curves of a plurality of chips, the transfer characteristic curve is a curve of the relationship between the gate-source voltage and the drain current of each chip during the turn-on process;

discretize each of the transfer characteristic curves, and obtain a plurality of discrete points of the transfer characteristic curve to form a chip discrete point set;

Obtaining the chip discrete point sets of any two chips among the plurality of chips;

Calculate several relative phase difference values of the two chips, the relative phase difference value is the relative phase difference value of the drain current or the relative phase difference value of the gate-source voltage; the relative phase difference value of the drain current is that the discrete points of the two chips are concentrated at The relative phase difference value of the drain current at the discrete point under the same gate-source voltage; the relative phase difference value of the gate-source voltage is the gate-source value of the discrete point at which the discrete points of the two chips are concentrated under the same drain current The relative phase difference of the voltage;

Calculate the average relative phase difference value of the two chips, the average relative phase difference value is the average value of several relative phase difference values of the two chips;

Comparing all the average relative phase difference values in a plurality of said chips to determine the minimum average relative phase difference value;

The two chips corresponding to the minimum average relative phase difference value are determined as target screening chips.

Optionally, the acquiring transfer characteristic curves of multiple chips specifically includes:

Obtain transfer characteristic measurements for each chip with a power analyzer;

Drawing transfer characteristic curves of a plurality of chips according to the transfer characteristic measurement value of each chip.

Optionally, discretizing each of the transfer characteristic curves to obtain a plurality of discrete points of the transfer characteristic curve to form a chip discrete point set specifically includes:

The transfer characteristic curve is processed by means of interpolation to obtain a plurality of discrete points of the transfer characteristic curve.

Optionally, the acquisition of the transfer characteristic measurement value of each chip through a power analyzer specifically includes:

Obtaining a fixed step size, the fixed step size is within a preset range;

The transfer characteristic measurement value of each chip is obtained according to the fixed step size.

The present invention also provides a screening system for parallel chips inside a power semiconductor module, including:

The first acquisition module is configured to acquire transfer characteristic curves of a plurality of chips, where the transfer characteristic curve is a curve of the relationship between the gate-source voltage and the drain current of each chip during the turn-on process;

a discrete module, configured to discretize each of the transfer characteristic curves, obtain a plurality of discrete points of the transfer characteristic curve, and form a chip discrete point set;

A second acquisition module, configured to acquire the chip discrete point sets of any two chips among the plurality of chips;

The first calculation module is used to calculate several relative phase difference values of the two chips, the relative phase difference value is the relative phase difference value of the drain current or the relative phase difference value of the gate-source voltage; the relative phase difference value of the drain current is two The relative phase difference value of the drain current of the discrete point of the discrete point of the chip concentrated under the same gate-source voltage; the relative phase difference value of the gate-source voltage of the two discrete points of the chip concentrated under the same drain current The relative phase difference value of the gate-source voltage at the discrete point of ;

The second calculation module is used to calculate the average relative phase difference value of the two chips, and the average relative phase difference value is the average value of several relative phase difference values of the two chips;

A comparison module, configured to compare all the average relative phase difference values in multiple chips, and determine the minimum average relative phase difference value;

The target chip determination module is configured to determine the two chips corresponding to the minimum average relative phase difference as target screening chips.

Optionally, the first acquisition module specifically includes:

a transfer characteristic measurement value acquisition unit, configured to obtain the transfer characteristic measurement value of each chip through a power analyzer;

The transfer characteristic curve acquisition unit is configured to draw transfer characteristic curves of a plurality of chips according to the transfer characteristic measurement value of each chip.

Optionally, the discrete module specifically includes:

The discrete point acquisition unit is configured to process the transfer characteristic curve by means of interpolation to obtain multiple discrete points of the transfer characteristic curve.

Optionally, the transfer characteristic measurement value acquisition unit specifically includes:

The step size obtaining subunit is used to obtain a fixed step size, and the fixed step size is within a preset range;

The transfer characteristic measurement value acquisition subunit is configured to obtain the transfer characteristic measurement value of each chip according to the fixed step size.

Compared with prior art, the beneficial effect of the present invention is:

The present invention proposes a method and system for screening parallel-connected chips inside a power semiconductor module. The method includes: obtaining transfer characteristic curves of multiple chips; discretizing each transfer characteristic curve to obtain multiple discrete points of the transfer characteristic curve, Constitute a chip discrete point set; obtain chip discrete point sets of any two chips in multiple chips; calculate several relative phase difference values of two chips; calculate the average relative phase difference value of two chips; compare all average relative phase difference values of multiple chips , determine the minimum average relative phase difference value; determine the two chips corresponding to the minimum average relative phase difference value as target screening chips. The present invention avoids the screening method of classifying according to a parameter, but screens by comparing the similarity of transfer characteristic curves of different chips, and reflects the two key points of chip threshold voltage and transconductance coefficient through the similarity of transfer characteristic curves. The dispersion of parameters, and using the relative phase difference value as a screening index, realizes the precise screening of chips, and improves the transient current sharing effect of the screened parallel chips. Among them, using the relative phase difference value as a screening index, the smaller the relative phase difference value, The higher the similarity of the transfer characteristic curves of the two chips is, the higher the dispersion of the threshold voltage and the dispersion of the transconductance coefficient of the two chips are. The difference is very small, and the dispersion of the transconductance coefficient is small, indicating that the rising speed of the conduction current is basically the same; the smaller the relative phase difference, the higher the similarity of the transfer characteristic curves of the two chips, and it can also indicate the transient state of the chips after they are connected in parallel. The current equalization effect is better.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some of the present invention. Embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without paying creative labor.

1 is a flowchart of a method for screening parallel chips inside a power semiconductor module according to an embodiment of the present invention;

Fig. 2 is the transfer characteristic curve of No. 1 chip and No. 2 chip of the embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a screening system for parallel chips inside a power semiconductor module according to an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

FIG. 1 is a flow chart of a method for screening parallel-connected chips inside a power semiconductor module according to an embodiment of the present invention.

Referring to Fig. 1, the method for screening parallel chips inside the power semiconductor module of the embodiment includes:

S1: Obtain transfer characteristic curves of a plurality of chips, where the transfer characteristic curve is a curve of a relationship between the gate-source voltage and the drain current of each chip during the turn-on process.

Specifically, the transfer characteristic curves of multiple chips are obtained through a power analyzer or other measurement equipment, including: obtaining a fixed step size, the fixed step size is within a preset range; obtaining the transfer characteristic curve of each chip according to the fixed step size Characteristic measurement values; drawing transfer characteristic curves of multiple chips according to the transfer characteristic measurement values of each chip.

S2: Discretize each of the transfer characteristic curves, and acquire a plurality of discrete points of the transfer characteristic curve to form a chip discrete point set.

Specifically, the transfer characteristic curve is processed in an interpolation manner to obtain multiple discrete points of the transfer characteristic curve.

S3: Obtain the chip discrete point sets of any two chips among the plurality of chips.

S4: Calculating several relative phase difference values of the two chips, the relative phase difference values being the relative phase difference values of the drain current or the relative phase difference values of the gate-source voltage.

Specifically, the relative phase difference value of the drain current is the relative phase difference value of the drain current at two discrete points of the chip at which the discrete points are concentrated under the same gate-source voltage; the relative phase difference value of the gate-source voltage is two The discrete points of the chip are concentrated in the relative phase difference of the gate-source voltage of the discrete points under the same drain current.

S5: Calculate an average relative phase difference value of the two chips, where the average relative phase difference value is an average value of several relative phase difference values of the two chips.

S6: Comparing all the average relative phase difference values in multiple chips, and determining the minimum average relative phase difference value.

S7: Determine the two chips corresponding to the minimum average relative phase difference as target screening chips.

In practical applications, the method for screening internal parallel chips of power semiconductor modules in the above embodiment can be used to screen chips numbered from 1 to 30 to obtain the required parallel chips, specifically:

The transfer characteristic curves of 30 chips are measured by a power analyzer or other measuring equipment. Each transfer characteristic curve is drawn from several transfer characteristic measurement values. The transfer characteristic measurement values are measured by the following steps: Obtain a fixed step long, the fixed step size is within a preset range; and the transfer characteristic measurement value of each chip is obtained according to the fixed step size.

The transfer characteristic curve is processed in an interpolation manner to obtain multiple discrete points of the transfer characteristic curve, the purpose of which is to obtain sufficient discrete points.

In this embodiment, a fixed step size of 1V is selected to obtain the transfer characteristic curves of No. 1 chip and No. 2 chip, and the transfer characteristic curves of No. 1 chip and No. 2 chip are respectively discretized by interpolation, so that each curve The number of discrete points is n.

Fig. 2 is the transfer characteristic curve of No. 1 chip and No. 2 chip of embodiment.

Referring to Fig. 2, curve _l1 is the transfer characteristic curve of No. 1 chip, and curve _l2 is the transfer characteristic curve of No. 2 chip. The abscissa of the transfer characteristic curve represents the gate-source voltage, and the ordinate represents the drain current. Under the gate-source voltage, for any pair of discrete points k(A, B), A represents the discrete point on the transfer characteristic curve of the No. 1 chip, and B represents the No. 2 chip under the same gate-source voltage as the No. 1 chip. The discrete points on the transfer characteristic curve of the chip, the coordinates of point A are (x,p _k ), and the coordinates of point B are (x,q _k ).

Calculate the relative phase difference of the drain current of No. 1 chip and No. 2 chip at the discrete point k(A, B), and the calculation formula is:

Calculate the relative phase difference of the drain current of all discrete points of No. 1 chip and No. 2 chip, and calculate the average value to obtain the average relative phase difference between No. 1 chip and No. 2 chip. The calculation formula is as follows:

The average relative phase difference between No. 1 chip and No. 2 chip As the screening index value of No. 1 chip and No. 2 chip.

Based on the transfer curve of No. 1 chip, use the above two formulas to calculate the average relative phase difference of each group of chips between No. 1 chip and No. 2 chip, No. 1 chip and No. 3 chip... No. 1 chip and No. 30 chip , to obtain several average relative phase difference values

All the comparisons between No. 1 chip and No. 2-30 chips have been completed above, and you only need to repeat the above steps to complete the comparison of the remaining chips. Taking No. 2 chip as the benchmark, calculate No. 2 chip and No. 3 chip, No. 2 chip and 4 chip No. chip... the average relative phase difference of each group between No. 2 chip and No. 30 chip. Similarly, the comparison of No. 3 chip, No. 4 chip and all chips can be completed.

Through the above calculation, the screening index values of any two chips can be obtained, as shown in the following table:

Compare the average relative phase difference values of any two chips among the 30 chips in the above table, and determine the two chips corresponding to the minimum average relative phase difference value as parallel chips.

The screening method for internal parallel chips of power semiconductor modules in the embodiment avoids the screening method of classifying according to a parameter, but screens by comparing the similarity of the transfer characteristic curves of different chips, and reflects the similarity of the transfer characteristic curves. The dispersion of the two key parameters of chip threshold voltage and transconductance coefficient, and using the relative phase difference value as the screening index, can realize the precise screening of chips and improve the transient current sharing effect of the screened parallel chips. Using the relative phase difference value as a screening index, the smaller the relative phase difference value, the higher the similarity of the transfer characteristic curves of the two chips, which in turn indicates that the dispersion of the threshold voltage and the transconductance coefficient of the two chips are very small, among which The small dispersion of the threshold voltage indicates that the difference in the turn-on time of the two chips is small, and the small dispersion of the transconductance coefficient indicates that the rising speed of the conduction current is basically the same; the smaller the relative phase difference, the better the transfer characteristic curve of the two chips. The higher the similarity, the better the transient current sharing effect after the chips are connected in parallel.

The present invention also provides a screening system for parallel chips inside a power semiconductor module, and FIG. 3 is a schematic structural diagram of the screening system for parallel chips inside a power semiconductor module according to an embodiment of the present invention.

Referring to Fig. 3, the chip screening system 30 of the embodiment includes:

The first acquiring module 301 is configured to acquire transfer characteristic curves of a plurality of chips, where the transfer characteristic curve is a curve of the relationship between the gate-source voltage and the drain current of each chip during the turn-on process.

Specifically, the first obtaining module 301 includes:

The transfer characteristic measurement value acquisition unit is used to obtain the transfer characteristic measurement value of each chip through the power analyzer, specifically including:

The step size obtaining subunit is used to obtain a fixed step size, and the fixed step size is within a preset range;

The transfer characteristic measurement value acquisition subunit is configured to obtain the transfer characteristic measurement value of each chip according to the fixed step size.

The transfer characteristic curve acquisition unit is configured to draw transfer characteristic curves of a plurality of chips according to the transfer characteristic measurement value of each chip.

The discretization module 302 is configured to discretize each of the transfer characteristic curves, obtain a plurality of discrete points of the transfer characteristic curves, and form a chip discrete point set.

Specifically, the discrete module 302 includes:

The discrete point acquisition unit is configured to process the transfer characteristic curve by means of interpolation to obtain multiple discrete points of the transfer characteristic curve.

The second obtaining module 303 is configured to obtain the chip discrete point sets of any two chips among the plurality of chips.

The first calculation module 304 is used to calculate several relative phase difference values of the two chips, the relative phase difference value is the relative phase difference value of the drain current or the relative phase difference value of the gate-source voltage; the relative phase difference value of the drain current is The relative phase difference value of the drain current at the discrete point of the discrete points of the two chips concentrated under the same gate-source voltage; the relative phase difference value of the gate-source voltage is concentrated at the same drain current The relative phase difference value of the gate-source voltage at the discrete point below.

The second calculation module 305 is configured to calculate an average relative phase difference value of the two chips, and the average relative phase difference value is an average value of several relative phase difference values of the two chips.

The comparison module 306 is configured to compare all the average relative phase difference values in multiple chips, and determine the minimum average relative phase difference value.

The target chip determination module 307 is configured to determine the two chips corresponding to the minimum average relative phase difference as target screening chips.

The internal parallel chip screening system of the power semiconductor module in this embodiment avoids the screening method of classifying according to a parameter, but screens by comparing the similarity of the transfer characteristic curves of different chips. To reflect the dispersion of the two key parameters of chip threshold voltage and transconductance coefficient, and use the relative phase difference value as the screening index, the precise screening of chips is realized, and the transient current sharing effect of the screened parallel chips is improved.

In this paper, specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; meanwhile, for those of ordinary skill in the art, according to the present invention Thoughts, there will be changes in specific implementation methods and application ranges. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims (8)

1. A method for screening parallel chips in a power semiconductor module is characterized by comprising the following steps:

obtaining transfer characteristic curves of a plurality of chips, wherein the transfer characteristic curves are curves of the change relation between the grid-source voltage and the drain current of each chip in the turn-on process;

discretizing each transfer characteristic curve to obtain a plurality of discrete points of the transfer characteristic curve to form a chip discrete point set;

obtaining the chip discrete point sets of any two chips in the plurality of chips;

calculating a plurality of relative phase difference values of the two chips, wherein the relative phase difference values are drain current relative phase difference values or gate-source voltage relative phase difference values; the relative phase difference value of the drain current is the relative phase difference value of the drain current of the discrete point of two chips under the condition that the discrete points are concentrated on the same grid-source voltage; the relative phase difference value of the grid-source voltages is the relative phase difference value of the grid-source voltages of the discrete points of the two chips under the condition that the discrete points are concentrated on the same drain current; the calculation formula of the relative phase difference value of the drain current is as follows:

wherein,for the relative phase difference value of drain current of the No. 1 chip and the No. 2 chip at the k-th pair of discrete points k (A, B), under the same grid-source voltage, for any pair of discrete points k (A, B), A represents a discrete point on the transfer characteristic curve of the No. 1 chip, B represents a discrete point on the transfer characteristic curve of the No. 2 chip at the same grid-source voltage with the No. 1 chip, and the coordinates of the point A are (x, p)_k) The coordinates of point B are (x, q)_k)；

Calculating an average relative phase difference value of the two chips, wherein the average relative phase difference value is an average value of a plurality of relative phase difference values of the two chips;

comparing all the average relative phase difference values in a plurality of the chips to determine a minimum average relative phase difference value;

and determining two chips corresponding to the minimum average relative phase difference value as target screening chips.

2. The method for screening chips connected in parallel inside a power semiconductor module according to claim 1, wherein the obtaining of transfer characteristic curves of a plurality of chips specifically comprises:

obtaining a transfer characteristic measured value of each chip through a power analyzer;

and drawing transfer characteristic curves of a plurality of chips according to the transfer characteristic measured value of each chip.

3. The method for screening chips connected in parallel inside a power semiconductor module according to claim 1, wherein the discretizing each transfer characteristic curve to obtain a plurality of discrete points of the transfer characteristic curve to form a chip discrete point set specifically comprises:

and processing the transfer characteristic curve in an interpolation mode to obtain a plurality of discrete points of the transfer characteristic curve.

4. The method for screening chips connected in parallel inside a power semiconductor module according to claim 2, wherein the obtaining of the transfer characteristic measurement value of each chip by the power analyzer specifically comprises:

obtaining a fixed step length, wherein the fixed step length is within a preset range;

and acquiring the transfer characteristic measurement value of each chip according to the fixed step length.

5. A power semiconductor module internal parallel chip screening system is characterized by comprising:

the first acquisition module is used for acquiring transfer characteristic curves of a plurality of chips, wherein the transfer characteristic curves are curves of the change relation between the grid-source voltage and the drain current of each chip in the turn-on process;

the discrete module is used for discretizing each transfer characteristic curve to obtain a plurality of discrete points of the transfer characteristic curve to form a chip discrete point set;

a second obtaining module, configured to obtain the chip discrete point sets of any two chips in the plurality of chips;

the first calculation module is used for calculating a plurality of relative phase difference values of the two chips, wherein the relative phase difference values are drain current relative phase difference values or gate-source voltage relative phase difference values; the relative phase difference value of the drain current is the relative phase difference value of the drain current of the discrete point of two chips under the condition that the discrete points are concentrated on the same grid-source voltage; the relative phase difference value of the grid-source voltages is the relative phase difference value of the grid-source voltages of the discrete points of the two chips under the condition that the discrete points are concentrated on the same drain current; the calculation formula of the relative phase difference value of the drain current is as follows:

wherein,for the relative phase difference value of drain current of the No. 1 chip and the No. 2 chip at the k-th pair of discrete points k (A, B), under the same grid-source voltage, for any pair of discrete points k (A, B), A represents a discrete point on the transfer characteristic curve of the No. 1 chip, B represents a discrete point on the transfer characteristic curve of the No. 2 chip at the same grid-source voltage with the No. 1 chip, and the coordinates of the point A are (x, p)_k) The coordinates of point B are (x, q)_k)；

The second calculation module is used for calculating an average relative phase difference value of the two chips, wherein the average relative phase difference value is an average value of a plurality of relative phase difference values of the two chips;

a comparison module for comparing all the average relative phase difference values in the plurality of chips to determine a minimum average relative phase difference value;

and the target chip determining module is used for determining two chips corresponding to the minimum average relative phase difference value as target screening chips.

6. The system for screening chips connected in parallel inside a power semiconductor module according to claim 5, wherein the first obtaining module specifically comprises:

a transfer characteristic measurement value acquisition unit for acquiring a transfer characteristic measurement value of each chip by a power analyzer;

and the transfer characteristic curve acquisition unit is used for drawing transfer characteristic curves of a plurality of chips according to the transfer characteristic measured value of each chip.

7. The system for screening chips connected in parallel inside a power semiconductor module according to claim 5, wherein the discrete module specifically comprises:

and the discrete point acquisition unit is used for processing the transfer characteristic curve in an interpolation mode to acquire a plurality of discrete points of the transfer characteristic curve.

8. The system for screening chips connected in parallel inside a power semiconductor module according to claim 6, wherein the transfer characteristic measurement value obtaining unit specifically comprises:

the step length obtaining subunit is used for obtaining a fixed step length, and the fixed step length is within a preset range;

and the transfer characteristic measurement value acquisition subunit is used for acquiring the transfer characteristic measurement value of each chip according to the fixed step length.