CN107958689B - Operation method of memory array - Google Patents

Abstract

The memory array includes a first memory cell, a second memory cell, and a third memory cell, which share a gate and are sequentially arranged along the extension direction of the gate. The memory array operation method includes the following steps. A first bias voltage is provided to a channel of the first memory cell to program the first memory cell. A second bias voltage is provided to a channel of the second memory cell to prohibit programming of the second memory cell. A third bias voltage is provided to a channel of the third memory cell to program or prohibit programming of the third memory cell. The first bias voltage and the third bias voltage are different.

Description

How to operate a memory array

technical field

The present invention relates to a method of operating a memory array, and more particularly, to a method of operating a NAND flash memory.

Background technique

As the critical dimensions of components in integrated circuits shrink to the limits of what the process technology can perceive, designers have begun to search for technologies that can achieve greater memory densities, thereby achieving lower costs per bit. Technologies currently under attention include NAND memory and its operation. However, the states of adjacent memory cells can be affected by mutual disturbance. The problem is exacerbated, especially as the trend is toward shrinking the size and pitch of memory cells.

SUMMARY OF THE INVENTION

The present invention relates to a method of operating a memory array.

According to an aspect of the present invention, a method of operating a memory array is provided. The memory array includes a first memory unit, a second memory unit and a third memory unit, which share a gate and are sequentially arranged along the extending direction of the gate. A method of operating a memory array includes the following steps. A first bias voltage is provided to a channel of the first memory cell to program the first memory cell. A second bias is provided to a channel of the second memory cell to inhibit programming of the second memory cell. A third bias voltage is provided to a channel of the third memory cell to program or inhibit programming of the third memory cell. The first bias voltage is not the same as the third bias voltage.

According to another aspect of the present invention, a method for operating a memory array is provided, which includes the following steps. A first bit line bias is provided to bring a first memory cell of a first memory string to a programmed state. A second bit line bias is provided to make a second memory cell of a second memory string a program-inhibited state. A third bit line bias is provided to place a third memory cell of a third memory string in a program state or a program inhibit state. The first bit line bias is different from the third bit line bias. The first storage unit, the second storage unit and the third storage unit are sequentially arranged on a page of the memory array.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are given below, and are described in detail as follows in conjunction with the accompanying drawings:

Description of drawings

Figure 1 shows a memory array according to an embodiment.

FIG. 2 shows a partial structure of a memory array according to an embodiment.

Figure 3 illustrates a method of operation according to an embodiment.

Figure 4 illustrates a method of operation according to an embodiment.

Figure 5 illustrates a method of operation according to an embodiment.

Figure 6 illustrates a method of operation according to an embodiment.

FIG. 7 shows an operation method according to a comparative example.

Description of reference numbers:

102, 104, 106, 108, 110, 112: bit lines

222, 224, 226, 228, 330, 350: Gate

352: Source

404, 406, 408, 410, 412: storage units

504, 506, 508, 510, 512: floating gate

P, P': programming state

I: Program disabled state.

Detailed ways

Embodiments of the present invention provide an operation method of a memory array, which can improve the properties of the device.

It should be noted that the present invention does not show all possible embodiments, and other embodiments not proposed in the present invention may also be applicable. Furthermore, the size ratios in the drawings are not drawn according to the actual product scale. Therefore, the contents of the description and the drawings are only used to describe the embodiments, rather than to limit the protection scope of the present invention. In addition, the descriptions in the embodiments, such as detailed structures, process steps, and material applications, etc., are merely illustrative, and do not limit the scope of protection of the present invention. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present invention. In the following, the same/similar symbols are used to represent the same/similar elements for description.

In an embodiment, having one of the two memory cells on the opposite side of the program-inhibited memory cell on the same page (eg, a gate or word line extension direction) have a higher channel bias, which can help improve the The channel bit energy of the program-inhibited memory cell is activated, so that the program-inhibited state can be stabilized. For example, one of the two memory cells on the opposite side of a program-inhibited memory cell is made to be in the program-inhibited state, while the other memory cell is in the programmed state. Alternatively, two memory cells on opposite sides of a program-inhibited memory cell are brought into a programmed state with different channel/bit line biases, one being greater than the other.

Some embodiments are exemplified below to illustrate the operation method of the memory array according to the present invention. In order to provide a clear understanding of the present invention, elements in the following description are named according to the block in which the method of operation is discussed, the applied bias voltage, and/or the state of the memory cell. For example, the bias voltage V1 may also be referred to as the first bias voltage or the first bit line bias voltage, and the memory cell corresponding to the bias voltage V1 may also be referred to as the first memory cell or the first memory cell corresponding to the first memory string. storage unit. And so on.

Figure 1 shows a memory array according to an embodiment. For example, several NAND strings correspond to different bit lines (or channels) 102, 104, 106, 108, 110, 112, and memory cells (eg, 404, 406, 408, 410, 412, etc.) are defined in bits Between lines 102 , 104 , 106 , 108 , 110 , 112 and gates 222 , 224 , 226 , 228 . String select transistors corresponding to the gates 330 and 350 may be coupled to both sides of the memory cell string group of the NAND string. An end of the NAND string relative to the bit lines 102 , 104 , 106 , 108 , 110 , 112 may be coupled to the source electrode 352 .

FIG. 2 shows portions of memory cells 404 , 406 , 408 , 410 , and 412 in the memory array of FIG. 1 , which are located on the same page, share the gate 224 and are arranged along the extending direction of the gate 224 . Memory cells 404 , 406 , 408 , 410 , 412 are defined at the intersections of gate 224 and bit lines 104 , 106 , 108 , 110 , 112 . The memory array may include a dielectric (eg, a memory film, not shown) disposed between gate 224 , bit lines 104 , 106 , 108 , 110 , 112 and floating gates 504 , 506 , 508 , 510 , 512 . The dielectric (or memory film) may include suitable materials such as silicon oxide and silicon nitride, for example, memory structures such as ONO, ONONO, and the like.

FIG. 7 shows the operation method of a comparative example. The memory cells 404 and 408 are in the programmed state P by the bias voltage (0V) of the bit line/channel. Memory cell 406 in program inhibit state I with bit line/channel bias (3.3V) is affected by memory cell 404 and memory cell 408 in program state P on both sides with low bias 0V, The boost of channel potential is reduced, as shown in the figure, and the depth of the ground-biased equal-potential line becomes shallower, which compresses the depletion depth. And increase the electric field, which increases the leakage current and reduces the raised channel potential, so the forbidden condition becomes unstable. The parasitic capacitance between the bit lines also reduces the bit energy lift rate.

Referring to FIG. 3, in a method of operation according to an embodiment, the (first) memory cell 404 is provided by a bias voltage ( The first bias voltage or first bit line bias voltage) V1 is programmed and is in the program state P. The (second) memory cell 406 is activated by a bias (second bias or second bit line bias) V2 supplied to the bit line 106 (corresponding to the channel or second bit line of the second memory string) Program prohibited, in program prohibited state I. (Third) memory cell 408 is provided with a bias voltage (third bias voltage or third bit line bias voltage) different from bias voltage V1 by providing to bit line 108 (corresponding to the channel or third bit line of the third memory string) It is programmed by pressing) V3, and it is in the programming state P'. In one embodiment, for example, the bias voltage V2 is greater than the bias voltage V1 and the bias voltage V3, and the bias voltage V3 is greater than the bias voltage V1. The bias voltage V1 can be a positive voltage or 0V. In one embodiment, for example, the bias voltage V1 is 0V, the bias voltage V2 is Vcc, such as 3.3V, and the bias voltage V3 is 1V. In the memory cell 408 in the programmed state P', the bias voltage V3 higher than the bias voltage V1 makes the potential energy line depth of the ground bias voltage of the adjacent memory cell 406 deeper, thereby raising the channel potential energy of the memory cell 406, and the energy compared to the comparison example has a more stable program-disabled state.

Referring to FIG. 4 , in a method of operation according to an embodiment, the memory cell 404 is in a programmed state P. Memory cell 406 is in program inhibit state I. Memory cell 408 is in program inhibit state I. In one embodiment, for example, the bias voltage V2 used to program inhibit memory cells 406 is equal to the bias voltage V3 used to program memory cells 408 and is greater than the bias voltage V1 used to program memory cells 404 . The bias voltage V1 can be a positive voltage or 0V. In an embodiment, for example, the bias voltage V1 is 0V, and the bias voltage V2 and the bias voltage V3 are Vcc, such as 3.3V. In the memory cell 408 in the program-inhibited state I, the bias voltage V3 higher than the bias voltage V1 makes the potential energy line depth of the ground bias voltage of the adjacent memory cell 406 deeper, thereby raising the channel potential energy of the memory cell 406, and the energy compared to the comparison example has a more stable program-disabled state.

Referring to FIG. 5, in a method of operation according to an embodiment, the (first) memory cell 406 is provided by a bias voltage V1 to the bit line 106 (corresponding to the channel or first bit line of the first memory string) (first bias or first bit line bias) to be programmed, in the programmed state P. The (second) memory cell 408 is biased by a bias voltage V2 (second bias or second bit line bias) supplied to the bit line 108 (corresponding to the channel or second bit line of the second memory string). Program prohibited, in program prohibited state I. The (third) memory cell 410 is provided with a bias voltage (the third bias voltage or the third bit line bias voltage) different from the bias voltage V1 by supplying to the bit line 110 (corresponding to the channel or the third bit line of the third memory string) It is programmed by pressing) V3, and it is in the programming state P'. In one embodiment, for example, the bias voltage V2 is greater than the bias voltage V1 and the bias voltage V3, and the bias voltage V3 is greater than the bias voltage V1. The bias voltage V1 can be a positive voltage or 0V. In one embodiment, for example, the bias voltage V1 is 0V, the bias voltage V2 is Vcc, such as 3.3V, and the bias voltage V3 is 1V. In the memory cell 410 in the programming state P', the bias voltage V3 higher than the bias voltage V1 makes the potential energy line depth of the ground bias voltage of the adjacent memory cell 408 deeper, thereby raising the channel potential energy of the memory cell 408, and the energy compared to the comparison The example (memory cell 406 of Figure 7) has a more stable program inhibit state.

Referring to FIG. 6, in a method of operation according to an embodiment, the (first) memory cell 410 is in a programmed state P'. The (second) memory cell 408 is in the program-inhibited state I. (Third) The memory cell 406 is in the program-inhibited state I. In one embodiment, for example, the bias voltage V2 used to inhibit programming of memory cells 408 is equal to the bias voltage V3 used to program memory cells 406 and greater than the bias voltage V1 used to program memory cells 410 . The bias voltage V1 can be a positive voltage or 0V. In an embodiment, for example, the bias voltage V1 is 1V, and the bias voltage V2 and the bias voltage V3 are Vcc, such as 3.3V. The memory cells 410 and 406 in the program state P' and the program-inhibited state I, respectively, have higher bias voltages V1 and V3 than generally cause the program state P to make the potential line depth of the ground bias voltage of the adjacent memory cell 408 deeper, so The channel bit energy of the memory cell 408 is raised to have a more stable program inhibit state than the comparative example (the memory cell 406 of FIG. 7).

Compared with the comparative example, the operating method according to the embodiment can cause a higher degree of channel bit energy boost to the intermediate memory cells, and thus can be in a more stable program-inhibited state.

In the embodiment, the bit lines provided with the bias voltages V1 , V2 and V3 belong to different bit line groups respectively. For example, the bit lines may be a group design in the arrangement of 3n+1, 3n+2, 3n+3, or a group design in the arrangement of 4n+1, 4n+2, 4n+3, 4n+4 , n=0, 1, 2... etc. positive integers. Bitlines in the same group are coupled to a shared bitline or voltage source.

The operating method according to the embodiment may be applied to a selected page of a memory array of a two-dimensional NAND memory string or a three-dimensional NAND memory string.

In conclusion, although the present invention has been described above with preferred embodiments, it is not intended to limit the present invention. Various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (6)

1. A method of operating a memory array, wherein the memory array comprises a first storage unit, a second storage unit and a third storage unit, sharing a gate and sequentially arranged along the extension direction of the gate, The method of operation of the memory array includes: providing a first bias voltage to a channel of the first memory cell to program the first memory cell; providing a second bias to a channel of the second memory cell to inhibit programming of the second memory cell; and providing a third bias voltage to a channel of the third memory cell to program or inhibit programming of the third memory cell, wherein the first bias voltage is different from the third bias voltage; Wherein, the third bias voltage is used to program the third memory cell, the third bias voltage is greater than the first bias voltage, and the second bias voltage is greater than the third bias voltage. 2. The operating method of the memory array according to claim 1, wherein the second bias voltage is greater than the first bias voltage and is greater than or equal to the third bias voltage. 3. The operating method of the memory array according to claim 1, wherein the first bias, the second bias and the third bias are 0V or a positive bias. 4. The operating method of a memory array according to claim 1, wherein while the second memory cell is in a program-inhibited state, the first memory cell is in a program-inhibited state, and the third memory cell is in a program-inhibited state or a program-inhibited state state. 5. A method of operating a memory array, comprising: providing a first bit line bias to make a first memory cell of a first memory string in a programmed state; providing a second bit line bias to make a second memory cell of a second memory string a program-inhibited state; and A third bit line bias is provided to make a third memory cell of a third memory string in a programmed state or a program inhibited state, wherein the first bit line bias is different from the third bit line bias, the first A storage unit, the second storage unit and the third storage unit are sequentially arranged on a page of the memory array; Wherein, the bias voltage of the third bit line is used to make the third memory cell in the programming state, the bias voltage of the third bit line is larger than the bias voltage of the first bit line, and the bias voltage of the second bit line is larger than the bias voltage of the third bit line bias. 6. The method of claim 5, wherein the second bit line bias is greater than the first bit line bias and is greater than or equal to the third bit line bias.

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